drivers/gpio/gpio-pmic-eic-sprd.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 Spreadtrum Communications Inc.
0004  * Copyright (C) 2018 Linaro Ltd.
0005  */
0006
0007 #include <linux/gpio/driver.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014
0015 /* EIC registers definition */
0016 #define SPRD_PMIC_EIC_DATA      0x0
0017 #define SPRD_PMIC_EIC_DMSK      0x4
0018 #define SPRD_PMIC_EIC_IEV       0x14
0019 #define SPRD_PMIC_EIC_IE        0x18
0020 #define SPRD_PMIC_EIC_RIS       0x1c
0021 #define SPRD_PMIC_EIC_MIS       0x20
0022 #define SPRD_PMIC_EIC_IC        0x24
0023 #define SPRD_PMIC_EIC_TRIG      0x28
0024 #define SPRD_PMIC_EIC_CTRL0     0x40
0025
0026 /*
0027  * The PMIC EIC controller only has one bank, and each bank now can contain
0028  * 16 EICs.
0029  */
0030 #define SPRD_PMIC_EIC_PER_BANK_NR   16
0031 #define SPRD_PMIC_EIC_NR        SPRD_PMIC_EIC_PER_BANK_NR
0032 #define SPRD_PMIC_EIC_DATA_MASK     GENMASK(15, 0)
0033 #define SPRD_PMIC_EIC_BIT(x)        ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
0034 #define SPRD_PMIC_EIC_DBNC_MASK     GENMASK(11, 0)
0035
0036 /*
0037  * These registers are modified under the irq bus lock and cached to avoid
0038  * unnecessary writes in bus_sync_unlock.
0039  */
0040 enum {
0041     REG_IEV,
0042     REG_IE,
0043     REG_TRIG,
0044     CACHE_NR_REGS
0045 };
0046
0047 /**
0048  * struct sprd_pmic_eic - PMIC EIC controller
0049  * @chip: the gpio_chip structure.
0050  * @intc: the irq_chip structure.
0051  * @map:  the regmap from the parent device.
0052  * @offset: the EIC controller's offset address of the PMIC.
0053  * @reg: the array to cache the EIC registers.
0054  * @buslock: for bus lock/sync and unlock.
0055  * @irq: the interrupt number of the PMIC EIC conteroller.
0056  */
0057 struct sprd_pmic_eic {
0058     struct gpio_chip chip;
0059     struct irq_chip intc;
0060     struct regmap *map;
0061     u32 offset;
0062     u8 reg[CACHE_NR_REGS];
0063     struct mutex buslock;
0064     int irq;
0065 };
0066
0067 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset,
0068                  u16 reg, unsigned int val)
0069 {
0070     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0071     u32 shift = SPRD_PMIC_EIC_BIT(offset);
0072
0073     regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,
0074                BIT(shift), val << shift);
0075 }
0076
0077 static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset,
0078                   u16 reg)
0079 {
0080     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0081     u32 value;
0082     int ret;
0083
0084     ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
0085     if (ret)
0086         return ret;
0087
0088     return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset)));
0089 }
0090
0091 static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset)
0092 {
0093     sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1);
0094     return 0;
0095 }
0096
0097 static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset)
0098 {
0099     sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0);
0100 }
0101
0102 static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset)
0103 {
0104     return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA);
0105 }
0106
0107 static int sprd_pmic_eic_direction_input(struct gpio_chip *chip,
0108                      unsigned int offset)
0109 {
0110     /* EICs are always input, nothing need to do here. */
0111     return 0;
0112 }
0113
0114 static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset,
0115                   int value)
0116 {
0117     /* EICs are always input, nothing need to do here. */
0118 }
0119
0120 static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip,
0121                       unsigned int offset,
0122                       unsigned int debounce)
0123 {
0124     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0125     u32 reg, value;
0126     int ret;
0127
0128     reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4;
0129     ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);
0130     if (ret)
0131         return ret;
0132
0133     value &= ~SPRD_PMIC_EIC_DBNC_MASK;
0134     value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK;
0135     return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);
0136 }
0137
0138 static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset,
0139                     unsigned long config)
0140 {
0141     unsigned long param = pinconf_to_config_param(config);
0142     u32 arg = pinconf_to_config_argument(config);
0143
0144     if (param == PIN_CONFIG_INPUT_DEBOUNCE)
0145         return sprd_pmic_eic_set_debounce(chip, offset, arg);
0146
0147     return -ENOTSUPP;
0148 }
0149
0150 static void sprd_pmic_eic_irq_mask(struct irq_data *data)
0151 {
0152     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0153     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0154
0155     pmic_eic->reg[REG_IE] = 0;
0156     pmic_eic->reg[REG_TRIG] = 0;
0157 }
0158
0159 static void sprd_pmic_eic_irq_unmask(struct irq_data *data)
0160 {
0161     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0162     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0163
0164     pmic_eic->reg[REG_IE] = 1;
0165     pmic_eic->reg[REG_TRIG] = 1;
0166 }
0167
0168 static int sprd_pmic_eic_irq_set_type(struct irq_data *data,
0169                       unsigned int flow_type)
0170 {
0171     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0172     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0173
0174     switch (flow_type) {
0175     case IRQ_TYPE_LEVEL_HIGH:
0176         pmic_eic->reg[REG_IEV] = 1;
0177         break;
0178     case IRQ_TYPE_LEVEL_LOW:
0179         pmic_eic->reg[REG_IEV] = 0;
0180         break;
0181     case IRQ_TYPE_EDGE_RISING:
0182     case IRQ_TYPE_EDGE_FALLING:
0183     case IRQ_TYPE_EDGE_BOTH:
0184         /*
0185          * Will set the trigger level according to current EIC level
0186          * in irq_bus_sync_unlock() interface, so here nothing to do.
0187          */
0188         break;
0189     default:
0190         return -ENOTSUPP;
0191     }
0192
0193     return 0;
0194 }
0195
0196 static void sprd_pmic_eic_bus_lock(struct irq_data *data)
0197 {
0198     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0199     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0200
0201     mutex_lock(&pmic_eic->buslock);
0202 }
0203
0204 static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data)
0205 {
0206     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0207     struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip);
0208     u32 trigger = irqd_get_trigger_type(data);
0209     u32 offset = irqd_to_hwirq(data);
0210     int state;
0211
0212     /* Set irq type */
0213     if (trigger & IRQ_TYPE_EDGE_BOTH) {
0214         state = sprd_pmic_eic_get(chip, offset);
0215         if (state)
0216             sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
0217         else
0218             sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
0219     } else {
0220         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV,
0221                      pmic_eic->reg[REG_IEV]);
0222     }
0223
0224     /* Set irq unmask */
0225     sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE,
0226                  pmic_eic->reg[REG_IE]);
0227     /* Generate trigger start pulse for debounce EIC */
0228     sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG,
0229                  pmic_eic->reg[REG_TRIG]);
0230
0231     mutex_unlock(&pmic_eic->buslock);
0232 }
0233
0234 static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip,
0235                      unsigned int irq, unsigned int offset)
0236 {
0237     u32 trigger = irq_get_trigger_type(irq);
0238     int state, post_state;
0239
0240     if (!(trigger & IRQ_TYPE_EDGE_BOTH))
0241         return;
0242
0243     state = sprd_pmic_eic_get(chip, offset);
0244 retry:
0245     if (state)
0246         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0);
0247     else
0248         sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1);
0249
0250     post_state = sprd_pmic_eic_get(chip, offset);
0251     if (state != post_state) {
0252         dev_warn(chip->parent, "PMIC EIC level was changed.\n");
0253         state = post_state;
0254         goto retry;
0255     }
0256
0257     /* Set irq unmask */
0258     sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1);
0259     /* Generate trigger start pulse for debounce EIC */
0260     sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1);
0261 }
0262
0263 static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data)
0264 {
0265     struct sprd_pmic_eic *pmic_eic = data;
0266     struct gpio_chip *chip = &pmic_eic->chip;
0267     unsigned long status;
0268     u32 n, girq, val;
0269     int ret;
0270
0271     ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,
0272               &val);
0273     if (ret)
0274         return IRQ_RETVAL(ret);
0275
0276     status = val & SPRD_PMIC_EIC_DATA_MASK;
0277
0278     for_each_set_bit(n, &status, chip->ngpio) {
0279         /* Clear the interrupt */
0280         sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1);
0281
0282         girq = irq_find_mapping(chip->irq.domain, n);
0283         handle_nested_irq(girq);
0284
0285         /*
0286          * The PMIC EIC can only support level trigger, so we can
0287          * toggle the level trigger to emulate the edge trigger.
0288          */
0289         sprd_pmic_eic_toggle_trigger(chip, girq, n);
0290     }
0291
0292     return IRQ_HANDLED;
0293 }
0294
0295 static int sprd_pmic_eic_probe(struct platform_device *pdev)
0296 {
0297     struct gpio_irq_chip *irq;
0298     struct sprd_pmic_eic *pmic_eic;
0299     int ret;
0300
0301     pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);
0302     if (!pmic_eic)
0303         return -ENOMEM;
0304
0305     mutex_init(&pmic_eic->buslock);
0306
0307     pmic_eic->irq = platform_get_irq(pdev, 0);
0308     if (pmic_eic->irq < 0)
0309         return pmic_eic->irq;
0310
0311     pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);
0312     if (!pmic_eic->map)
0313         return -ENODEV;
0314
0315     ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);
0316     if (ret) {
0317         dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");
0318         return ret;
0319     }
0320
0321     ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,
0322                     sprd_pmic_eic_irq_handler,
0323                     IRQF_ONESHOT | IRQF_NO_SUSPEND,
0324                     dev_name(&pdev->dev), pmic_eic);
0325     if (ret) {
0326         dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");
0327         return ret;
0328     }
0329
0330     pmic_eic->chip.label = dev_name(&pdev->dev);
0331     pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;
0332     pmic_eic->chip.base = -1;
0333     pmic_eic->chip.parent = &pdev->dev;
0334     pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;
0335     pmic_eic->chip.request = sprd_pmic_eic_request;
0336     pmic_eic->chip.free = sprd_pmic_eic_free;
0337     pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
0338     pmic_eic->chip.set = sprd_pmic_eic_set;
0339     pmic_eic->chip.get = sprd_pmic_eic_get;
0340
0341     pmic_eic->intc.name = dev_name(&pdev->dev);
0342     pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
0343     pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;
0344     pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;
0345     pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;
0346     pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;
0347     pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
0348
0349     irq = &pmic_eic->chip.irq;
0350     irq->chip = &pmic_eic->intc;
0351     irq->threaded = true;
0352
0353     ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);
0354     if (ret < 0) {
0355         dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
0356         return ret;
0357     }
0358
0359     platform_set_drvdata(pdev, pmic_eic);
0360     return 0;
0361 }
0362
0363 static const struct of_device_id sprd_pmic_eic_of_match[] = {
0364     { .compatible = "sprd,sc2731-eic", },
0365     { /* end of list */ }
0366 };
0367 MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match);
0368
0369 static struct platform_driver sprd_pmic_eic_driver = {
0370     .probe = sprd_pmic_eic_probe,
0371     .driver = {
0372         .name = "sprd-pmic-eic",
0373         .of_match_table = sprd_pmic_eic_of_match,
0374     },
0375 };
0376
0377 module_platform_driver(sprd_pmic_eic_driver);
0378
0379 MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");
0380 MODULE_LICENSE("GPL v2");