drivers/gpio/gpio-pl061.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2008, 2009 Provigent Ltd.
0004  *
0005  * Author: Baruch Siach <baruch@tkos.co.il>
0006  *
0007  * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
0008  *
0009  * Data sheet: ARM DDI 0190B, September 2000
0010  */
0011 #include <linux/spinlock.h>
0012 #include <linux/errno.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/ioport.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/irq.h>
0018 #include <linux/irqchip/chained_irq.h>
0019 #include <linux/module.h>
0020 #include <linux/bitops.h>
0021 #include <linux/gpio/driver.h>
0022 #include <linux/device.h>
0023 #include <linux/amba/bus.h>
0024 #include <linux/slab.h>
0025 #include <linux/pinctrl/consumer.h>
0026 #include <linux/pm.h>
0027
0028 #define GPIODIR 0x400
0029 #define GPIOIS  0x404
0030 #define GPIOIBE 0x408
0031 #define GPIOIEV 0x40C
0032 #define GPIOIE  0x410
0033 #define GPIORIS 0x414
0034 #define GPIOMIS 0x418
0035 #define GPIOIC  0x41C
0036
0037 #define PL061_GPIO_NR   8
0038
0039 #ifdef CONFIG_PM
0040 struct pl061_context_save_regs {
0041     u8 gpio_data;
0042     u8 gpio_dir;
0043     u8 gpio_is;
0044     u8 gpio_ibe;
0045     u8 gpio_iev;
0046     u8 gpio_ie;
0047 };
0048 #endif
0049
0050 struct pl061 {
0051     raw_spinlock_t      lock;
0052
0053     void __iomem        *base;
0054     struct gpio_chip    gc;
0055     int         parent_irq;
0056
0057 #ifdef CONFIG_PM
0058     struct pl061_context_save_regs csave_regs;
0059 #endif
0060 };
0061
0062 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
0063 {
0064     struct pl061 *pl061 = gpiochip_get_data(gc);
0065
0066     if (readb(pl061->base + GPIODIR) & BIT(offset))
0067         return GPIO_LINE_DIRECTION_OUT;
0068
0069     return GPIO_LINE_DIRECTION_IN;
0070 }
0071
0072 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
0073 {
0074     struct pl061 *pl061 = gpiochip_get_data(gc);
0075     unsigned long flags;
0076     unsigned char gpiodir;
0077
0078     raw_spin_lock_irqsave(&pl061->lock, flags);
0079     gpiodir = readb(pl061->base + GPIODIR);
0080     gpiodir &= ~(BIT(offset));
0081     writeb(gpiodir, pl061->base + GPIODIR);
0082     raw_spin_unlock_irqrestore(&pl061->lock, flags);
0083
0084     return 0;
0085 }
0086
0087 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
0088         int value)
0089 {
0090     struct pl061 *pl061 = gpiochip_get_data(gc);
0091     unsigned long flags;
0092     unsigned char gpiodir;
0093
0094     raw_spin_lock_irqsave(&pl061->lock, flags);
0095     writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
0096     gpiodir = readb(pl061->base + GPIODIR);
0097     gpiodir |= BIT(offset);
0098     writeb(gpiodir, pl061->base + GPIODIR);
0099
0100     /*
0101      * gpio value is set again, because pl061 doesn't allow to set value of
0102      * a gpio pin before configuring it in OUT mode.
0103      */
0104     writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
0105     raw_spin_unlock_irqrestore(&pl061->lock, flags);
0106
0107     return 0;
0108 }
0109
0110 static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
0111 {
0112     struct pl061 *pl061 = gpiochip_get_data(gc);
0113
0114     return !!readb(pl061->base + (BIT(offset + 2)));
0115 }
0116
0117 static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
0118 {
0119     struct pl061 *pl061 = gpiochip_get_data(gc);
0120
0121     writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
0122 }
0123
0124 static int pl061_irq_type(struct irq_data *d, unsigned trigger)
0125 {
0126     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0127     struct pl061 *pl061 = gpiochip_get_data(gc);
0128     int offset = irqd_to_hwirq(d);
0129     unsigned long flags;
0130     u8 gpiois, gpioibe, gpioiev;
0131     u8 bit = BIT(offset);
0132
0133     if (offset < 0 || offset >= PL061_GPIO_NR)
0134         return -EINVAL;
0135
0136     if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
0137         (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
0138     {
0139         dev_err(gc->parent,
0140             "trying to configure line %d for both level and edge "
0141             "detection, choose one!\n",
0142             offset);
0143         return -EINVAL;
0144     }
0145
0146
0147     raw_spin_lock_irqsave(&pl061->lock, flags);
0148
0149     gpioiev = readb(pl061->base + GPIOIEV);
0150     gpiois = readb(pl061->base + GPIOIS);
0151     gpioibe = readb(pl061->base + GPIOIBE);
0152
0153     if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
0154         bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
0155
0156         /* Disable edge detection */
0157         gpioibe &= ~bit;
0158         /* Enable level detection */
0159         gpiois |= bit;
0160         /* Select polarity */
0161         if (polarity)
0162             gpioiev |= bit;
0163         else
0164             gpioiev &= ~bit;
0165         irq_set_handler_locked(d, handle_level_irq);
0166         dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
0167             offset,
0168             polarity ? "HIGH" : "LOW");
0169     } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
0170         /* Disable level detection */
0171         gpiois &= ~bit;
0172         /* Select both edges, setting this makes GPIOEV be ignored */
0173         gpioibe |= bit;
0174         irq_set_handler_locked(d, handle_edge_irq);
0175         dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
0176     } else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
0177            (trigger & IRQ_TYPE_EDGE_FALLING)) {
0178         bool rising = trigger & IRQ_TYPE_EDGE_RISING;
0179
0180         /* Disable level detection */
0181         gpiois &= ~bit;
0182         /* Clear detection on both edges */
0183         gpioibe &= ~bit;
0184         /* Select edge */
0185         if (rising)
0186             gpioiev |= bit;
0187         else
0188             gpioiev &= ~bit;
0189         irq_set_handler_locked(d, handle_edge_irq);
0190         dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
0191             offset,
0192             rising ? "RISING" : "FALLING");
0193     } else {
0194         /* No trigger: disable everything */
0195         gpiois &= ~bit;
0196         gpioibe &= ~bit;
0197         gpioiev &= ~bit;
0198         irq_set_handler_locked(d, handle_bad_irq);
0199         dev_warn(gc->parent, "no trigger selected for line %d\n",
0200              offset);
0201     }
0202
0203     writeb(gpiois, pl061->base + GPIOIS);
0204     writeb(gpioibe, pl061->base + GPIOIBE);
0205     writeb(gpioiev, pl061->base + GPIOIEV);
0206
0207     raw_spin_unlock_irqrestore(&pl061->lock, flags);
0208
0209     return 0;
0210 }
0211
0212 static void pl061_irq_handler(struct irq_desc *desc)
0213 {
0214     unsigned long pending;
0215     int offset;
0216     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0217     struct pl061 *pl061 = gpiochip_get_data(gc);
0218     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0219
0220     chained_irq_enter(irqchip, desc);
0221
0222     pending = readb(pl061->base + GPIOMIS);
0223     if (pending) {
0224         for_each_set_bit(offset, &pending, PL061_GPIO_NR)
0225             generic_handle_domain_irq(gc->irq.domain,
0226                           offset);
0227     }
0228
0229     chained_irq_exit(irqchip, desc);
0230 }
0231
0232 static void pl061_irq_mask(struct irq_data *d)
0233 {
0234     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0235     struct pl061 *pl061 = gpiochip_get_data(gc);
0236     u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
0237     u8 gpioie;
0238
0239     raw_spin_lock(&pl061->lock);
0240     gpioie = readb(pl061->base + GPIOIE) & ~mask;
0241     writeb(gpioie, pl061->base + GPIOIE);
0242     raw_spin_unlock(&pl061->lock);
0243
0244     gpiochip_disable_irq(gc, d->hwirq);
0245 }
0246
0247 static void pl061_irq_unmask(struct irq_data *d)
0248 {
0249     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0250     struct pl061 *pl061 = gpiochip_get_data(gc);
0251     u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
0252     u8 gpioie;
0253
0254     gpiochip_enable_irq(gc, d->hwirq);
0255
0256     raw_spin_lock(&pl061->lock);
0257     gpioie = readb(pl061->base + GPIOIE) | mask;
0258     writeb(gpioie, pl061->base + GPIOIE);
0259     raw_spin_unlock(&pl061->lock);
0260 }
0261
0262 /**
0263  * pl061_irq_ack() - ACK an edge IRQ
0264  * @d: IRQ data for this IRQ
0265  *
0266  * This gets called from the edge IRQ handler to ACK the edge IRQ
0267  * in the GPIOIC (interrupt-clear) register. For level IRQs this is
0268  * not needed: these go away when the level signal goes away.
0269  */
0270 static void pl061_irq_ack(struct irq_data *d)
0271 {
0272     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0273     struct pl061 *pl061 = gpiochip_get_data(gc);
0274     u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
0275
0276     raw_spin_lock(&pl061->lock);
0277     writeb(mask, pl061->base + GPIOIC);
0278     raw_spin_unlock(&pl061->lock);
0279 }
0280
0281 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
0282 {
0283     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0284     struct pl061 *pl061 = gpiochip_get_data(gc);
0285
0286     return irq_set_irq_wake(pl061->parent_irq, state);
0287 }
0288
0289 static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p)
0290 {
0291     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0292
0293     seq_printf(p, dev_name(gc->parent));
0294 }
0295
0296 static const struct irq_chip pl061_irq_chip = {
0297     .irq_ack        = pl061_irq_ack,
0298     .irq_mask       = pl061_irq_mask,
0299     .irq_unmask     = pl061_irq_unmask,
0300     .irq_set_type       = pl061_irq_type,
0301     .irq_set_wake       = pl061_irq_set_wake,
0302     .irq_print_chip     = pl061_irq_print_chip,
0303     .flags          = IRQCHIP_IMMUTABLE,
0304     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0305 };
0306
0307 static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
0308 {
0309     struct device *dev = &adev->dev;
0310     struct pl061 *pl061;
0311     struct gpio_irq_chip *girq;
0312     int ret, irq;
0313
0314     pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
0315     if (pl061 == NULL)
0316         return -ENOMEM;
0317
0318     pl061->base = devm_ioremap_resource(dev, &adev->res);
0319     if (IS_ERR(pl061->base))
0320         return PTR_ERR(pl061->base);
0321
0322     raw_spin_lock_init(&pl061->lock);
0323     pl061->gc.request = gpiochip_generic_request;
0324     pl061->gc.free = gpiochip_generic_free;
0325     pl061->gc.base = -1;
0326     pl061->gc.get_direction = pl061_get_direction;
0327     pl061->gc.direction_input = pl061_direction_input;
0328     pl061->gc.direction_output = pl061_direction_output;
0329     pl061->gc.get = pl061_get_value;
0330     pl061->gc.set = pl061_set_value;
0331     pl061->gc.ngpio = PL061_GPIO_NR;
0332     pl061->gc.label = dev_name(dev);
0333     pl061->gc.parent = dev;
0334     pl061->gc.owner = THIS_MODULE;
0335
0336     /*
0337      * irq_chip support
0338      */
0339     writeb(0, pl061->base + GPIOIE); /* disable irqs */
0340     irq = adev->irq[0];
0341     if (!irq)
0342         dev_warn(&adev->dev, "IRQ support disabled\n");
0343     pl061->parent_irq = irq;
0344
0345     girq = &pl061->gc.irq;
0346     gpio_irq_chip_set_chip(girq, &pl061_irq_chip);
0347     girq->parent_handler = pl061_irq_handler;
0348     girq->num_parents = 1;
0349     girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
0350                      GFP_KERNEL);
0351     if (!girq->parents)
0352         return -ENOMEM;
0353     girq->parents[0] = irq;
0354     girq->default_type = IRQ_TYPE_NONE;
0355     girq->handler = handle_bad_irq;
0356
0357     ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
0358     if (ret)
0359         return ret;
0360
0361     amba_set_drvdata(adev, pl061);
0362     dev_info(dev, "PL061 GPIO chip registered\n");
0363
0364     return 0;
0365 }
0366
0367 #ifdef CONFIG_PM
0368 static int pl061_suspend(struct device *dev)
0369 {
0370     struct pl061 *pl061 = dev_get_drvdata(dev);
0371     int offset;
0372
0373     pl061->csave_regs.gpio_data = 0;
0374     pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
0375     pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
0376     pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
0377     pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
0378     pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
0379
0380     for (offset = 0; offset < PL061_GPIO_NR; offset++) {
0381         if (pl061->csave_regs.gpio_dir & (BIT(offset)))
0382             pl061->csave_regs.gpio_data |=
0383                 pl061_get_value(&pl061->gc, offset) << offset;
0384     }
0385
0386     return 0;
0387 }
0388
0389 static int pl061_resume(struct device *dev)
0390 {
0391     struct pl061 *pl061 = dev_get_drvdata(dev);
0392     int offset;
0393
0394     for (offset = 0; offset < PL061_GPIO_NR; offset++) {
0395         if (pl061->csave_regs.gpio_dir & (BIT(offset)))
0396             pl061_direction_output(&pl061->gc, offset,
0397                     pl061->csave_regs.gpio_data &
0398                     (BIT(offset)));
0399         else
0400             pl061_direction_input(&pl061->gc, offset);
0401     }
0402
0403     writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
0404     writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
0405     writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
0406     writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
0407
0408     return 0;
0409 }
0410
0411 static const struct dev_pm_ops pl061_dev_pm_ops = {
0412     .suspend = pl061_suspend,
0413     .resume = pl061_resume,
0414     .freeze = pl061_suspend,
0415     .restore = pl061_resume,
0416 };
0417 #endif
0418
0419 static const struct amba_id pl061_ids[] = {
0420     {
0421         .id = 0x00041061,
0422         .mask   = 0x000fffff,
0423     },
0424     { 0, 0 },
0425 };
0426 MODULE_DEVICE_TABLE(amba, pl061_ids);
0427
0428 static struct amba_driver pl061_gpio_driver = {
0429     .drv = {
0430         .name   = "pl061_gpio",
0431 #ifdef CONFIG_PM
0432         .pm = &pl061_dev_pm_ops,
0433 #endif
0434     },
0435     .id_table   = pl061_ids,
0436     .probe      = pl061_probe,
0437 };
0438 module_amba_driver(pl061_gpio_driver);
0439
0440 MODULE_LICENSE("GPL v2");