drivers/gpio/gpio-pch.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
0004  */
0005 #include <linux/bits.h>
0006 #include <linux/gpio/driver.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/pci.h>
0012 #include <linux/slab.h>
0013
0014 #define PCH_EDGE_FALLING    0
0015 #define PCH_EDGE_RISING     1
0016 #define PCH_LEVEL_L     2
0017 #define PCH_LEVEL_H     3
0018 #define PCH_EDGE_BOTH       4
0019 #define PCH_IM_MASK     GENMASK(2, 0)
0020
0021 #define PCH_IRQ_BASE        24
0022
0023 struct pch_regs {
0024     u32 ien;
0025     u32 istatus;
0026     u32 idisp;
0027     u32 iclr;
0028     u32 imask;
0029     u32 imaskclr;
0030     u32 po;
0031     u32 pi;
0032     u32 pm;
0033     u32 im0;
0034     u32 im1;
0035     u32 reserved[3];
0036     u32 gpio_use_sel;
0037     u32 reset;
0038 };
0039
0040 #define PCI_DEVICE_ID_INTEL_EG20T_PCH       0x8803
0041 #define PCI_DEVICE_ID_ROHM_ML7223m_IOH      0x8014
0042 #define PCI_DEVICE_ID_ROHM_ML7223n_IOH      0x8043
0043 #define PCI_DEVICE_ID_ROHM_EG20T_PCH        0x8803
0044
0045 enum pch_type_t {
0046     INTEL_EG20T_PCH,
0047     OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
0048     OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
0049 };
0050
0051 /* Specifies number of GPIO PINS */
0052 static int gpio_pins[] = {
0053     [INTEL_EG20T_PCH] = 12,
0054     [OKISEMI_ML7223m_IOH] = 8,
0055     [OKISEMI_ML7223n_IOH] = 8,
0056 };
0057
0058 /**
0059  * struct pch_gpio_reg_data - The register store data.
0060  * @ien_reg:    To store contents of IEN register.
0061  * @imask_reg:  To store contents of IMASK register.
0062  * @po_reg: To store contents of PO register.
0063  * @pm_reg: To store contents of PM register.
0064  * @im0_reg:    To store contents of IM0 register.
0065  * @im1_reg:    To store contents of IM1 register.
0066  * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
0067  *             (Only ML7223 Bus-n)
0068  */
0069 struct pch_gpio_reg_data {
0070     u32 ien_reg;
0071     u32 imask_reg;
0072     u32 po_reg;
0073     u32 pm_reg;
0074     u32 im0_reg;
0075     u32 im1_reg;
0076     u32 gpio_use_sel_reg;
0077 };
0078
0079 /**
0080  * struct pch_gpio - GPIO private data structure.
0081  * @base:           PCI base address of Memory mapped I/O register.
0082  * @reg:            Memory mapped PCH GPIO register list.
0083  * @dev:            Pointer to device structure.
0084  * @gpio:           Data for GPIO infrastructure.
0085  * @pch_gpio_reg:       Memory mapped Register data is saved here
0086  *              when suspend.
0087  * @lock:           Used for register access protection
0088  * @irq_base:       Save base of IRQ number for interrupt
0089  * @ioh:        IOH ID
0090  * @spinlock:       Used for register access protection
0091  */
0092 struct pch_gpio {
0093     void __iomem *base;
0094     struct pch_regs __iomem *reg;
0095     struct device *dev;
0096     struct gpio_chip gpio;
0097     struct pch_gpio_reg_data pch_gpio_reg;
0098     int irq_base;
0099     enum pch_type_t ioh;
0100     spinlock_t spinlock;
0101 };
0102
0103 static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
0104 {
0105     u32 reg_val;
0106     struct pch_gpio *chip = gpiochip_get_data(gpio);
0107     unsigned long flags;
0108
0109     spin_lock_irqsave(&chip->spinlock, flags);
0110     reg_val = ioread32(&chip->reg->po);
0111     if (val)
0112         reg_val |= BIT(nr);
0113     else
0114         reg_val &= ~BIT(nr);
0115
0116     iowrite32(reg_val, &chip->reg->po);
0117     spin_unlock_irqrestore(&chip->spinlock, flags);
0118 }
0119
0120 static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
0121 {
0122     struct pch_gpio *chip = gpiochip_get_data(gpio);
0123
0124     return !!(ioread32(&chip->reg->pi) & BIT(nr));
0125 }
0126
0127 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
0128                      int val)
0129 {
0130     struct pch_gpio *chip = gpiochip_get_data(gpio);
0131     u32 pm;
0132     u32 reg_val;
0133     unsigned long flags;
0134
0135     spin_lock_irqsave(&chip->spinlock, flags);
0136
0137     reg_val = ioread32(&chip->reg->po);
0138     if (val)
0139         reg_val |= BIT(nr);
0140     else
0141         reg_val &= ~BIT(nr);
0142     iowrite32(reg_val, &chip->reg->po);
0143
0144     pm = ioread32(&chip->reg->pm);
0145     pm &= BIT(gpio_pins[chip->ioh]) - 1;
0146     pm |= BIT(nr);
0147     iowrite32(pm, &chip->reg->pm);
0148
0149     spin_unlock_irqrestore(&chip->spinlock, flags);
0150
0151     return 0;
0152 }
0153
0154 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
0155 {
0156     struct pch_gpio *chip = gpiochip_get_data(gpio);
0157     u32 pm;
0158     unsigned long flags;
0159
0160     spin_lock_irqsave(&chip->spinlock, flags);
0161     pm = ioread32(&chip->reg->pm);
0162     pm &= BIT(gpio_pins[chip->ioh]) - 1;
0163     pm &= ~BIT(nr);
0164     iowrite32(pm, &chip->reg->pm);
0165     spin_unlock_irqrestore(&chip->spinlock, flags);
0166
0167     return 0;
0168 }
0169
0170 /*
0171  * Save register configuration and disable interrupts.
0172  */
0173 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
0174 {
0175     chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
0176     chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
0177     chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
0178     chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
0179     chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
0180     if (chip->ioh == INTEL_EG20T_PCH)
0181         chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
0182     if (chip->ioh == OKISEMI_ML7223n_IOH)
0183         chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
0184 }
0185
0186 /*
0187  * This function restores the register configuration of the GPIO device.
0188  */
0189 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
0190 {
0191     iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
0192     iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
0193     /* to store contents of PO register */
0194     iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
0195     /* to store contents of PM register */
0196     iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
0197     iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
0198     if (chip->ioh == INTEL_EG20T_PCH)
0199         iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
0200     if (chip->ioh == OKISEMI_ML7223n_IOH)
0201         iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
0202 }
0203
0204 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
0205 {
0206     struct pch_gpio *chip = gpiochip_get_data(gpio);
0207
0208     return chip->irq_base + offset;
0209 }
0210
0211 static void pch_gpio_setup(struct pch_gpio *chip)
0212 {
0213     struct gpio_chip *gpio = &chip->gpio;
0214
0215     gpio->label = dev_name(chip->dev);
0216     gpio->parent = chip->dev;
0217     gpio->owner = THIS_MODULE;
0218     gpio->direction_input = pch_gpio_direction_input;
0219     gpio->get = pch_gpio_get;
0220     gpio->direction_output = pch_gpio_direction_output;
0221     gpio->set = pch_gpio_set;
0222     gpio->base = -1;
0223     gpio->ngpio = gpio_pins[chip->ioh];
0224     gpio->can_sleep = false;
0225     gpio->to_irq = pch_gpio_to_irq;
0226 }
0227
0228 static int pch_irq_type(struct irq_data *d, unsigned int type)
0229 {
0230     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0231     struct pch_gpio *chip = gc->private;
0232     u32 im, im_pos, val;
0233     u32 __iomem *im_reg;
0234     unsigned long flags;
0235     int ch, irq = d->irq;
0236
0237     ch = irq - chip->irq_base;
0238     if (irq < chip->irq_base + 8) {
0239         im_reg = &chip->reg->im0;
0240         im_pos = ch - 0;
0241     } else {
0242         im_reg = &chip->reg->im1;
0243         im_pos = ch - 8;
0244     }
0245     dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
0246
0247     switch (type) {
0248     case IRQ_TYPE_EDGE_RISING:
0249         val = PCH_EDGE_RISING;
0250         break;
0251     case IRQ_TYPE_EDGE_FALLING:
0252         val = PCH_EDGE_FALLING;
0253         break;
0254     case IRQ_TYPE_EDGE_BOTH:
0255         val = PCH_EDGE_BOTH;
0256         break;
0257     case IRQ_TYPE_LEVEL_HIGH:
0258         val = PCH_LEVEL_H;
0259         break;
0260     case IRQ_TYPE_LEVEL_LOW:
0261         val = PCH_LEVEL_L;
0262         break;
0263     default:
0264         return 0;
0265     }
0266
0267     spin_lock_irqsave(&chip->spinlock, flags);
0268
0269     /* Set interrupt mode */
0270     im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
0271     iowrite32(im | (val << (im_pos * 4)), im_reg);
0272
0273     /* And the handler */
0274     if (type & IRQ_TYPE_LEVEL_MASK)
0275         irq_set_handler_locked(d, handle_level_irq);
0276     else if (type & IRQ_TYPE_EDGE_BOTH)
0277         irq_set_handler_locked(d, handle_edge_irq);
0278
0279     spin_unlock_irqrestore(&chip->spinlock, flags);
0280     return 0;
0281 }
0282
0283 static void pch_irq_unmask(struct irq_data *d)
0284 {
0285     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0286     struct pch_gpio *chip = gc->private;
0287
0288     iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
0289 }
0290
0291 static void pch_irq_mask(struct irq_data *d)
0292 {
0293     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0294     struct pch_gpio *chip = gc->private;
0295
0296     iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
0297 }
0298
0299 static void pch_irq_ack(struct irq_data *d)
0300 {
0301     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0302     struct pch_gpio *chip = gc->private;
0303
0304     iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
0305 }
0306
0307 static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
0308 {
0309     struct pch_gpio *chip = dev_id;
0310     unsigned long reg_val = ioread32(&chip->reg->istatus);
0311     int i;
0312
0313     dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);
0314
0315     reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
0316
0317     for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
0318         generic_handle_irq(chip->irq_base + i);
0319
0320     return IRQ_RETVAL(reg_val);
0321 }
0322
0323 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
0324                        unsigned int irq_start,
0325                        unsigned int num)
0326 {
0327     struct irq_chip_generic *gc;
0328     struct irq_chip_type *ct;
0329     int rv;
0330
0331     gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
0332                      chip->base, handle_simple_irq);
0333     if (!gc)
0334         return -ENOMEM;
0335
0336     gc->private = chip;
0337     ct = gc->chip_types;
0338
0339     ct->chip.irq_ack = pch_irq_ack;
0340     ct->chip.irq_mask = pch_irq_mask;
0341     ct->chip.irq_unmask = pch_irq_unmask;
0342     ct->chip.irq_set_type = pch_irq_type;
0343
0344     rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
0345                      IRQ_GC_INIT_MASK_CACHE,
0346                      IRQ_NOREQUEST | IRQ_NOPROBE, 0);
0347
0348     return rv;
0349 }
0350
0351 static int pch_gpio_probe(struct pci_dev *pdev,
0352                     const struct pci_device_id *id)
0353 {
0354     struct device *dev = &pdev->dev;
0355     s32 ret;
0356     struct pch_gpio *chip;
0357     int irq_base;
0358
0359     chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
0360     if (chip == NULL)
0361         return -ENOMEM;
0362
0363     chip->dev = dev;
0364     ret = pcim_enable_device(pdev);
0365     if (ret)
0366         return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
0367
0368     ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
0369     if (ret)
0370         return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
0371
0372     chip->base = pcim_iomap_table(pdev)[1];
0373     chip->ioh = id->driver_data;
0374     chip->reg = chip->base;
0375     pci_set_drvdata(pdev, chip);
0376     spin_lock_init(&chip->spinlock);
0377     pch_gpio_setup(chip);
0378
0379     ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
0380     if (ret)
0381         return dev_err_probe(dev, ret, "Failed to register GPIO\n");
0382
0383     irq_base = devm_irq_alloc_descs(dev, -1, 0,
0384                     gpio_pins[chip->ioh], NUMA_NO_NODE);
0385     if (irq_base < 0) {
0386         dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
0387         chip->irq_base = -1;
0388         return 0;
0389     }
0390     chip->irq_base = irq_base;
0391
0392     /* Mask all interrupts, but enable them */
0393     iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
0394     iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
0395
0396     ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
0397                    IRQF_SHARED, KBUILD_MODNAME, chip);
0398     if (ret)
0399         return dev_err_probe(dev, ret, "Failed to request IRQ\n");
0400
0401     return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
0402 }
0403
0404 static int __maybe_unused pch_gpio_suspend(struct device *dev)
0405 {
0406     struct pch_gpio *chip = dev_get_drvdata(dev);
0407     unsigned long flags;
0408
0409     spin_lock_irqsave(&chip->spinlock, flags);
0410     pch_gpio_save_reg_conf(chip);
0411     spin_unlock_irqrestore(&chip->spinlock, flags);
0412
0413     return 0;
0414 }
0415
0416 static int __maybe_unused pch_gpio_resume(struct device *dev)
0417 {
0418     struct pch_gpio *chip = dev_get_drvdata(dev);
0419     unsigned long flags;
0420
0421     spin_lock_irqsave(&chip->spinlock, flags);
0422     iowrite32(0x01, &chip->reg->reset);
0423     iowrite32(0x00, &chip->reg->reset);
0424     pch_gpio_restore_reg_conf(chip);
0425     spin_unlock_irqrestore(&chip->spinlock, flags);
0426
0427     return 0;
0428 }
0429
0430 static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
0431
0432 static const struct pci_device_id pch_gpio_pcidev_id[] = {
0433     { PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
0434     { PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
0435     { PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
0436     { PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
0437     { }
0438 };
0439 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
0440
0441 static struct pci_driver pch_gpio_driver = {
0442     .name = "pch_gpio",
0443     .id_table = pch_gpio_pcidev_id,
0444     .probe = pch_gpio_probe,
0445     .driver = {
0446         .pm = &pch_gpio_pm_ops,
0447     },
0448 };
0449
0450 module_pci_driver(pch_gpio_driver);
0451
0452 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
0453 MODULE_LICENSE("GPL v2");