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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Support functions for OMAP GPIO
0004  *
0005  * Copyright (C) 2003-2005 Nokia Corporation
0006  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
0007  *
0008  * Copyright (C) 2009 Texas Instruments
0009  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
0010  */
0011 
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/syscore_ops.h>
0016 #include <linux/err.h>
0017 #include <linux/clk.h>
0018 #include <linux/io.h>
0019 #include <linux/cpu_pm.h>
0020 #include <linux/device.h>
0021 #include <linux/pm_runtime.h>
0022 #include <linux/pm.h>
0023 #include <linux/of.h>
0024 #include <linux/of_device.h>
0025 #include <linux/gpio/driver.h>
0026 #include <linux/bitops.h>
0027 #include <linux/platform_data/gpio-omap.h>
0028 
0029 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
0030 
0031 struct gpio_regs {
0032     u32 sysconfig;
0033     u32 irqenable1;
0034     u32 irqenable2;
0035     u32 wake_en;
0036     u32 ctrl;
0037     u32 oe;
0038     u32 leveldetect0;
0039     u32 leveldetect1;
0040     u32 risingdetect;
0041     u32 fallingdetect;
0042     u32 dataout;
0043     u32 debounce;
0044     u32 debounce_en;
0045 };
0046 
0047 struct gpio_bank {
0048     void __iomem *base;
0049     const struct omap_gpio_reg_offs *regs;
0050 
0051     int irq;
0052     u32 non_wakeup_gpios;
0053     u32 enabled_non_wakeup_gpios;
0054     struct gpio_regs context;
0055     u32 saved_datain;
0056     u32 level_mask;
0057     u32 toggle_mask;
0058     raw_spinlock_t lock;
0059     raw_spinlock_t wa_lock;
0060     struct gpio_chip chip;
0061     struct clk *dbck;
0062     struct notifier_block nb;
0063     unsigned int is_suspended:1;
0064     unsigned int needs_resume:1;
0065     u32 mod_usage;
0066     u32 irq_usage;
0067     u32 dbck_enable_mask;
0068     bool dbck_enabled;
0069     bool is_mpuio;
0070     bool dbck_flag;
0071     bool loses_context;
0072     bool context_valid;
0073     int stride;
0074     u32 width;
0075     int context_loss_count;
0076 
0077     void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
0078     int (*get_context_loss_count)(struct device *dev);
0079 };
0080 
0081 #define GPIO_MOD_CTRL_BIT   BIT(0)
0082 
0083 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
0084 #define LINE_USED(line, offset) (line & (BIT(offset)))
0085 
0086 static void omap_gpio_unmask_irq(struct irq_data *d);
0087 
0088 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
0089 {
0090     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0091     return gpiochip_get_data(chip);
0092 }
0093 
0094 static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
0095 {
0096     u32 val = readl_relaxed(reg);
0097 
0098     if (set)
0099         val |= mask;
0100     else
0101         val &= ~mask;
0102 
0103     writel_relaxed(val, reg);
0104 
0105     return val;
0106 }
0107 
0108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
0109                     int is_input)
0110 {
0111     bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
0112                      BIT(gpio), is_input);
0113 }
0114 
0115 
0116 /* set data out value using dedicate set/clear register */
0117 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
0118                       int enable)
0119 {
0120     void __iomem *reg = bank->base;
0121     u32 l = BIT(offset);
0122 
0123     if (enable) {
0124         reg += bank->regs->set_dataout;
0125         bank->context.dataout |= l;
0126     } else {
0127         reg += bank->regs->clr_dataout;
0128         bank->context.dataout &= ~l;
0129     }
0130 
0131     writel_relaxed(l, reg);
0132 }
0133 
0134 /* set data out value using mask register */
0135 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
0136                        int enable)
0137 {
0138     bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
0139                           BIT(offset), enable);
0140 }
0141 
0142 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
0143 {
0144     if (bank->dbck_enable_mask && !bank->dbck_enabled) {
0145         clk_enable(bank->dbck);
0146         bank->dbck_enabled = true;
0147 
0148         writel_relaxed(bank->dbck_enable_mask,
0149                  bank->base + bank->regs->debounce_en);
0150     }
0151 }
0152 
0153 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
0154 {
0155     if (bank->dbck_enable_mask && bank->dbck_enabled) {
0156         /*
0157          * Disable debounce before cutting it's clock. If debounce is
0158          * enabled but the clock is not, GPIO module seems to be unable
0159          * to detect events and generate interrupts at least on OMAP3.
0160          */
0161         writel_relaxed(0, bank->base + bank->regs->debounce_en);
0162 
0163         clk_disable(bank->dbck);
0164         bank->dbck_enabled = false;
0165     }
0166 }
0167 
0168 /**
0169  * omap2_set_gpio_debounce - low level gpio debounce time
0170  * @bank: the gpio bank we're acting upon
0171  * @offset: the gpio number on this @bank
0172  * @debounce: debounce time to use
0173  *
0174  * OMAP's debounce time is in 31us steps
0175  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
0176  * so we need to convert and round up to the closest unit.
0177  *
0178  * Return: 0 on success, negative error otherwise.
0179  */
0180 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
0181                    unsigned debounce)
0182 {
0183     u32         val;
0184     u32         l;
0185     bool            enable = !!debounce;
0186 
0187     if (!bank->dbck_flag)
0188         return -ENOTSUPP;
0189 
0190     if (enable) {
0191         debounce = DIV_ROUND_UP(debounce, 31) - 1;
0192         if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
0193             return -EINVAL;
0194     }
0195 
0196     l = BIT(offset);
0197 
0198     clk_enable(bank->dbck);
0199     writel_relaxed(debounce, bank->base + bank->regs->debounce);
0200 
0201     val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
0202     bank->dbck_enable_mask = val;
0203 
0204     clk_disable(bank->dbck);
0205     /*
0206      * Enable debounce clock per module.
0207      * This call is mandatory because in omap_gpio_request() when
0208      * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
0209      * runtime callbck fails to turn on dbck because dbck_enable_mask
0210      * used within _gpio_dbck_enable() is still not initialized at
0211      * that point. Therefore we have to enable dbck here.
0212      */
0213     omap_gpio_dbck_enable(bank);
0214     if (bank->dbck_enable_mask) {
0215         bank->context.debounce = debounce;
0216         bank->context.debounce_en = val;
0217     }
0218 
0219     return 0;
0220 }
0221 
0222 /**
0223  * omap_clear_gpio_debounce - clear debounce settings for a gpio
0224  * @bank: the gpio bank we're acting upon
0225  * @offset: the gpio number on this @bank
0226  *
0227  * If a gpio is using debounce, then clear the debounce enable bit and if
0228  * this is the only gpio in this bank using debounce, then clear the debounce
0229  * time too. The debounce clock will also be disabled when calling this function
0230  * if this is the only gpio in the bank using debounce.
0231  */
0232 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
0233 {
0234     u32 gpio_bit = BIT(offset);
0235 
0236     if (!bank->dbck_flag)
0237         return;
0238 
0239     if (!(bank->dbck_enable_mask & gpio_bit))
0240         return;
0241 
0242     bank->dbck_enable_mask &= ~gpio_bit;
0243     bank->context.debounce_en &= ~gpio_bit;
0244         writel_relaxed(bank->context.debounce_en,
0245              bank->base + bank->regs->debounce_en);
0246 
0247     if (!bank->dbck_enable_mask) {
0248         bank->context.debounce = 0;
0249         writel_relaxed(bank->context.debounce, bank->base +
0250                  bank->regs->debounce);
0251         clk_disable(bank->dbck);
0252         bank->dbck_enabled = false;
0253     }
0254 }
0255 
0256 /*
0257  * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
0258  * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
0259  * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
0260  * are capable waking up the system from off mode.
0261  */
0262 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
0263 {
0264     u32 no_wake = bank->non_wakeup_gpios;
0265 
0266     if (no_wake)
0267         return !!(~no_wake & gpio_mask);
0268 
0269     return false;
0270 }
0271 
0272 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
0273                         unsigned trigger)
0274 {
0275     void __iomem *base = bank->base;
0276     u32 gpio_bit = BIT(gpio);
0277 
0278     omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
0279               trigger & IRQ_TYPE_LEVEL_LOW);
0280     omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
0281               trigger & IRQ_TYPE_LEVEL_HIGH);
0282 
0283     /*
0284      * We need the edge detection enabled for to allow the GPIO block
0285      * to be woken from idle state.  Set the appropriate edge detection
0286      * in addition to the level detection.
0287      */
0288     omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
0289               trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
0290     omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
0291               trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
0292 
0293     bank->context.leveldetect0 =
0294             readl_relaxed(bank->base + bank->regs->leveldetect0);
0295     bank->context.leveldetect1 =
0296             readl_relaxed(bank->base + bank->regs->leveldetect1);
0297     bank->context.risingdetect =
0298             readl_relaxed(bank->base + bank->regs->risingdetect);
0299     bank->context.fallingdetect =
0300             readl_relaxed(bank->base + bank->regs->fallingdetect);
0301 
0302     bank->level_mask = bank->context.leveldetect0 |
0303                bank->context.leveldetect1;
0304 
0305     /* This part needs to be executed always for OMAP{34xx, 44xx} */
0306     if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
0307         /*
0308          * Log the edge gpio and manually trigger the IRQ
0309          * after resume if the input level changes
0310          * to avoid irq lost during PER RET/OFF mode
0311          * Applies for omap2 non-wakeup gpio and all omap3 gpios
0312          */
0313         if (trigger & IRQ_TYPE_EDGE_BOTH)
0314             bank->enabled_non_wakeup_gpios |= gpio_bit;
0315         else
0316             bank->enabled_non_wakeup_gpios &= ~gpio_bit;
0317     }
0318 }
0319 
0320 /*
0321  * This only applies to chips that can't do both rising and falling edge
0322  * detection at once.  For all other chips, this function is a noop.
0323  */
0324 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
0325 {
0326     if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
0327         void __iomem *reg = bank->base + bank->regs->irqctrl;
0328 
0329         writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
0330     }
0331 }
0332 
0333 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
0334                     unsigned trigger)
0335 {
0336     void __iomem *reg = bank->base;
0337     u32 l = 0;
0338 
0339     if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
0340         omap_set_gpio_trigger(bank, gpio, trigger);
0341     } else if (bank->regs->irqctrl) {
0342         reg += bank->regs->irqctrl;
0343 
0344         l = readl_relaxed(reg);
0345         if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
0346             bank->toggle_mask |= BIT(gpio);
0347         if (trigger & IRQ_TYPE_EDGE_RISING)
0348             l |= BIT(gpio);
0349         else if (trigger & IRQ_TYPE_EDGE_FALLING)
0350             l &= ~(BIT(gpio));
0351         else
0352             return -EINVAL;
0353 
0354         writel_relaxed(l, reg);
0355     } else if (bank->regs->edgectrl1) {
0356         if (gpio & 0x08)
0357             reg += bank->regs->edgectrl2;
0358         else
0359             reg += bank->regs->edgectrl1;
0360 
0361         gpio &= 0x07;
0362         l = readl_relaxed(reg);
0363         l &= ~(3 << (gpio << 1));
0364         if (trigger & IRQ_TYPE_EDGE_RISING)
0365             l |= 2 << (gpio << 1);
0366         if (trigger & IRQ_TYPE_EDGE_FALLING)
0367             l |= BIT(gpio << 1);
0368         writel_relaxed(l, reg);
0369     }
0370     return 0;
0371 }
0372 
0373 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
0374 {
0375     if (bank->regs->pinctrl) {
0376         void __iomem *reg = bank->base + bank->regs->pinctrl;
0377 
0378         /* Claim the pin for MPU */
0379         writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
0380     }
0381 
0382     if (bank->regs->ctrl && !BANK_USED(bank)) {
0383         void __iomem *reg = bank->base + bank->regs->ctrl;
0384         u32 ctrl;
0385 
0386         ctrl = readl_relaxed(reg);
0387         /* Module is enabled, clocks are not gated */
0388         ctrl &= ~GPIO_MOD_CTRL_BIT;
0389         writel_relaxed(ctrl, reg);
0390         bank->context.ctrl = ctrl;
0391     }
0392 }
0393 
0394 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
0395 {
0396     if (bank->regs->ctrl && !BANK_USED(bank)) {
0397         void __iomem *reg = bank->base + bank->regs->ctrl;
0398         u32 ctrl;
0399 
0400         ctrl = readl_relaxed(reg);
0401         /* Module is disabled, clocks are gated */
0402         ctrl |= GPIO_MOD_CTRL_BIT;
0403         writel_relaxed(ctrl, reg);
0404         bank->context.ctrl = ctrl;
0405     }
0406 }
0407 
0408 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
0409 {
0410     void __iomem *reg = bank->base + bank->regs->direction;
0411 
0412     return readl_relaxed(reg) & BIT(offset);
0413 }
0414 
0415 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
0416 {
0417     if (!LINE_USED(bank->mod_usage, offset)) {
0418         omap_enable_gpio_module(bank, offset);
0419         omap_set_gpio_direction(bank, offset, 1);
0420     }
0421     bank->irq_usage |= BIT(offset);
0422 }
0423 
0424 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
0425 {
0426     struct gpio_bank *bank = omap_irq_data_get_bank(d);
0427     int retval;
0428     unsigned long flags;
0429     unsigned offset = d->hwirq;
0430 
0431     if (type & ~IRQ_TYPE_SENSE_MASK)
0432         return -EINVAL;
0433 
0434     if (!bank->regs->leveldetect0 &&
0435         (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
0436         return -EINVAL;
0437 
0438     raw_spin_lock_irqsave(&bank->lock, flags);
0439     retval = omap_set_gpio_triggering(bank, offset, type);
0440     if (retval) {
0441         raw_spin_unlock_irqrestore(&bank->lock, flags);
0442         goto error;
0443     }
0444     omap_gpio_init_irq(bank, offset);
0445     if (!omap_gpio_is_input(bank, offset)) {
0446         raw_spin_unlock_irqrestore(&bank->lock, flags);
0447         retval = -EINVAL;
0448         goto error;
0449     }
0450     raw_spin_unlock_irqrestore(&bank->lock, flags);
0451 
0452     if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
0453         irq_set_handler_locked(d, handle_level_irq);
0454     else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0455         /*
0456          * Edge IRQs are already cleared/acked in irq_handler and
0457          * not need to be masked, as result handle_edge_irq()
0458          * logic is excessed here and may cause lose of interrupts.
0459          * So just use handle_simple_irq.
0460          */
0461         irq_set_handler_locked(d, handle_simple_irq);
0462 
0463     return 0;
0464 
0465 error:
0466     return retval;
0467 }
0468 
0469 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
0470 {
0471     void __iomem *reg = bank->base;
0472 
0473     reg += bank->regs->irqstatus;
0474     writel_relaxed(gpio_mask, reg);
0475 
0476     /* Workaround for clearing DSP GPIO interrupts to allow retention */
0477     if (bank->regs->irqstatus2) {
0478         reg = bank->base + bank->regs->irqstatus2;
0479         writel_relaxed(gpio_mask, reg);
0480     }
0481 
0482     /* Flush posted write for the irq status to avoid spurious interrupts */
0483     readl_relaxed(reg);
0484 }
0485 
0486 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
0487                          unsigned offset)
0488 {
0489     omap_clear_gpio_irqbank(bank, BIT(offset));
0490 }
0491 
0492 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
0493 {
0494     void __iomem *reg = bank->base;
0495     u32 l;
0496     u32 mask = (BIT(bank->width)) - 1;
0497 
0498     reg += bank->regs->irqenable;
0499     l = readl_relaxed(reg);
0500     if (bank->regs->irqenable_inv)
0501         l = ~l;
0502     l &= mask;
0503     return l;
0504 }
0505 
0506 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
0507                        unsigned offset, int enable)
0508 {
0509     void __iomem *reg = bank->base;
0510     u32 gpio_mask = BIT(offset);
0511 
0512     if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
0513         if (enable) {
0514             reg += bank->regs->set_irqenable;
0515             bank->context.irqenable1 |= gpio_mask;
0516         } else {
0517             reg += bank->regs->clr_irqenable;
0518             bank->context.irqenable1 &= ~gpio_mask;
0519         }
0520         writel_relaxed(gpio_mask, reg);
0521     } else {
0522         bank->context.irqenable1 =
0523             omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
0524                       enable ^ bank->regs->irqenable_inv);
0525     }
0526 
0527     /*
0528      * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
0529      * note requiring correlation between the IRQ enable registers and
0530      * the wakeup registers.  In any case, we want wakeup from idle
0531      * enabled for the GPIOs which support this feature.
0532      */
0533     if (bank->regs->wkup_en &&
0534         (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
0535         bank->context.wake_en =
0536             omap_gpio_rmw(bank->base + bank->regs->wkup_en,
0537                       gpio_mask, enable);
0538     }
0539 }
0540 
0541 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
0542 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
0543 {
0544     struct gpio_bank *bank = omap_irq_data_get_bank(d);
0545 
0546     return irq_set_irq_wake(bank->irq, enable);
0547 }
0548 
0549 /*
0550  * We need to unmask the GPIO bank interrupt as soon as possible to
0551  * avoid missing GPIO interrupts for other lines in the bank.
0552  * Then we need to mask-read-clear-unmask the triggered GPIO lines
0553  * in the bank to avoid missing nested interrupts for a GPIO line.
0554  * If we wait to unmask individual GPIO lines in the bank after the
0555  * line's interrupt handler has been run, we may miss some nested
0556  * interrupts.
0557  */
0558 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
0559 {
0560     void __iomem *isr_reg = NULL;
0561     u32 enabled, isr, edge;
0562     unsigned int bit;
0563     struct gpio_bank *bank = gpiobank;
0564     unsigned long wa_lock_flags;
0565     unsigned long lock_flags;
0566 
0567     isr_reg = bank->base + bank->regs->irqstatus;
0568     if (WARN_ON(!isr_reg))
0569         goto exit;
0570 
0571     if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
0572               "gpio irq%i while runtime suspended?\n", irq))
0573         return IRQ_NONE;
0574 
0575     while (1) {
0576         raw_spin_lock_irqsave(&bank->lock, lock_flags);
0577 
0578         enabled = omap_get_gpio_irqbank_mask(bank);
0579         isr = readl_relaxed(isr_reg) & enabled;
0580 
0581         /*
0582          * Clear edge sensitive interrupts before calling handler(s)
0583          * so subsequent edge transitions are not missed while the
0584          * handlers are running.
0585          */
0586         edge = isr & ~bank->level_mask;
0587         if (edge)
0588             omap_clear_gpio_irqbank(bank, edge);
0589 
0590         raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
0591 
0592         if (!isr)
0593             break;
0594 
0595         while (isr) {
0596             bit = __ffs(isr);
0597             isr &= ~(BIT(bit));
0598 
0599             raw_spin_lock_irqsave(&bank->lock, lock_flags);
0600             /*
0601              * Some chips can't respond to both rising and falling
0602              * at the same time.  If this irq was requested with
0603              * both flags, we need to flip the ICR data for the IRQ
0604              * to respond to the IRQ for the opposite direction.
0605              * This will be indicated in the bank toggle_mask.
0606              */
0607             if (bank->toggle_mask & (BIT(bit)))
0608                 omap_toggle_gpio_edge_triggering(bank, bit);
0609 
0610             raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
0611 
0612             raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
0613 
0614             generic_handle_domain_irq(bank->chip.irq.domain, bit);
0615 
0616             raw_spin_unlock_irqrestore(&bank->wa_lock,
0617                            wa_lock_flags);
0618         }
0619     }
0620 exit:
0621     return IRQ_HANDLED;
0622 }
0623 
0624 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
0625 {
0626     struct gpio_bank *bank = omap_irq_data_get_bank(d);
0627     unsigned long flags;
0628     unsigned offset = d->hwirq;
0629 
0630     raw_spin_lock_irqsave(&bank->lock, flags);
0631 
0632     if (!LINE_USED(bank->mod_usage, offset))
0633         omap_set_gpio_direction(bank, offset, 1);
0634     omap_enable_gpio_module(bank, offset);
0635     bank->irq_usage |= BIT(offset);
0636 
0637     raw_spin_unlock_irqrestore(&bank->lock, flags);
0638     omap_gpio_unmask_irq(d);
0639 
0640     return 0;
0641 }
0642 
0643 static void omap_gpio_irq_shutdown(struct irq_data *d)
0644 {
0645     struct gpio_bank *bank = omap_irq_data_get_bank(d);
0646     unsigned long flags;
0647     unsigned offset = d->hwirq;
0648 
0649     raw_spin_lock_irqsave(&bank->lock, flags);
0650     bank->irq_usage &= ~(BIT(offset));
0651     omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
0652     omap_clear_gpio_irqstatus(bank, offset);
0653     omap_set_gpio_irqenable(bank, offset, 0);
0654     if (!LINE_USED(bank->mod_usage, offset))
0655         omap_clear_gpio_debounce(bank, offset);
0656     omap_disable_gpio_module(bank, offset);
0657     raw_spin_unlock_irqrestore(&bank->lock, flags);
0658 }
0659 
0660 static void omap_gpio_irq_bus_lock(struct irq_data *data)
0661 {
0662     struct gpio_bank *bank = omap_irq_data_get_bank(data);
0663 
0664     pm_runtime_get_sync(bank->chip.parent);
0665 }
0666 
0667 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
0668 {
0669     struct gpio_bank *bank = omap_irq_data_get_bank(data);
0670 
0671     pm_runtime_put(bank->chip.parent);
0672 }
0673 
0674 static void omap_gpio_mask_irq(struct irq_data *d)
0675 {
0676     struct gpio_bank *bank = omap_irq_data_get_bank(d);
0677     unsigned offset = d->hwirq;
0678     unsigned long flags;
0679 
0680     raw_spin_lock_irqsave(&bank->lock, flags);
0681     omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
0682     omap_set_gpio_irqenable(bank, offset, 0);
0683     raw_spin_unlock_irqrestore(&bank->lock, flags);
0684 }
0685 
0686 static void omap_gpio_unmask_irq(struct irq_data *d)
0687 {
0688     struct gpio_bank *bank = omap_irq_data_get_bank(d);
0689     unsigned offset = d->hwirq;
0690     u32 trigger = irqd_get_trigger_type(d);
0691     unsigned long flags;
0692 
0693     raw_spin_lock_irqsave(&bank->lock, flags);
0694     omap_set_gpio_irqenable(bank, offset, 1);
0695 
0696     /*
0697      * For level-triggered GPIOs, clearing must be done after the source
0698      * is cleared, thus after the handler has run. OMAP4 needs this done
0699      * after enabing the interrupt to clear the wakeup status.
0700      */
0701     if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
0702         trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
0703         omap_clear_gpio_irqstatus(bank, offset);
0704 
0705     if (trigger)
0706         omap_set_gpio_triggering(bank, offset, trigger);
0707 
0708     raw_spin_unlock_irqrestore(&bank->lock, flags);
0709 }
0710 
0711 /*---------------------------------------------------------------------*/
0712 
0713 static int omap_mpuio_suspend_noirq(struct device *dev)
0714 {
0715     struct gpio_bank    *bank = dev_get_drvdata(dev);
0716     void __iomem        *mask_reg = bank->base +
0717                     OMAP_MPUIO_GPIO_MASKIT / bank->stride;
0718     unsigned long       flags;
0719 
0720     raw_spin_lock_irqsave(&bank->lock, flags);
0721     writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
0722     raw_spin_unlock_irqrestore(&bank->lock, flags);
0723 
0724     return 0;
0725 }
0726 
0727 static int omap_mpuio_resume_noirq(struct device *dev)
0728 {
0729     struct gpio_bank    *bank = dev_get_drvdata(dev);
0730     void __iomem        *mask_reg = bank->base +
0731                     OMAP_MPUIO_GPIO_MASKIT / bank->stride;
0732     unsigned long       flags;
0733 
0734     raw_spin_lock_irqsave(&bank->lock, flags);
0735     writel_relaxed(bank->context.wake_en, mask_reg);
0736     raw_spin_unlock_irqrestore(&bank->lock, flags);
0737 
0738     return 0;
0739 }
0740 
0741 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
0742     .suspend_noirq = omap_mpuio_suspend_noirq,
0743     .resume_noirq = omap_mpuio_resume_noirq,
0744 };
0745 
0746 /* use platform_driver for this. */
0747 static struct platform_driver omap_mpuio_driver = {
0748     .driver     = {
0749         .name   = "mpuio",
0750         .pm = &omap_mpuio_dev_pm_ops,
0751     },
0752 };
0753 
0754 static struct platform_device omap_mpuio_device = {
0755     .name       = "mpuio",
0756     .id     = -1,
0757     .dev = {
0758         .driver = &omap_mpuio_driver.driver,
0759     }
0760     /* could list the /proc/iomem resources */
0761 };
0762 
0763 static inline void omap_mpuio_init(struct gpio_bank *bank)
0764 {
0765     platform_set_drvdata(&omap_mpuio_device, bank);
0766 
0767     if (platform_driver_register(&omap_mpuio_driver) == 0)
0768         (void) platform_device_register(&omap_mpuio_device);
0769 }
0770 
0771 /*---------------------------------------------------------------------*/
0772 
0773 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
0774 {
0775     struct gpio_bank *bank = gpiochip_get_data(chip);
0776     unsigned long flags;
0777 
0778     pm_runtime_get_sync(chip->parent);
0779 
0780     raw_spin_lock_irqsave(&bank->lock, flags);
0781     omap_enable_gpio_module(bank, offset);
0782     bank->mod_usage |= BIT(offset);
0783     raw_spin_unlock_irqrestore(&bank->lock, flags);
0784 
0785     return 0;
0786 }
0787 
0788 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
0789 {
0790     struct gpio_bank *bank = gpiochip_get_data(chip);
0791     unsigned long flags;
0792 
0793     raw_spin_lock_irqsave(&bank->lock, flags);
0794     bank->mod_usage &= ~(BIT(offset));
0795     if (!LINE_USED(bank->irq_usage, offset)) {
0796         omap_set_gpio_direction(bank, offset, 1);
0797         omap_clear_gpio_debounce(bank, offset);
0798     }
0799     omap_disable_gpio_module(bank, offset);
0800     raw_spin_unlock_irqrestore(&bank->lock, flags);
0801 
0802     pm_runtime_put(chip->parent);
0803 }
0804 
0805 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
0806 {
0807     struct gpio_bank *bank = gpiochip_get_data(chip);
0808 
0809     if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
0810         return GPIO_LINE_DIRECTION_IN;
0811 
0812     return GPIO_LINE_DIRECTION_OUT;
0813 }
0814 
0815 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
0816 {
0817     struct gpio_bank *bank;
0818     unsigned long flags;
0819 
0820     bank = gpiochip_get_data(chip);
0821     raw_spin_lock_irqsave(&bank->lock, flags);
0822     omap_set_gpio_direction(bank, offset, 1);
0823     raw_spin_unlock_irqrestore(&bank->lock, flags);
0824     return 0;
0825 }
0826 
0827 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
0828 {
0829     struct gpio_bank *bank = gpiochip_get_data(chip);
0830     void __iomem *reg;
0831 
0832     if (omap_gpio_is_input(bank, offset))
0833         reg = bank->base + bank->regs->datain;
0834     else
0835         reg = bank->base + bank->regs->dataout;
0836 
0837     return (readl_relaxed(reg) & BIT(offset)) != 0;
0838 }
0839 
0840 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
0841 {
0842     struct gpio_bank *bank;
0843     unsigned long flags;
0844 
0845     bank = gpiochip_get_data(chip);
0846     raw_spin_lock_irqsave(&bank->lock, flags);
0847     bank->set_dataout(bank, offset, value);
0848     omap_set_gpio_direction(bank, offset, 0);
0849     raw_spin_unlock_irqrestore(&bank->lock, flags);
0850     return 0;
0851 }
0852 
0853 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
0854                   unsigned long *bits)
0855 {
0856     struct gpio_bank *bank = gpiochip_get_data(chip);
0857     void __iomem *base = bank->base;
0858     u32 direction, m, val = 0;
0859 
0860     direction = readl_relaxed(base + bank->regs->direction);
0861 
0862     m = direction & *mask;
0863     if (m)
0864         val |= readl_relaxed(base + bank->regs->datain) & m;
0865 
0866     m = ~direction & *mask;
0867     if (m)
0868         val |= readl_relaxed(base + bank->regs->dataout) & m;
0869 
0870     *bits = val;
0871 
0872     return 0;
0873 }
0874 
0875 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
0876                   unsigned debounce)
0877 {
0878     struct gpio_bank *bank;
0879     unsigned long flags;
0880     int ret;
0881 
0882     bank = gpiochip_get_data(chip);
0883 
0884     raw_spin_lock_irqsave(&bank->lock, flags);
0885     ret = omap2_set_gpio_debounce(bank, offset, debounce);
0886     raw_spin_unlock_irqrestore(&bank->lock, flags);
0887 
0888     if (ret)
0889         dev_info(chip->parent,
0890              "Could not set line %u debounce to %u microseconds (%d)",
0891              offset, debounce, ret);
0892 
0893     return ret;
0894 }
0895 
0896 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
0897                 unsigned long config)
0898 {
0899     u32 debounce;
0900     int ret = -ENOTSUPP;
0901 
0902     switch (pinconf_to_config_param(config)) {
0903     case PIN_CONFIG_BIAS_DISABLE:
0904     case PIN_CONFIG_BIAS_PULL_UP:
0905     case PIN_CONFIG_BIAS_PULL_DOWN:
0906         ret = gpiochip_generic_config(chip, offset, config);
0907         break;
0908     case PIN_CONFIG_INPUT_DEBOUNCE:
0909         debounce = pinconf_to_config_argument(config);
0910         ret = omap_gpio_debounce(chip, offset, debounce);
0911         break;
0912     default:
0913         break;
0914     }
0915 
0916     return ret;
0917 }
0918 
0919 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0920 {
0921     struct gpio_bank *bank;
0922     unsigned long flags;
0923 
0924     bank = gpiochip_get_data(chip);
0925     raw_spin_lock_irqsave(&bank->lock, flags);
0926     bank->set_dataout(bank, offset, value);
0927     raw_spin_unlock_irqrestore(&bank->lock, flags);
0928 }
0929 
0930 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
0931                    unsigned long *bits)
0932 {
0933     struct gpio_bank *bank = gpiochip_get_data(chip);
0934     void __iomem *reg = bank->base + bank->regs->dataout;
0935     unsigned long flags;
0936     u32 l;
0937 
0938     raw_spin_lock_irqsave(&bank->lock, flags);
0939     l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
0940     writel_relaxed(l, reg);
0941     bank->context.dataout = l;
0942     raw_spin_unlock_irqrestore(&bank->lock, flags);
0943 }
0944 
0945 /*---------------------------------------------------------------------*/
0946 
0947 static void omap_gpio_show_rev(struct gpio_bank *bank)
0948 {
0949     static bool called;
0950     u32 rev;
0951 
0952     if (called || bank->regs->revision == USHRT_MAX)
0953         return;
0954 
0955     rev = readw_relaxed(bank->base + bank->regs->revision);
0956     pr_info("OMAP GPIO hardware version %d.%d\n",
0957         (rev >> 4) & 0x0f, rev & 0x0f);
0958 
0959     called = true;
0960 }
0961 
0962 static void omap_gpio_mod_init(struct gpio_bank *bank)
0963 {
0964     void __iomem *base = bank->base;
0965     u32 l = 0xffffffff;
0966 
0967     if (bank->width == 16)
0968         l = 0xffff;
0969 
0970     if (bank->is_mpuio) {
0971         writel_relaxed(l, bank->base + bank->regs->irqenable);
0972         return;
0973     }
0974 
0975     omap_gpio_rmw(base + bank->regs->irqenable, l,
0976               bank->regs->irqenable_inv);
0977     omap_gpio_rmw(base + bank->regs->irqstatus, l,
0978               !bank->regs->irqenable_inv);
0979     if (bank->regs->debounce_en)
0980         writel_relaxed(0, base + bank->regs->debounce_en);
0981 
0982     /* Save OE default value (0xffffffff) in the context */
0983     bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
0984      /* Initialize interface clk ungated, module enabled */
0985     if (bank->regs->ctrl)
0986         writel_relaxed(0, base + bank->regs->ctrl);
0987 }
0988 
0989 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc,
0990                    struct device *pm_dev)
0991 {
0992     struct gpio_irq_chip *irq;
0993     static int gpio;
0994     const char *label;
0995     int irq_base = 0;
0996     int ret;
0997 
0998     /*
0999      * REVISIT eventually switch from OMAP-specific gpio structs
1000      * over to the generic ones
1001      */
1002     bank->chip.request = omap_gpio_request;
1003     bank->chip.free = omap_gpio_free;
1004     bank->chip.get_direction = omap_gpio_get_direction;
1005     bank->chip.direction_input = omap_gpio_input;
1006     bank->chip.get = omap_gpio_get;
1007     bank->chip.get_multiple = omap_gpio_get_multiple;
1008     bank->chip.direction_output = omap_gpio_output;
1009     bank->chip.set_config = omap_gpio_set_config;
1010     bank->chip.set = omap_gpio_set;
1011     bank->chip.set_multiple = omap_gpio_set_multiple;
1012     if (bank->is_mpuio) {
1013         bank->chip.label = "mpuio";
1014         if (bank->regs->wkup_en)
1015             bank->chip.parent = &omap_mpuio_device.dev;
1016         bank->chip.base = OMAP_MPUIO(0);
1017     } else {
1018         label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1019                        gpio, gpio + bank->width - 1);
1020         if (!label)
1021             return -ENOMEM;
1022         bank->chip.label = label;
1023         bank->chip.base = gpio;
1024     }
1025     bank->chip.ngpio = bank->width;
1026 
1027 #ifdef CONFIG_ARCH_OMAP1
1028     /*
1029      * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1030      * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1031      */
1032     irq_base = devm_irq_alloc_descs(bank->chip.parent,
1033                     -1, 0, bank->width, 0);
1034     if (irq_base < 0) {
1035         dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1036         return -ENODEV;
1037     }
1038 #endif
1039 
1040     /* MPUIO is a bit different, reading IRQ status clears it */
1041     if (bank->is_mpuio && !bank->regs->wkup_en)
1042         irqc->irq_set_wake = NULL;
1043 
1044     irq = &bank->chip.irq;
1045     irq->chip = irqc;
1046     irq->handler = handle_bad_irq;
1047     irq->default_type = IRQ_TYPE_NONE;
1048     irq->num_parents = 1;
1049     irq->parents = &bank->irq;
1050     irq->first = irq_base;
1051 
1052     ret = gpiochip_add_data(&bank->chip, bank);
1053     if (ret)
1054         return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
1055 
1056     irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev);
1057     ret = devm_request_irq(bank->chip.parent, bank->irq,
1058                    omap_gpio_irq_handler,
1059                    0, dev_name(bank->chip.parent), bank);
1060     if (ret)
1061         gpiochip_remove(&bank->chip);
1062 
1063     if (!bank->is_mpuio)
1064         gpio += bank->width;
1065 
1066     return ret;
1067 }
1068 
1069 static void omap_gpio_init_context(struct gpio_bank *p)
1070 {
1071     const struct omap_gpio_reg_offs *regs = p->regs;
1072     void __iomem *base = p->base;
1073 
1074     p->context.sysconfig    = readl_relaxed(base + regs->sysconfig);
1075     p->context.ctrl     = readl_relaxed(base + regs->ctrl);
1076     p->context.oe       = readl_relaxed(base + regs->direction);
1077     p->context.wake_en  = readl_relaxed(base + regs->wkup_en);
1078     p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1079     p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1080     p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1081     p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1082     p->context.irqenable1   = readl_relaxed(base + regs->irqenable);
1083     p->context.irqenable2   = readl_relaxed(base + regs->irqenable2);
1084     p->context.dataout  = readl_relaxed(base + regs->dataout);
1085 
1086     p->context_valid = true;
1087 }
1088 
1089 static void omap_gpio_restore_context(struct gpio_bank *bank)
1090 {
1091     const struct omap_gpio_reg_offs *regs = bank->regs;
1092     void __iomem *base = bank->base;
1093 
1094     writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1095     writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1096     writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1097     writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1098     writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1099     writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1100     writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1101     writel_relaxed(bank->context.dataout, base + regs->dataout);
1102     writel_relaxed(bank->context.oe, base + regs->direction);
1103 
1104     if (bank->dbck_enable_mask) {
1105         writel_relaxed(bank->context.debounce, base + regs->debounce);
1106         writel_relaxed(bank->context.debounce_en,
1107                    base + regs->debounce_en);
1108     }
1109 
1110     writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1111     writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1112 }
1113 
1114 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1115 {
1116     struct device *dev = bank->chip.parent;
1117     void __iomem *base = bank->base;
1118     u32 mask, nowake;
1119 
1120     bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1121 
1122     /* Save syconfig, it's runtime value can be different from init value */
1123     if (bank->loses_context)
1124         bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1125 
1126     if (!bank->enabled_non_wakeup_gpios)
1127         goto update_gpio_context_count;
1128 
1129     /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
1130     mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1131     mask &= ~bank->context.risingdetect;
1132     bank->saved_datain |= mask;
1133 
1134     /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
1135     mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1136     mask &= ~bank->context.fallingdetect;
1137     bank->saved_datain &= ~mask;
1138 
1139     if (!may_lose_context)
1140         goto update_gpio_context_count;
1141 
1142     /*
1143      * If going to OFF, remove triggering for all wkup domain
1144      * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1145      * generated.  See OMAP2420 Errata item 1.101.
1146      */
1147     if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1148         nowake = bank->enabled_non_wakeup_gpios;
1149         omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1150         omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1151     }
1152 
1153 update_gpio_context_count:
1154     if (bank->get_context_loss_count)
1155         bank->context_loss_count =
1156                 bank->get_context_loss_count(dev);
1157 
1158     omap_gpio_dbck_disable(bank);
1159 }
1160 
1161 static void omap_gpio_unidle(struct gpio_bank *bank)
1162 {
1163     struct device *dev = bank->chip.parent;
1164     u32 l = 0, gen, gen0, gen1;
1165     int c;
1166 
1167     /*
1168      * On the first resume during the probe, the context has not
1169      * been initialised and so initialise it now. Also initialise
1170      * the context loss count.
1171      */
1172     if (bank->loses_context && !bank->context_valid) {
1173         omap_gpio_init_context(bank);
1174 
1175         if (bank->get_context_loss_count)
1176             bank->context_loss_count =
1177                 bank->get_context_loss_count(dev);
1178     }
1179 
1180     omap_gpio_dbck_enable(bank);
1181 
1182     if (bank->loses_context) {
1183         if (!bank->get_context_loss_count) {
1184             omap_gpio_restore_context(bank);
1185         } else {
1186             c = bank->get_context_loss_count(dev);
1187             if (c != bank->context_loss_count) {
1188                 omap_gpio_restore_context(bank);
1189             } else {
1190                 return;
1191             }
1192         }
1193     } else {
1194         /* Restore changes done for OMAP2420 errata 1.101 */
1195         writel_relaxed(bank->context.fallingdetect,
1196                    bank->base + bank->regs->fallingdetect);
1197         writel_relaxed(bank->context.risingdetect,
1198                    bank->base + bank->regs->risingdetect);
1199     }
1200 
1201     l = readl_relaxed(bank->base + bank->regs->datain);
1202 
1203     /*
1204      * Check if any of the non-wakeup interrupt GPIOs have changed
1205      * state.  If so, generate an IRQ by software.  This is
1206      * horribly racy, but it's the best we can do to work around
1207      * this silicon bug.
1208      */
1209     l ^= bank->saved_datain;
1210     l &= bank->enabled_non_wakeup_gpios;
1211 
1212     /*
1213      * No need to generate IRQs for the rising edge for gpio IRQs
1214      * configured with falling edge only; and vice versa.
1215      */
1216     gen0 = l & bank->context.fallingdetect;
1217     gen0 &= bank->saved_datain;
1218 
1219     gen1 = l & bank->context.risingdetect;
1220     gen1 &= ~(bank->saved_datain);
1221 
1222     /* FIXME: Consider GPIO IRQs with level detections properly! */
1223     gen = l & (~(bank->context.fallingdetect) &
1224                      ~(bank->context.risingdetect));
1225     /* Consider all GPIO IRQs needed to be updated */
1226     gen |= gen0 | gen1;
1227 
1228     if (gen) {
1229         u32 old0, old1;
1230 
1231         old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1232         old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1233 
1234         if (!bank->regs->irqstatus_raw0) {
1235             writel_relaxed(old0 | gen, bank->base +
1236                         bank->regs->leveldetect0);
1237             writel_relaxed(old1 | gen, bank->base +
1238                         bank->regs->leveldetect1);
1239         }
1240 
1241         if (bank->regs->irqstatus_raw0) {
1242             writel_relaxed(old0 | l, bank->base +
1243                         bank->regs->leveldetect0);
1244             writel_relaxed(old1 | l, bank->base +
1245                         bank->regs->leveldetect1);
1246         }
1247         writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1248         writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1249     }
1250 }
1251 
1252 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1253                   unsigned long cmd, void *v)
1254 {
1255     struct gpio_bank *bank;
1256     unsigned long flags;
1257     int ret = NOTIFY_OK;
1258     u32 isr, mask;
1259 
1260     bank = container_of(nb, struct gpio_bank, nb);
1261 
1262     raw_spin_lock_irqsave(&bank->lock, flags);
1263     if (bank->is_suspended)
1264         goto out_unlock;
1265 
1266     switch (cmd) {
1267     case CPU_CLUSTER_PM_ENTER:
1268         mask = omap_get_gpio_irqbank_mask(bank);
1269         isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1270         if (isr) {
1271             ret = NOTIFY_BAD;
1272             break;
1273         }
1274         omap_gpio_idle(bank, true);
1275         break;
1276     case CPU_CLUSTER_PM_ENTER_FAILED:
1277     case CPU_CLUSTER_PM_EXIT:
1278         omap_gpio_unidle(bank);
1279         break;
1280     }
1281 
1282 out_unlock:
1283     raw_spin_unlock_irqrestore(&bank->lock, flags);
1284 
1285     return ret;
1286 }
1287 
1288 static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1289     .revision =     OMAP24XX_GPIO_REVISION,
1290     .sysconfig =        OMAP24XX_GPIO_SYSCONFIG,
1291     .direction =        OMAP24XX_GPIO_OE,
1292     .datain =       OMAP24XX_GPIO_DATAIN,
1293     .dataout =      OMAP24XX_GPIO_DATAOUT,
1294     .set_dataout =      OMAP24XX_GPIO_SETDATAOUT,
1295     .clr_dataout =      OMAP24XX_GPIO_CLEARDATAOUT,
1296     .irqstatus =        OMAP24XX_GPIO_IRQSTATUS1,
1297     .irqstatus2 =       OMAP24XX_GPIO_IRQSTATUS2,
1298     .irqenable =        OMAP24XX_GPIO_IRQENABLE1,
1299     .irqenable2 =       OMAP24XX_GPIO_IRQENABLE2,
1300     .set_irqenable =    OMAP24XX_GPIO_SETIRQENABLE1,
1301     .clr_irqenable =    OMAP24XX_GPIO_CLEARIRQENABLE1,
1302     .debounce =     OMAP24XX_GPIO_DEBOUNCE_VAL,
1303     .debounce_en =      OMAP24XX_GPIO_DEBOUNCE_EN,
1304     .ctrl =         OMAP24XX_GPIO_CTRL,
1305     .wkup_en =      OMAP24XX_GPIO_WAKE_EN,
1306     .leveldetect0 =     OMAP24XX_GPIO_LEVELDETECT0,
1307     .leveldetect1 =     OMAP24XX_GPIO_LEVELDETECT1,
1308     .risingdetect =     OMAP24XX_GPIO_RISINGDETECT,
1309     .fallingdetect =    OMAP24XX_GPIO_FALLINGDETECT,
1310 };
1311 
1312 static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1313     .revision =     OMAP4_GPIO_REVISION,
1314     .sysconfig =        OMAP4_GPIO_SYSCONFIG,
1315     .direction =        OMAP4_GPIO_OE,
1316     .datain =       OMAP4_GPIO_DATAIN,
1317     .dataout =      OMAP4_GPIO_DATAOUT,
1318     .set_dataout =      OMAP4_GPIO_SETDATAOUT,
1319     .clr_dataout =      OMAP4_GPIO_CLEARDATAOUT,
1320     .irqstatus =        OMAP4_GPIO_IRQSTATUS0,
1321     .irqstatus2 =       OMAP4_GPIO_IRQSTATUS1,
1322     .irqstatus_raw0 =   OMAP4_GPIO_IRQSTATUSRAW0,
1323     .irqstatus_raw1 =   OMAP4_GPIO_IRQSTATUSRAW1,
1324     .irqenable =        OMAP4_GPIO_IRQSTATUSSET0,
1325     .irqenable2 =       OMAP4_GPIO_IRQSTATUSSET1,
1326     .set_irqenable =    OMAP4_GPIO_IRQSTATUSSET0,
1327     .clr_irqenable =    OMAP4_GPIO_IRQSTATUSCLR0,
1328     .debounce =     OMAP4_GPIO_DEBOUNCINGTIME,
1329     .debounce_en =      OMAP4_GPIO_DEBOUNCENABLE,
1330     .ctrl =         OMAP4_GPIO_CTRL,
1331     .wkup_en =      OMAP4_GPIO_IRQWAKEN0,
1332     .leveldetect0 =     OMAP4_GPIO_LEVELDETECT0,
1333     .leveldetect1 =     OMAP4_GPIO_LEVELDETECT1,
1334     .risingdetect =     OMAP4_GPIO_RISINGDETECT,
1335     .fallingdetect =    OMAP4_GPIO_FALLINGDETECT,
1336 };
1337 
1338 static const struct omap_gpio_platform_data omap2_pdata = {
1339     .regs = &omap2_gpio_regs,
1340     .bank_width = 32,
1341     .dbck_flag = false,
1342 };
1343 
1344 static const struct omap_gpio_platform_data omap3_pdata = {
1345     .regs = &omap2_gpio_regs,
1346     .bank_width = 32,
1347     .dbck_flag = true,
1348 };
1349 
1350 static const struct omap_gpio_platform_data omap4_pdata = {
1351     .regs = &omap4_gpio_regs,
1352     .bank_width = 32,
1353     .dbck_flag = true,
1354 };
1355 
1356 static const struct of_device_id omap_gpio_match[] = {
1357     {
1358         .compatible = "ti,omap4-gpio",
1359         .data = &omap4_pdata,
1360     },
1361     {
1362         .compatible = "ti,omap3-gpio",
1363         .data = &omap3_pdata,
1364     },
1365     {
1366         .compatible = "ti,omap2-gpio",
1367         .data = &omap2_pdata,
1368     },
1369     { },
1370 };
1371 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1372 
1373 static int omap_gpio_probe(struct platform_device *pdev)
1374 {
1375     struct device *dev = &pdev->dev;
1376     struct device_node *node = dev->of_node;
1377     const struct omap_gpio_platform_data *pdata;
1378     struct gpio_bank *bank;
1379     struct irq_chip *irqc;
1380     int ret;
1381 
1382     pdata = device_get_match_data(dev);
1383 
1384     pdata = pdata ?: dev_get_platdata(dev);
1385     if (!pdata)
1386         return -EINVAL;
1387 
1388     bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1389     if (!bank)
1390         return -ENOMEM;
1391 
1392     irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1393     if (!irqc)
1394         return -ENOMEM;
1395 
1396     irqc->irq_startup = omap_gpio_irq_startup,
1397     irqc->irq_shutdown = omap_gpio_irq_shutdown,
1398     irqc->irq_ack = dummy_irq_chip.irq_ack,
1399     irqc->irq_mask = omap_gpio_mask_irq,
1400     irqc->irq_unmask = omap_gpio_unmask_irq,
1401     irqc->irq_set_type = omap_gpio_irq_type,
1402     irqc->irq_set_wake = omap_gpio_wake_enable,
1403     irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1404     irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1405     irqc->name = dev_name(&pdev->dev);
1406     irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1407 
1408     bank->irq = platform_get_irq(pdev, 0);
1409     if (bank->irq <= 0) {
1410         if (!bank->irq)
1411             bank->irq = -ENXIO;
1412         return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
1413     }
1414 
1415     bank->chip.parent = dev;
1416     bank->chip.owner = THIS_MODULE;
1417     bank->dbck_flag = pdata->dbck_flag;
1418     bank->stride = pdata->bank_stride;
1419     bank->width = pdata->bank_width;
1420     bank->is_mpuio = pdata->is_mpuio;
1421     bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1422     bank->regs = pdata->regs;
1423 
1424     if (node) {
1425         if (!of_property_read_bool(node, "ti,gpio-always-on"))
1426             bank->loses_context = true;
1427     } else {
1428         bank->loses_context = pdata->loses_context;
1429 
1430         if (bank->loses_context)
1431             bank->get_context_loss_count =
1432                 pdata->get_context_loss_count;
1433     }
1434 
1435     if (bank->regs->set_dataout && bank->regs->clr_dataout)
1436         bank->set_dataout = omap_set_gpio_dataout_reg;
1437     else
1438         bank->set_dataout = omap_set_gpio_dataout_mask;
1439 
1440     raw_spin_lock_init(&bank->lock);
1441     raw_spin_lock_init(&bank->wa_lock);
1442 
1443     /* Static mapping, never released */
1444     bank->base = devm_platform_ioremap_resource(pdev, 0);
1445     if (IS_ERR(bank->base)) {
1446         return PTR_ERR(bank->base);
1447     }
1448 
1449     if (bank->dbck_flag) {
1450         bank->dbck = devm_clk_get(dev, "dbclk");
1451         if (IS_ERR(bank->dbck)) {
1452             dev_err(dev,
1453                 "Could not get gpio dbck. Disable debounce\n");
1454             bank->dbck_flag = false;
1455         } else {
1456             clk_prepare(bank->dbck);
1457         }
1458     }
1459 
1460     platform_set_drvdata(pdev, bank);
1461 
1462     pm_runtime_enable(dev);
1463     pm_runtime_get_sync(dev);
1464 
1465     if (bank->is_mpuio)
1466         omap_mpuio_init(bank);
1467 
1468     omap_gpio_mod_init(bank);
1469 
1470     ret = omap_gpio_chip_init(bank, irqc, dev);
1471     if (ret) {
1472         pm_runtime_put_sync(dev);
1473         pm_runtime_disable(dev);
1474         if (bank->dbck_flag)
1475             clk_unprepare(bank->dbck);
1476         return ret;
1477     }
1478 
1479     omap_gpio_show_rev(bank);
1480 
1481     bank->nb.notifier_call = gpio_omap_cpu_notifier;
1482     cpu_pm_register_notifier(&bank->nb);
1483 
1484     pm_runtime_put(dev);
1485 
1486     return 0;
1487 }
1488 
1489 static int omap_gpio_remove(struct platform_device *pdev)
1490 {
1491     struct gpio_bank *bank = platform_get_drvdata(pdev);
1492 
1493     cpu_pm_unregister_notifier(&bank->nb);
1494     gpiochip_remove(&bank->chip);
1495     pm_runtime_disable(&pdev->dev);
1496     if (bank->dbck_flag)
1497         clk_unprepare(bank->dbck);
1498 
1499     return 0;
1500 }
1501 
1502 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1503 {
1504     struct gpio_bank *bank = dev_get_drvdata(dev);
1505     unsigned long flags;
1506 
1507     raw_spin_lock_irqsave(&bank->lock, flags);
1508     omap_gpio_idle(bank, true);
1509     bank->is_suspended = true;
1510     raw_spin_unlock_irqrestore(&bank->lock, flags);
1511 
1512     return 0;
1513 }
1514 
1515 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1516 {
1517     struct gpio_bank *bank = dev_get_drvdata(dev);
1518     unsigned long flags;
1519 
1520     raw_spin_lock_irqsave(&bank->lock, flags);
1521     omap_gpio_unidle(bank);
1522     bank->is_suspended = false;
1523     raw_spin_unlock_irqrestore(&bank->lock, flags);
1524 
1525     return 0;
1526 }
1527 
1528 static int __maybe_unused omap_gpio_suspend(struct device *dev)
1529 {
1530     struct gpio_bank *bank = dev_get_drvdata(dev);
1531 
1532     if (bank->is_suspended)
1533         return 0;
1534 
1535     bank->needs_resume = 1;
1536 
1537     return omap_gpio_runtime_suspend(dev);
1538 }
1539 
1540 static int __maybe_unused omap_gpio_resume(struct device *dev)
1541 {
1542     struct gpio_bank *bank = dev_get_drvdata(dev);
1543 
1544     if (!bank->needs_resume)
1545         return 0;
1546 
1547     bank->needs_resume = 0;
1548 
1549     return omap_gpio_runtime_resume(dev);
1550 }
1551 
1552 static const struct dev_pm_ops gpio_pm_ops = {
1553     SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1554                                     NULL)
1555     SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1556 };
1557 
1558 static struct platform_driver omap_gpio_driver = {
1559     .probe      = omap_gpio_probe,
1560     .remove     = omap_gpio_remove,
1561     .driver     = {
1562         .name   = "omap_gpio",
1563         .pm = &gpio_pm_ops,
1564         .of_match_table = omap_gpio_match,
1565     },
1566 };
1567 
1568 /*
1569  * gpio driver register needs to be done before
1570  * machine_init functions access gpio APIs.
1571  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1572  */
1573 static int __init omap_gpio_drv_reg(void)
1574 {
1575     return platform_driver_register(&omap_gpio_driver);
1576 }
1577 postcore_initcall(omap_gpio_drv_reg);
1578 
1579 static void __exit omap_gpio_exit(void)
1580 {
1581     platform_driver_unregister(&omap_gpio_driver);
1582 }
1583 module_exit(omap_gpio_exit);
1584 
1585 MODULE_DESCRIPTION("omap gpio driver");
1586 MODULE_ALIAS("platform:gpio-omap");
1587 MODULE_LICENSE("GPL v2");
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