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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
0004 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de
0005 //
0006 // Based on code from Freescale Semiconductor,
0007 // Authors: Daniel Mack, Juergen Beisert.
0008 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
0009 
0010 #include <linux/clk.h>
0011 #include <linux/err.h>
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/io.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/irqchip/chained_irq.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 #include <linux/syscore_ops.h>
0022 #include <linux/gpio/driver.h>
0023 #include <linux/of.h>
0024 #include <linux/of_device.h>
0025 #include <linux/bug.h>
0026 
0027 /* device type dependent stuff */
0028 struct mxc_gpio_hwdata {
0029     unsigned dr_reg;
0030     unsigned gdir_reg;
0031     unsigned psr_reg;
0032     unsigned icr1_reg;
0033     unsigned icr2_reg;
0034     unsigned imr_reg;
0035     unsigned isr_reg;
0036     int edge_sel_reg;
0037     unsigned low_level;
0038     unsigned high_level;
0039     unsigned rise_edge;
0040     unsigned fall_edge;
0041 };
0042 
0043 struct mxc_gpio_reg_saved {
0044     u32 icr1;
0045     u32 icr2;
0046     u32 imr;
0047     u32 gdir;
0048     u32 edge_sel;
0049     u32 dr;
0050 };
0051 
0052 struct mxc_gpio_port {
0053     struct list_head node;
0054     void __iomem *base;
0055     struct clk *clk;
0056     int irq;
0057     int irq_high;
0058     struct irq_domain *domain;
0059     struct gpio_chip gc;
0060     struct device *dev;
0061     u32 both_edges;
0062     struct mxc_gpio_reg_saved gpio_saved_reg;
0063     bool power_off;
0064     const struct mxc_gpio_hwdata *hwdata;
0065 };
0066 
0067 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
0068     .dr_reg     = 0x1c,
0069     .gdir_reg   = 0x00,
0070     .psr_reg    = 0x24,
0071     .icr1_reg   = 0x28,
0072     .icr2_reg   = 0x2c,
0073     .imr_reg    = 0x30,
0074     .isr_reg    = 0x34,
0075     .edge_sel_reg   = -EINVAL,
0076     .low_level  = 0x03,
0077     .high_level = 0x02,
0078     .rise_edge  = 0x00,
0079     .fall_edge  = 0x01,
0080 };
0081 
0082 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
0083     .dr_reg     = 0x00,
0084     .gdir_reg   = 0x04,
0085     .psr_reg    = 0x08,
0086     .icr1_reg   = 0x0c,
0087     .icr2_reg   = 0x10,
0088     .imr_reg    = 0x14,
0089     .isr_reg    = 0x18,
0090     .edge_sel_reg   = -EINVAL,
0091     .low_level  = 0x00,
0092     .high_level = 0x01,
0093     .rise_edge  = 0x02,
0094     .fall_edge  = 0x03,
0095 };
0096 
0097 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
0098     .dr_reg     = 0x00,
0099     .gdir_reg   = 0x04,
0100     .psr_reg    = 0x08,
0101     .icr1_reg   = 0x0c,
0102     .icr2_reg   = 0x10,
0103     .imr_reg    = 0x14,
0104     .isr_reg    = 0x18,
0105     .edge_sel_reg   = 0x1c,
0106     .low_level  = 0x00,
0107     .high_level = 0x01,
0108     .rise_edge  = 0x02,
0109     .fall_edge  = 0x03,
0110 };
0111 
0112 #define GPIO_DR         (port->hwdata->dr_reg)
0113 #define GPIO_GDIR       (port->hwdata->gdir_reg)
0114 #define GPIO_PSR        (port->hwdata->psr_reg)
0115 #define GPIO_ICR1       (port->hwdata->icr1_reg)
0116 #define GPIO_ICR2       (port->hwdata->icr2_reg)
0117 #define GPIO_IMR        (port->hwdata->imr_reg)
0118 #define GPIO_ISR        (port->hwdata->isr_reg)
0119 #define GPIO_EDGE_SEL       (port->hwdata->edge_sel_reg)
0120 
0121 #define GPIO_INT_LOW_LEV    (port->hwdata->low_level)
0122 #define GPIO_INT_HIGH_LEV   (port->hwdata->high_level)
0123 #define GPIO_INT_RISE_EDGE  (port->hwdata->rise_edge)
0124 #define GPIO_INT_FALL_EDGE  (port->hwdata->fall_edge)
0125 #define GPIO_INT_BOTH_EDGES 0x4
0126 
0127 static const struct of_device_id mxc_gpio_dt_ids[] = {
0128     { .compatible = "fsl,imx1-gpio", .data =  &imx1_imx21_gpio_hwdata },
0129     { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
0130     { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
0131     { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
0132     { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
0133     { /* sentinel */ }
0134 };
0135 MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
0136 
0137 /*
0138  * MX2 has one interrupt *for all* gpio ports. The list is used
0139  * to save the references to all ports, so that mx2_gpio_irq_handler
0140  * can walk through all interrupt status registers.
0141  */
0142 static LIST_HEAD(mxc_gpio_ports);
0143 
0144 /* Note: This driver assumes 32 GPIOs are handled in one register */
0145 
0146 static int gpio_set_irq_type(struct irq_data *d, u32 type)
0147 {
0148     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0149     struct mxc_gpio_port *port = gc->private;
0150     u32 bit, val;
0151     u32 gpio_idx = d->hwirq;
0152     int edge;
0153     void __iomem *reg = port->base;
0154 
0155     port->both_edges &= ~(1 << gpio_idx);
0156     switch (type) {
0157     case IRQ_TYPE_EDGE_RISING:
0158         edge = GPIO_INT_RISE_EDGE;
0159         break;
0160     case IRQ_TYPE_EDGE_FALLING:
0161         edge = GPIO_INT_FALL_EDGE;
0162         break;
0163     case IRQ_TYPE_EDGE_BOTH:
0164         if (GPIO_EDGE_SEL >= 0) {
0165             edge = GPIO_INT_BOTH_EDGES;
0166         } else {
0167             val = port->gc.get(&port->gc, gpio_idx);
0168             if (val) {
0169                 edge = GPIO_INT_LOW_LEV;
0170                 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
0171             } else {
0172                 edge = GPIO_INT_HIGH_LEV;
0173                 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
0174             }
0175             port->both_edges |= 1 << gpio_idx;
0176         }
0177         break;
0178     case IRQ_TYPE_LEVEL_LOW:
0179         edge = GPIO_INT_LOW_LEV;
0180         break;
0181     case IRQ_TYPE_LEVEL_HIGH:
0182         edge = GPIO_INT_HIGH_LEV;
0183         break;
0184     default:
0185         return -EINVAL;
0186     }
0187 
0188     if (GPIO_EDGE_SEL >= 0) {
0189         val = readl(port->base + GPIO_EDGE_SEL);
0190         if (edge == GPIO_INT_BOTH_EDGES)
0191             writel(val | (1 << gpio_idx),
0192                 port->base + GPIO_EDGE_SEL);
0193         else
0194             writel(val & ~(1 << gpio_idx),
0195                 port->base + GPIO_EDGE_SEL);
0196     }
0197 
0198     if (edge != GPIO_INT_BOTH_EDGES) {
0199         reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
0200         bit = gpio_idx & 0xf;
0201         val = readl(reg) & ~(0x3 << (bit << 1));
0202         writel(val | (edge << (bit << 1)), reg);
0203     }
0204 
0205     writel(1 << gpio_idx, port->base + GPIO_ISR);
0206 
0207     return 0;
0208 }
0209 
0210 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
0211 {
0212     void __iomem *reg = port->base;
0213     u32 bit, val;
0214     int edge;
0215 
0216     reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
0217     bit = gpio & 0xf;
0218     val = readl(reg);
0219     edge = (val >> (bit << 1)) & 3;
0220     val &= ~(0x3 << (bit << 1));
0221     if (edge == GPIO_INT_HIGH_LEV) {
0222         edge = GPIO_INT_LOW_LEV;
0223         pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
0224     } else if (edge == GPIO_INT_LOW_LEV) {
0225         edge = GPIO_INT_HIGH_LEV;
0226         pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
0227     } else {
0228         pr_err("mxc: invalid configuration for GPIO %d: %x\n",
0229                gpio, edge);
0230         return;
0231     }
0232     writel(val | (edge << (bit << 1)), reg);
0233 }
0234 
0235 /* handle 32 interrupts in one status register */
0236 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
0237 {
0238     while (irq_stat != 0) {
0239         int irqoffset = fls(irq_stat) - 1;
0240 
0241         if (port->both_edges & (1 << irqoffset))
0242             mxc_flip_edge(port, irqoffset);
0243 
0244         generic_handle_domain_irq(port->domain, irqoffset);
0245 
0246         irq_stat &= ~(1 << irqoffset);
0247     }
0248 }
0249 
0250 /* MX1 and MX3 has one interrupt *per* gpio port */
0251 static void mx3_gpio_irq_handler(struct irq_desc *desc)
0252 {
0253     u32 irq_stat;
0254     struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
0255     struct irq_chip *chip = irq_desc_get_chip(desc);
0256 
0257     chained_irq_enter(chip, desc);
0258 
0259     irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
0260 
0261     mxc_gpio_irq_handler(port, irq_stat);
0262 
0263     chained_irq_exit(chip, desc);
0264 }
0265 
0266 /* MX2 has one interrupt *for all* gpio ports */
0267 static void mx2_gpio_irq_handler(struct irq_desc *desc)
0268 {
0269     u32 irq_msk, irq_stat;
0270     struct mxc_gpio_port *port;
0271     struct irq_chip *chip = irq_desc_get_chip(desc);
0272 
0273     chained_irq_enter(chip, desc);
0274 
0275     /* walk through all interrupt status registers */
0276     list_for_each_entry(port, &mxc_gpio_ports, node) {
0277         irq_msk = readl(port->base + GPIO_IMR);
0278         if (!irq_msk)
0279             continue;
0280 
0281         irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
0282         if (irq_stat)
0283             mxc_gpio_irq_handler(port, irq_stat);
0284     }
0285     chained_irq_exit(chip, desc);
0286 }
0287 
0288 /*
0289  * Set interrupt number "irq" in the GPIO as a wake-up source.
0290  * While system is running, all registered GPIO interrupts need to have
0291  * wake-up enabled. When system is suspended, only selected GPIO interrupts
0292  * need to have wake-up enabled.
0293  * @param  irq          interrupt source number
0294  * @param  enable       enable as wake-up if equal to non-zero
0295  * @return       This function returns 0 on success.
0296  */
0297 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
0298 {
0299     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0300     struct mxc_gpio_port *port = gc->private;
0301     u32 gpio_idx = d->hwirq;
0302     int ret;
0303 
0304     if (enable) {
0305         if (port->irq_high && (gpio_idx >= 16))
0306             ret = enable_irq_wake(port->irq_high);
0307         else
0308             ret = enable_irq_wake(port->irq);
0309     } else {
0310         if (port->irq_high && (gpio_idx >= 16))
0311             ret = disable_irq_wake(port->irq_high);
0312         else
0313             ret = disable_irq_wake(port->irq);
0314     }
0315 
0316     return ret;
0317 }
0318 
0319 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
0320 {
0321     struct irq_chip_generic *gc;
0322     struct irq_chip_type *ct;
0323     int rv;
0324 
0325     gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
0326                      port->base, handle_level_irq);
0327     if (!gc)
0328         return -ENOMEM;
0329     gc->private = port;
0330 
0331     ct = gc->chip_types;
0332     ct->chip.irq_ack = irq_gc_ack_set_bit;
0333     ct->chip.irq_mask = irq_gc_mask_clr_bit;
0334     ct->chip.irq_unmask = irq_gc_mask_set_bit;
0335     ct->chip.irq_set_type = gpio_set_irq_type;
0336     ct->chip.irq_set_wake = gpio_set_wake_irq;
0337     ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
0338     ct->regs.ack = GPIO_ISR;
0339     ct->regs.mask = GPIO_IMR;
0340 
0341     rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
0342                      IRQ_GC_INIT_NESTED_LOCK,
0343                      IRQ_NOREQUEST, 0);
0344 
0345     return rv;
0346 }
0347 
0348 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
0349 {
0350     struct mxc_gpio_port *port = gpiochip_get_data(gc);
0351 
0352     return irq_find_mapping(port->domain, offset);
0353 }
0354 
0355 static int mxc_gpio_probe(struct platform_device *pdev)
0356 {
0357     struct device_node *np = pdev->dev.of_node;
0358     struct mxc_gpio_port *port;
0359     int irq_count;
0360     int irq_base;
0361     int err;
0362 
0363     port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
0364     if (!port)
0365         return -ENOMEM;
0366 
0367     port->dev = &pdev->dev;
0368 
0369     port->hwdata = device_get_match_data(&pdev->dev);
0370 
0371     port->base = devm_platform_ioremap_resource(pdev, 0);
0372     if (IS_ERR(port->base))
0373         return PTR_ERR(port->base);
0374 
0375     irq_count = platform_irq_count(pdev);
0376     if (irq_count < 0)
0377         return irq_count;
0378 
0379     if (irq_count > 1) {
0380         port->irq_high = platform_get_irq(pdev, 1);
0381         if (port->irq_high < 0)
0382             port->irq_high = 0;
0383     }
0384 
0385     port->irq = platform_get_irq(pdev, 0);
0386     if (port->irq < 0)
0387         return port->irq;
0388 
0389     /* the controller clock is optional */
0390     port->clk = devm_clk_get_optional(&pdev->dev, NULL);
0391     if (IS_ERR(port->clk))
0392         return PTR_ERR(port->clk);
0393 
0394     err = clk_prepare_enable(port->clk);
0395     if (err) {
0396         dev_err(&pdev->dev, "Unable to enable clock.\n");
0397         return err;
0398     }
0399 
0400     if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
0401         port->power_off = true;
0402 
0403     /* disable the interrupt and clear the status */
0404     writel(0, port->base + GPIO_IMR);
0405     writel(~0, port->base + GPIO_ISR);
0406 
0407     if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
0408         /*
0409          * Setup one handler for all GPIO interrupts. Actually setting
0410          * the handler is needed only once, but doing it for every port
0411          * is more robust and easier.
0412          */
0413         irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
0414     } else {
0415         /* setup one handler for each entry */
0416         irq_set_chained_handler_and_data(port->irq,
0417                          mx3_gpio_irq_handler, port);
0418         if (port->irq_high > 0)
0419             /* setup handler for GPIO 16 to 31 */
0420             irq_set_chained_handler_and_data(port->irq_high,
0421                              mx3_gpio_irq_handler,
0422                              port);
0423     }
0424 
0425     err = bgpio_init(&port->gc, &pdev->dev, 4,
0426              port->base + GPIO_PSR,
0427              port->base + GPIO_DR, NULL,
0428              port->base + GPIO_GDIR, NULL,
0429              BGPIOF_READ_OUTPUT_REG_SET);
0430     if (err)
0431         goto out_bgio;
0432 
0433     port->gc.request = gpiochip_generic_request;
0434     port->gc.free = gpiochip_generic_free;
0435     port->gc.to_irq = mxc_gpio_to_irq;
0436     port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
0437                          pdev->id * 32;
0438 
0439     err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
0440     if (err)
0441         goto out_bgio;
0442 
0443     irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
0444     if (irq_base < 0) {
0445         err = irq_base;
0446         goto out_bgio;
0447     }
0448 
0449     port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
0450                          &irq_domain_simple_ops, NULL);
0451     if (!port->domain) {
0452         err = -ENODEV;
0453         goto out_bgio;
0454     }
0455 
0456     /* gpio-mxc can be a generic irq chip */
0457     err = mxc_gpio_init_gc(port, irq_base);
0458     if (err < 0)
0459         goto out_irqdomain_remove;
0460 
0461     list_add_tail(&port->node, &mxc_gpio_ports);
0462 
0463     platform_set_drvdata(pdev, port);
0464 
0465     return 0;
0466 
0467 out_irqdomain_remove:
0468     irq_domain_remove(port->domain);
0469 out_bgio:
0470     clk_disable_unprepare(port->clk);
0471     dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
0472     return err;
0473 }
0474 
0475 static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
0476 {
0477     if (!port->power_off)
0478         return;
0479 
0480     port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
0481     port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
0482     port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
0483     port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
0484     port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
0485     port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
0486 }
0487 
0488 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
0489 {
0490     if (!port->power_off)
0491         return;
0492 
0493     writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
0494     writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
0495     writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
0496     writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
0497     writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
0498     writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
0499 }
0500 
0501 static int mxc_gpio_syscore_suspend(void)
0502 {
0503     struct mxc_gpio_port *port;
0504 
0505     /* walk through all ports */
0506     list_for_each_entry(port, &mxc_gpio_ports, node) {
0507         mxc_gpio_save_regs(port);
0508         clk_disable_unprepare(port->clk);
0509     }
0510 
0511     return 0;
0512 }
0513 
0514 static void mxc_gpio_syscore_resume(void)
0515 {
0516     struct mxc_gpio_port *port;
0517     int ret;
0518 
0519     /* walk through all ports */
0520     list_for_each_entry(port, &mxc_gpio_ports, node) {
0521         ret = clk_prepare_enable(port->clk);
0522         if (ret) {
0523             pr_err("mxc: failed to enable gpio clock %d\n", ret);
0524             return;
0525         }
0526         mxc_gpio_restore_regs(port);
0527     }
0528 }
0529 
0530 static struct syscore_ops mxc_gpio_syscore_ops = {
0531     .suspend = mxc_gpio_syscore_suspend,
0532     .resume = mxc_gpio_syscore_resume,
0533 };
0534 
0535 static struct platform_driver mxc_gpio_driver = {
0536     .driver     = {
0537         .name   = "gpio-mxc",
0538         .of_match_table = mxc_gpio_dt_ids,
0539         .suppress_bind_attrs = true,
0540     },
0541     .probe      = mxc_gpio_probe,
0542 };
0543 
0544 static int __init gpio_mxc_init(void)
0545 {
0546     register_syscore_ops(&mxc_gpio_syscore_ops);
0547 
0548     return platform_driver_register(&mxc_gpio_driver);
0549 }
0550 subsys_initcall(gpio_mxc_init);
0551 
0552 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
0553 MODULE_DESCRIPTION("i.MX GPIO Driver");
0554 MODULE_LICENSE("GPL");
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