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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * GPIO driver for Marvell SoCs
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0008  * Andrew Lunn <andrew@lunn.ch>
0009  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0010  *
0011  * This driver is a fairly straightforward GPIO driver for the
0012  * complete family of Marvell EBU SoC platforms (Orion, Dove,
0013  * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
0014  * driver is the different register layout that exists between the
0015  * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
0016  * platforms (MV78200 from the Discovery family and the Armada
0017  * XP). Therefore, this driver handles three variants of the GPIO
0018  * block:
0019  * - the basic variant, called "orion-gpio", with the simplest
0020  *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
0021  *   non-SMP Discovery systems
0022  * - the mv78200 variant for MV78200 Discovery systems. This variant
0023  *   turns the edge mask and level mask registers into CPU0 edge
0024  *   mask/level mask registers, and adds CPU1 edge mask/level mask
0025  *   registers.
0026  * - the armadaxp variant for Armada XP systems. This variant keeps
0027  *   the normal cause/edge mask/level mask registers when the global
0028  *   interrupts are used, but adds per-CPU cause/edge mask/level mask
0029  *   registers n a separate memory area for the per-CPU GPIO
0030  *   interrupts.
0031  */
0032 
0033 #include <linux/bitops.h>
0034 #include <linux/clk.h>
0035 #include <linux/err.h>
0036 #include <linux/gpio/driver.h>
0037 #include <linux/gpio/consumer.h>
0038 #include <linux/gpio/machine.h>
0039 #include <linux/init.h>
0040 #include <linux/io.h>
0041 #include <linux/irq.h>
0042 #include <linux/irqchip/chained_irq.h>
0043 #include <linux/irqdomain.h>
0044 #include <linux/mfd/syscon.h>
0045 #include <linux/of_device.h>
0046 #include <linux/pinctrl/consumer.h>
0047 #include <linux/platform_device.h>
0048 #include <linux/pwm.h>
0049 #include <linux/regmap.h>
0050 #include <linux/slab.h>
0051 
0052 /*
0053  * GPIO unit register offsets.
0054  */
0055 #define GPIO_OUT_OFF            0x0000
0056 #define GPIO_IO_CONF_OFF        0x0004
0057 #define GPIO_BLINK_EN_OFF       0x0008
0058 #define GPIO_IN_POL_OFF         0x000c
0059 #define GPIO_DATA_IN_OFF        0x0010
0060 #define GPIO_EDGE_CAUSE_OFF     0x0014
0061 #define GPIO_EDGE_MASK_OFF      0x0018
0062 #define GPIO_LEVEL_MASK_OFF     0x001c
0063 #define GPIO_BLINK_CNT_SELECT_OFF   0x0020
0064 
0065 /*
0066  * PWM register offsets.
0067  */
0068 #define PWM_BLINK_ON_DURATION_OFF   0x0
0069 #define PWM_BLINK_OFF_DURATION_OFF  0x4
0070 #define PWM_BLINK_COUNTER_B_OFF     0x8
0071 
0072 /* Armada 8k variant gpios register offsets */
0073 #define AP80X_GPIO0_OFF_A8K     0x1040
0074 #define CP11X_GPIO0_OFF_A8K     0x100
0075 #define CP11X_GPIO1_OFF_A8K     0x140
0076 
0077 /* The MV78200 has per-CPU registers for edge mask and level mask */
0078 #define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
0079 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
0080 
0081 /*
0082  * The Armada XP has per-CPU registers for interrupt cause, interrupt
0083  * mask and interrupt level mask. Those are in percpu_regs range.
0084  */
0085 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
0086 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
0087 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
0088 
0089 #define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
0090 #define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
0091 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
0092 #define MVEBU_GPIO_SOC_VARIANT_A8K  0x4
0093 
0094 #define MVEBU_MAX_GPIO_PER_BANK     32
0095 
0096 struct mvebu_pwm {
0097     struct regmap       *regs;
0098     u32          offset;
0099     unsigned long        clk_rate;
0100     struct gpio_desc    *gpiod;
0101     struct pwm_chip      chip;
0102     spinlock_t       lock;
0103     struct mvebu_gpio_chip  *mvchip;
0104 
0105     /* Used to preserve GPIO/PWM registers across suspend/resume */
0106     u32          blink_select;
0107     u32          blink_on_duration;
0108     u32          blink_off_duration;
0109 };
0110 
0111 struct mvebu_gpio_chip {
0112     struct gpio_chip   chip;
0113     struct regmap     *regs;
0114     u32        offset;
0115     struct regmap     *percpu_regs;
0116     int        irqbase;
0117     struct irq_domain *domain;
0118     int        soc_variant;
0119 
0120     /* Used for PWM support */
0121     struct clk    *clk;
0122     struct mvebu_pwm  *mvpwm;
0123 
0124     /* Used to preserve GPIO registers across suspend/resume */
0125     u32        out_reg;
0126     u32        io_conf_reg;
0127     u32        blink_en_reg;
0128     u32        in_pol_reg;
0129     u32        edge_mask_regs[4];
0130     u32        level_mask_regs[4];
0131 };
0132 
0133 /*
0134  * Functions returning addresses of individual registers for a given
0135  * GPIO controller.
0136  */
0137 
0138 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
0139              struct regmap **map, unsigned int *offset)
0140 {
0141     int cpu;
0142 
0143     switch (mvchip->soc_variant) {
0144     case MVEBU_GPIO_SOC_VARIANT_ORION:
0145     case MVEBU_GPIO_SOC_VARIANT_MV78200:
0146     case MVEBU_GPIO_SOC_VARIANT_A8K:
0147         *map = mvchip->regs;
0148         *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
0149         break;
0150     case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
0151         cpu = smp_processor_id();
0152         *map = mvchip->percpu_regs;
0153         *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
0154         break;
0155     default:
0156         BUG();
0157     }
0158 }
0159 
0160 static u32
0161 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)
0162 {
0163     struct regmap *map;
0164     unsigned int offset;
0165     u32 val;
0166 
0167     mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
0168     regmap_read(map, offset, &val);
0169 
0170     return val;
0171 }
0172 
0173 static void
0174 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val)
0175 {
0176     struct regmap *map;
0177     unsigned int offset;
0178 
0179     mvebu_gpioreg_edge_cause(mvchip, &map, &offset);
0180     regmap_write(map, offset, val);
0181 }
0182 
0183 static inline void
0184 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip,
0185             struct regmap **map, unsigned int *offset)
0186 {
0187     int cpu;
0188 
0189     switch (mvchip->soc_variant) {
0190     case MVEBU_GPIO_SOC_VARIANT_ORION:
0191     case MVEBU_GPIO_SOC_VARIANT_A8K:
0192         *map = mvchip->regs;
0193         *offset = GPIO_EDGE_MASK_OFF + mvchip->offset;
0194         break;
0195     case MVEBU_GPIO_SOC_VARIANT_MV78200:
0196         cpu = smp_processor_id();
0197         *map = mvchip->regs;
0198         *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu);
0199         break;
0200     case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
0201         cpu = smp_processor_id();
0202         *map = mvchip->percpu_regs;
0203         *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
0204         break;
0205     default:
0206         BUG();
0207     }
0208 }
0209 
0210 static u32
0211 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip)
0212 {
0213     struct regmap *map;
0214     unsigned int offset;
0215     u32 val;
0216 
0217     mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
0218     regmap_read(map, offset, &val);
0219 
0220     return val;
0221 }
0222 
0223 static void
0224 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val)
0225 {
0226     struct regmap *map;
0227     unsigned int offset;
0228 
0229     mvebu_gpioreg_edge_mask(mvchip, &map, &offset);
0230     regmap_write(map, offset, val);
0231 }
0232 
0233 static void
0234 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip,
0235              struct regmap **map, unsigned int *offset)
0236 {
0237     int cpu;
0238 
0239     switch (mvchip->soc_variant) {
0240     case MVEBU_GPIO_SOC_VARIANT_ORION:
0241     case MVEBU_GPIO_SOC_VARIANT_A8K:
0242         *map = mvchip->regs;
0243         *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset;
0244         break;
0245     case MVEBU_GPIO_SOC_VARIANT_MV78200:
0246         cpu = smp_processor_id();
0247         *map = mvchip->regs;
0248         *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu);
0249         break;
0250     case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
0251         cpu = smp_processor_id();
0252         *map = mvchip->percpu_regs;
0253         *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
0254         break;
0255     default:
0256         BUG();
0257     }
0258 }
0259 
0260 static u32
0261 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip)
0262 {
0263     struct regmap *map;
0264     unsigned int offset;
0265     u32 val;
0266 
0267     mvebu_gpioreg_level_mask(mvchip, &map, &offset);
0268     regmap_read(map, offset, &val);
0269 
0270     return val;
0271 }
0272 
0273 static void
0274 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val)
0275 {
0276     struct regmap *map;
0277     unsigned int offset;
0278 
0279     mvebu_gpioreg_level_mask(mvchip, &map, &offset);
0280     regmap_write(map, offset, val);
0281 }
0282 
0283 /*
0284  * Functions returning offsets of individual registers for a given
0285  * PWM controller.
0286  */
0287 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm)
0288 {
0289     return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF;
0290 }
0291 
0292 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm)
0293 {
0294     return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF;
0295 }
0296 
0297 /*
0298  * Functions implementing the gpio_chip methods
0299  */
0300 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
0301 {
0302     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0303 
0304     regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
0305                BIT(pin), value ? BIT(pin) : 0);
0306 }
0307 
0308 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin)
0309 {
0310     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0311     u32 u;
0312 
0313     regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
0314 
0315     if (u & BIT(pin)) {
0316         u32 data_in, in_pol;
0317 
0318         regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset,
0319                 &data_in);
0320         regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
0321                 &in_pol);
0322         u = data_in ^ in_pol;
0323     } else {
0324         regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u);
0325     }
0326 
0327     return (u >> pin) & 1;
0328 }
0329 
0330 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin,
0331                  int value)
0332 {
0333     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0334 
0335     regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
0336                BIT(pin), value ? BIT(pin) : 0);
0337 }
0338 
0339 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
0340 {
0341     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0342     int ret;
0343 
0344     /*
0345      * Check with the pinctrl driver whether this pin is usable as
0346      * an input GPIO
0347      */
0348     ret = pinctrl_gpio_direction_input(chip->base + pin);
0349     if (ret)
0350         return ret;
0351 
0352     regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
0353                BIT(pin), BIT(pin));
0354 
0355     return 0;
0356 }
0357 
0358 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
0359                        int value)
0360 {
0361     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0362     int ret;
0363 
0364     /*
0365      * Check with the pinctrl driver whether this pin is usable as
0366      * an output GPIO
0367      */
0368     ret = pinctrl_gpio_direction_output(chip->base + pin);
0369     if (ret)
0370         return ret;
0371 
0372     mvebu_gpio_blink(chip, pin, 0);
0373     mvebu_gpio_set(chip, pin, value);
0374 
0375     regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
0376                BIT(pin), 0);
0377 
0378     return 0;
0379 }
0380 
0381 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
0382 {
0383     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0384     u32 u;
0385 
0386     regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
0387 
0388     if (u & BIT(pin))
0389         return GPIO_LINE_DIRECTION_IN;
0390 
0391     return GPIO_LINE_DIRECTION_OUT;
0392 }
0393 
0394 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin)
0395 {
0396     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0397 
0398     return irq_create_mapping(mvchip->domain, pin);
0399 }
0400 
0401 /*
0402  * Functions implementing the irq_chip methods
0403  */
0404 static void mvebu_gpio_irq_ack(struct irq_data *d)
0405 {
0406     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0407     struct mvebu_gpio_chip *mvchip = gc->private;
0408     u32 mask = d->mask;
0409 
0410     irq_gc_lock(gc);
0411     mvebu_gpio_write_edge_cause(mvchip, ~mask);
0412     irq_gc_unlock(gc);
0413 }
0414 
0415 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
0416 {
0417     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0418     struct mvebu_gpio_chip *mvchip = gc->private;
0419     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0420     u32 mask = d->mask;
0421 
0422     irq_gc_lock(gc);
0423     ct->mask_cache_priv &= ~mask;
0424     mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
0425     irq_gc_unlock(gc);
0426 }
0427 
0428 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
0429 {
0430     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0431     struct mvebu_gpio_chip *mvchip = gc->private;
0432     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0433     u32 mask = d->mask;
0434 
0435     irq_gc_lock(gc);
0436     mvebu_gpio_write_edge_cause(mvchip, ~mask);
0437     ct->mask_cache_priv |= mask;
0438     mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
0439     irq_gc_unlock(gc);
0440 }
0441 
0442 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
0443 {
0444     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0445     struct mvebu_gpio_chip *mvchip = gc->private;
0446     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0447     u32 mask = d->mask;
0448 
0449     irq_gc_lock(gc);
0450     ct->mask_cache_priv &= ~mask;
0451     mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
0452     irq_gc_unlock(gc);
0453 }
0454 
0455 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
0456 {
0457     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0458     struct mvebu_gpio_chip *mvchip = gc->private;
0459     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0460     u32 mask = d->mask;
0461 
0462     irq_gc_lock(gc);
0463     ct->mask_cache_priv |= mask;
0464     mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv);
0465     irq_gc_unlock(gc);
0466 }
0467 
0468 /*****************************************************************************
0469  * MVEBU GPIO IRQ
0470  *
0471  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
0472  * value of the line or the opposite value.
0473  *
0474  * Level IRQ handlers: DATA_IN is used directly as cause register.
0475  *             Interrupt are masked by LEVEL_MASK registers.
0476  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
0477  *             Interrupt are masked by EDGE_MASK registers.
0478  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
0479  *             the polarity to catch the next line transaction.
0480  *             This is a race condition that might not perfectly
0481  *             work on some use cases.
0482  *
0483  * Every eight GPIO lines are grouped (OR'ed) before going up to main
0484  * cause register.
0485  *
0486  *            EDGE  cause    mask
0487  *    data-in   /--------| |-----| |----\
0488  *     -----| |-----                 ---- to main cause reg
0489  *       X      \----------------| |----/
0490  *    polarity    LEVEL      mask
0491  *
0492  ****************************************************************************/
0493 
0494 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0495 {
0496     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0497     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0498     struct mvebu_gpio_chip *mvchip = gc->private;
0499     int pin;
0500     u32 u;
0501 
0502     pin = d->hwirq;
0503 
0504     regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u);
0505     if ((u & BIT(pin)) == 0)
0506         return -EINVAL;
0507 
0508     type &= IRQ_TYPE_SENSE_MASK;
0509     if (type == IRQ_TYPE_NONE)
0510         return -EINVAL;
0511 
0512     /* Check if we need to change chip and handler */
0513     if (!(ct->type & type))
0514         if (irq_setup_alt_chip(d, type))
0515             return -EINVAL;
0516 
0517     /*
0518      * Configure interrupt polarity.
0519      */
0520     switch (type) {
0521     case IRQ_TYPE_EDGE_RISING:
0522     case IRQ_TYPE_LEVEL_HIGH:
0523         regmap_update_bits(mvchip->regs,
0524                    GPIO_IN_POL_OFF + mvchip->offset,
0525                    BIT(pin), 0);
0526         break;
0527     case IRQ_TYPE_EDGE_FALLING:
0528     case IRQ_TYPE_LEVEL_LOW:
0529         regmap_update_bits(mvchip->regs,
0530                    GPIO_IN_POL_OFF + mvchip->offset,
0531                    BIT(pin), BIT(pin));
0532         break;
0533     case IRQ_TYPE_EDGE_BOTH: {
0534         u32 data_in, in_pol, val;
0535 
0536         regmap_read(mvchip->regs,
0537                 GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
0538         regmap_read(mvchip->regs,
0539                 GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
0540 
0541         /*
0542          * set initial polarity based on current input level
0543          */
0544         if ((data_in ^ in_pol) & BIT(pin))
0545             val = BIT(pin); /* falling */
0546         else
0547             val = 0; /* raising */
0548 
0549         regmap_update_bits(mvchip->regs,
0550                    GPIO_IN_POL_OFF + mvchip->offset,
0551                    BIT(pin), val);
0552         break;
0553     }
0554     }
0555     return 0;
0556 }
0557 
0558 static void mvebu_gpio_irq_handler(struct irq_desc *desc)
0559 {
0560     struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc);
0561     struct irq_chip *chip = irq_desc_get_chip(desc);
0562     u32 cause, type, data_in, level_mask, edge_cause, edge_mask;
0563     int i;
0564 
0565     if (mvchip == NULL)
0566         return;
0567 
0568     chained_irq_enter(chip, desc);
0569 
0570     regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
0571     level_mask = mvebu_gpio_read_level_mask(mvchip);
0572     edge_cause = mvebu_gpio_read_edge_cause(mvchip);
0573     edge_mask  = mvebu_gpio_read_edge_mask(mvchip);
0574 
0575     cause = (data_in & level_mask) | (edge_cause & edge_mask);
0576 
0577     for (i = 0; i < mvchip->chip.ngpio; i++) {
0578         int irq;
0579 
0580         irq = irq_find_mapping(mvchip->domain, i);
0581 
0582         if (!(cause & BIT(i)))
0583             continue;
0584 
0585         type = irq_get_trigger_type(irq);
0586         if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
0587             /* Swap polarity (race with GPIO line) */
0588             u32 polarity;
0589 
0590             regmap_read(mvchip->regs,
0591                     GPIO_IN_POL_OFF + mvchip->offset,
0592                     &polarity);
0593             polarity ^= BIT(i);
0594             regmap_write(mvchip->regs,
0595                      GPIO_IN_POL_OFF + mvchip->offset,
0596                      polarity);
0597         }
0598 
0599         generic_handle_irq(irq);
0600     }
0601 
0602     chained_irq_exit(chip, desc);
0603 }
0604 
0605 static const struct regmap_config mvebu_gpio_regmap_config = {
0606     .reg_bits = 32,
0607     .reg_stride = 4,
0608     .val_bits = 32,
0609     .fast_io = true,
0610 };
0611 
0612 /*
0613  * Functions implementing the pwm_chip methods
0614  */
0615 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip)
0616 {
0617     return container_of(chip, struct mvebu_pwm, chip);
0618 }
0619 
0620 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
0621 {
0622     struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
0623     struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
0624     struct gpio_desc *desc;
0625     unsigned long flags;
0626     int ret = 0;
0627 
0628     spin_lock_irqsave(&mvpwm->lock, flags);
0629 
0630     if (mvpwm->gpiod) {
0631         ret = -EBUSY;
0632     } else {
0633         desc = gpiochip_request_own_desc(&mvchip->chip,
0634                          pwm->hwpwm, "mvebu-pwm",
0635                          GPIO_ACTIVE_HIGH,
0636                          GPIOD_OUT_LOW);
0637         if (IS_ERR(desc)) {
0638             ret = PTR_ERR(desc);
0639             goto out;
0640         }
0641 
0642         mvpwm->gpiod = desc;
0643     }
0644 out:
0645     spin_unlock_irqrestore(&mvpwm->lock, flags);
0646     return ret;
0647 }
0648 
0649 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
0650 {
0651     struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
0652     unsigned long flags;
0653 
0654     spin_lock_irqsave(&mvpwm->lock, flags);
0655     gpiochip_free_own_desc(mvpwm->gpiod);
0656     mvpwm->gpiod = NULL;
0657     spin_unlock_irqrestore(&mvpwm->lock, flags);
0658 }
0659 
0660 static void mvebu_pwm_get_state(struct pwm_chip *chip,
0661                 struct pwm_device *pwm,
0662                 struct pwm_state *state) {
0663 
0664     struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
0665     struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
0666     unsigned long long val;
0667     unsigned long flags;
0668     u32 u;
0669 
0670     spin_lock_irqsave(&mvpwm->lock, flags);
0671 
0672     regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u);
0673     /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */
0674     if (u > 0)
0675         val = u;
0676     else
0677         val = UINT_MAX + 1ULL;
0678     state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC,
0679             mvpwm->clk_rate);
0680 
0681     regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u);
0682     /* period = on + off duration */
0683     if (u > 0)
0684         val += u;
0685     else
0686         val += UINT_MAX + 1ULL;
0687     state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
0688 
0689     regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u);
0690     if (u)
0691         state->enabled = true;
0692     else
0693         state->enabled = false;
0694 
0695     spin_unlock_irqrestore(&mvpwm->lock, flags);
0696 }
0697 
0698 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
0699                const struct pwm_state *state)
0700 {
0701     struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip);
0702     struct mvebu_gpio_chip *mvchip = mvpwm->mvchip;
0703     unsigned long long val;
0704     unsigned long flags;
0705     unsigned int on, off;
0706 
0707     if (state->polarity != PWM_POLARITY_NORMAL)
0708         return -EINVAL;
0709 
0710     val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
0711     do_div(val, NSEC_PER_SEC);
0712     if (val > UINT_MAX + 1ULL)
0713         return -EINVAL;
0714     /*
0715      * Zero on/off values don't work as expected. Experimentation shows
0716      * that zero value is treated as 2^32. This behavior is not documented.
0717      */
0718     if (val == UINT_MAX + 1ULL)
0719         on = 0;
0720     else if (val)
0721         on = val;
0722     else
0723         on = 1;
0724 
0725     val = (unsigned long long) mvpwm->clk_rate * state->period;
0726     do_div(val, NSEC_PER_SEC);
0727     val -= on;
0728     if (val > UINT_MAX + 1ULL)
0729         return -EINVAL;
0730     if (val == UINT_MAX + 1ULL)
0731         off = 0;
0732     else if (val)
0733         off = val;
0734     else
0735         off = 1;
0736 
0737     spin_lock_irqsave(&mvpwm->lock, flags);
0738 
0739     regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on);
0740     regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off);
0741     if (state->enabled)
0742         mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1);
0743     else
0744         mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0);
0745 
0746     spin_unlock_irqrestore(&mvpwm->lock, flags);
0747 
0748     return 0;
0749 }
0750 
0751 static const struct pwm_ops mvebu_pwm_ops = {
0752     .request = mvebu_pwm_request,
0753     .free = mvebu_pwm_free,
0754     .get_state = mvebu_pwm_get_state,
0755     .apply = mvebu_pwm_apply,
0756     .owner = THIS_MODULE,
0757 };
0758 
0759 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip)
0760 {
0761     struct mvebu_pwm *mvpwm = mvchip->mvpwm;
0762 
0763     regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
0764             &mvpwm->blink_select);
0765     regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
0766             &mvpwm->blink_on_duration);
0767     regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
0768             &mvpwm->blink_off_duration);
0769 }
0770 
0771 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip)
0772 {
0773     struct mvebu_pwm *mvpwm = mvchip->mvpwm;
0774 
0775     regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset,
0776              mvpwm->blink_select);
0777     regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm),
0778              mvpwm->blink_on_duration);
0779     regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm),
0780              mvpwm->blink_off_duration);
0781 }
0782 
0783 static int mvebu_pwm_probe(struct platform_device *pdev,
0784                struct mvebu_gpio_chip *mvchip,
0785                int id)
0786 {
0787     struct device *dev = &pdev->dev;
0788     struct mvebu_pwm *mvpwm;
0789     void __iomem *base;
0790     u32 offset;
0791     u32 set;
0792 
0793     if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
0794         int ret = of_property_read_u32(dev->of_node,
0795                            "marvell,pwm-offset", &offset);
0796         if (ret < 0)
0797             return 0;
0798     } else {
0799         /*
0800          * There are only two sets of PWM configuration registers for
0801          * all the GPIO lines on those SoCs which this driver reserves
0802          * for the first two GPIO chips. So if the resource is missing
0803          * we can't treat it as an error.
0804          */
0805         if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
0806             return 0;
0807         offset = 0;
0808     }
0809 
0810     if (IS_ERR(mvchip->clk))
0811         return PTR_ERR(mvchip->clk);
0812 
0813     mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL);
0814     if (!mvpwm)
0815         return -ENOMEM;
0816     mvchip->mvpwm = mvpwm;
0817     mvpwm->mvchip = mvchip;
0818     mvpwm->offset = offset;
0819 
0820     if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
0821         mvpwm->regs = mvchip->regs;
0822 
0823         switch (mvchip->offset) {
0824         case AP80X_GPIO0_OFF_A8K:
0825         case CP11X_GPIO0_OFF_A8K:
0826             /* Blink counter A */
0827             set = 0;
0828             break;
0829         case CP11X_GPIO1_OFF_A8K:
0830             /* Blink counter B */
0831             set = U32_MAX;
0832             mvpwm->offset += PWM_BLINK_COUNTER_B_OFF;
0833             break;
0834         default:
0835             return -EINVAL;
0836         }
0837     } else {
0838         base = devm_platform_ioremap_resource_byname(pdev, "pwm");
0839         if (IS_ERR(base))
0840             return PTR_ERR(base);
0841 
0842         mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base,
0843                             &mvebu_gpio_regmap_config);
0844         if (IS_ERR(mvpwm->regs))
0845             return PTR_ERR(mvpwm->regs);
0846 
0847         /*
0848          * Use set A for lines of GPIO chip with id 0, B for GPIO chip
0849          * with id 1. Don't allow further GPIO chips to be used for PWM.
0850          */
0851         if (id == 0)
0852             set = 0;
0853         else if (id == 1)
0854             set = U32_MAX;
0855         else
0856             return -EINVAL;
0857     }
0858 
0859     regmap_write(mvchip->regs,
0860              GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set);
0861 
0862     mvpwm->clk_rate = clk_get_rate(mvchip->clk);
0863     if (!mvpwm->clk_rate) {
0864         dev_err(dev, "failed to get clock rate\n");
0865         return -EINVAL;
0866     }
0867 
0868     mvpwm->chip.dev = dev;
0869     mvpwm->chip.ops = &mvebu_pwm_ops;
0870     mvpwm->chip.npwm = mvchip->chip.ngpio;
0871 
0872     spin_lock_init(&mvpwm->lock);
0873 
0874     return pwmchip_add(&mvpwm->chip);
0875 }
0876 
0877 #ifdef CONFIG_DEBUG_FS
0878 #include <linux/seq_file.h>
0879 
0880 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0881 {
0882     struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip);
0883     u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
0884     const char *label;
0885     int i;
0886 
0887     regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out);
0888     regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf);
0889     regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink);
0890     regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol);
0891     regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in);
0892     cause   = mvebu_gpio_read_edge_cause(mvchip);
0893     edg_msk = mvebu_gpio_read_edge_mask(mvchip);
0894     lvl_msk = mvebu_gpio_read_level_mask(mvchip);
0895 
0896     for_each_requested_gpio(chip, i, label) {
0897         u32 msk;
0898         bool is_out;
0899 
0900         msk = BIT(i);
0901         is_out = !(io_conf & msk);
0902 
0903         seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
0904 
0905         if (is_out) {
0906             seq_printf(s, " out %s %s\n",
0907                    out & msk ? "hi" : "lo",
0908                    blink & msk ? "(blink )" : "");
0909             continue;
0910         }
0911 
0912         seq_printf(s, " in  %s (act %s) - IRQ",
0913                (data_in ^ in_pol) & msk  ? "hi" : "lo",
0914                in_pol & msk ? "lo" : "hi");
0915         if (!((edg_msk | lvl_msk) & msk)) {
0916             seq_puts(s, " disabled\n");
0917             continue;
0918         }
0919         if (edg_msk & msk)
0920             seq_puts(s, " edge ");
0921         if (lvl_msk & msk)
0922             seq_puts(s, " level");
0923         seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
0924     }
0925 }
0926 #else
0927 #define mvebu_gpio_dbg_show NULL
0928 #endif
0929 
0930 static const struct of_device_id mvebu_gpio_of_match[] = {
0931     {
0932         .compatible = "marvell,orion-gpio",
0933         .data       = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
0934     },
0935     {
0936         .compatible = "marvell,mv78200-gpio",
0937         .data       = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
0938     },
0939     {
0940         .compatible = "marvell,armadaxp-gpio",
0941         .data       = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
0942     },
0943     {
0944         .compatible = "marvell,armada-370-gpio",
0945         .data       = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
0946     },
0947     {
0948         .compatible = "marvell,armada-8k-gpio",
0949         .data       = (void *) MVEBU_GPIO_SOC_VARIANT_A8K,
0950     },
0951     {
0952         /* sentinel */
0953     },
0954 };
0955 
0956 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
0957 {
0958     struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
0959     int i;
0960 
0961     regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
0962             &mvchip->out_reg);
0963     regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
0964             &mvchip->io_conf_reg);
0965     regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
0966             &mvchip->blink_en_reg);
0967     regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
0968             &mvchip->in_pol_reg);
0969 
0970     switch (mvchip->soc_variant) {
0971     case MVEBU_GPIO_SOC_VARIANT_ORION:
0972     case MVEBU_GPIO_SOC_VARIANT_A8K:
0973         regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
0974                 &mvchip->edge_mask_regs[0]);
0975         regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
0976                 &mvchip->level_mask_regs[0]);
0977         break;
0978     case MVEBU_GPIO_SOC_VARIANT_MV78200:
0979         for (i = 0; i < 2; i++) {
0980             regmap_read(mvchip->regs,
0981                     GPIO_EDGE_MASK_MV78200_OFF(i),
0982                     &mvchip->edge_mask_regs[i]);
0983             regmap_read(mvchip->regs,
0984                     GPIO_LEVEL_MASK_MV78200_OFF(i),
0985                     &mvchip->level_mask_regs[i]);
0986         }
0987         break;
0988     case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
0989         for (i = 0; i < 4; i++) {
0990             regmap_read(mvchip->regs,
0991                     GPIO_EDGE_MASK_ARMADAXP_OFF(i),
0992                     &mvchip->edge_mask_regs[i]);
0993             regmap_read(mvchip->regs,
0994                     GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
0995                     &mvchip->level_mask_regs[i]);
0996         }
0997         break;
0998     default:
0999         BUG();
1000     }
1001 
1002     if (IS_ENABLED(CONFIG_PWM))
1003         mvebu_pwm_suspend(mvchip);
1004 
1005     return 0;
1006 }
1007 
1008 static int mvebu_gpio_resume(struct platform_device *pdev)
1009 {
1010     struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
1011     int i;
1012 
1013     regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset,
1014              mvchip->out_reg);
1015     regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset,
1016              mvchip->io_conf_reg);
1017     regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset,
1018              mvchip->blink_en_reg);
1019     regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset,
1020              mvchip->in_pol_reg);
1021 
1022     switch (mvchip->soc_variant) {
1023     case MVEBU_GPIO_SOC_VARIANT_ORION:
1024     case MVEBU_GPIO_SOC_VARIANT_A8K:
1025         regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset,
1026                  mvchip->edge_mask_regs[0]);
1027         regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset,
1028                  mvchip->level_mask_regs[0]);
1029         break;
1030     case MVEBU_GPIO_SOC_VARIANT_MV78200:
1031         for (i = 0; i < 2; i++) {
1032             regmap_write(mvchip->regs,
1033                      GPIO_EDGE_MASK_MV78200_OFF(i),
1034                      mvchip->edge_mask_regs[i]);
1035             regmap_write(mvchip->regs,
1036                      GPIO_LEVEL_MASK_MV78200_OFF(i),
1037                      mvchip->level_mask_regs[i]);
1038         }
1039         break;
1040     case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1041         for (i = 0; i < 4; i++) {
1042             regmap_write(mvchip->regs,
1043                      GPIO_EDGE_MASK_ARMADAXP_OFF(i),
1044                      mvchip->edge_mask_regs[i]);
1045             regmap_write(mvchip->regs,
1046                      GPIO_LEVEL_MASK_ARMADAXP_OFF(i),
1047                      mvchip->level_mask_regs[i]);
1048         }
1049         break;
1050     default:
1051         BUG();
1052     }
1053 
1054     if (IS_ENABLED(CONFIG_PWM))
1055         mvebu_pwm_resume(mvchip);
1056 
1057     return 0;
1058 }
1059 
1060 static int mvebu_gpio_probe_raw(struct platform_device *pdev,
1061                 struct mvebu_gpio_chip *mvchip)
1062 {
1063     void __iomem *base;
1064 
1065     base = devm_platform_ioremap_resource(pdev, 0);
1066     if (IS_ERR(base))
1067         return PTR_ERR(base);
1068 
1069     mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base,
1070                          &mvebu_gpio_regmap_config);
1071     if (IS_ERR(mvchip->regs))
1072         return PTR_ERR(mvchip->regs);
1073 
1074     /*
1075      * For the legacy SoCs, the regmap directly maps to the GPIO
1076      * registers, so no offset is needed.
1077      */
1078     mvchip->offset = 0;
1079 
1080     /*
1081      * The Armada XP has a second range of registers for the
1082      * per-CPU registers
1083      */
1084     if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
1085         base = devm_platform_ioremap_resource(pdev, 1);
1086         if (IS_ERR(base))
1087             return PTR_ERR(base);
1088 
1089         mvchip->percpu_regs =
1090             devm_regmap_init_mmio(&pdev->dev, base,
1091                           &mvebu_gpio_regmap_config);
1092         if (IS_ERR(mvchip->percpu_regs))
1093             return PTR_ERR(mvchip->percpu_regs);
1094     }
1095 
1096     return 0;
1097 }
1098 
1099 static int mvebu_gpio_probe_syscon(struct platform_device *pdev,
1100                    struct mvebu_gpio_chip *mvchip)
1101 {
1102     mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node);
1103     if (IS_ERR(mvchip->regs))
1104         return PTR_ERR(mvchip->regs);
1105 
1106     if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset))
1107         return -EINVAL;
1108 
1109     return 0;
1110 }
1111 
1112 static int mvebu_gpio_probe(struct platform_device *pdev)
1113 {
1114     struct mvebu_gpio_chip *mvchip;
1115     const struct of_device_id *match;
1116     struct device_node *np = pdev->dev.of_node;
1117     struct irq_chip_generic *gc;
1118     struct irq_chip_type *ct;
1119     unsigned int ngpios;
1120     bool have_irqs;
1121     int soc_variant;
1122     int i, cpu, id;
1123     int err;
1124 
1125     match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
1126     if (match)
1127         soc_variant = (unsigned long) match->data;
1128     else
1129         soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
1130 
1131     /* Some gpio controllers do not provide irq support */
1132     err = platform_irq_count(pdev);
1133     if (err < 0)
1134         return err;
1135 
1136     have_irqs = err != 0;
1137 
1138     mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
1139                   GFP_KERNEL);
1140     if (!mvchip)
1141         return -ENOMEM;
1142 
1143     platform_set_drvdata(pdev, mvchip);
1144 
1145     if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
1146         dev_err(&pdev->dev, "Missing ngpios OF property\n");
1147         return -ENODEV;
1148     }
1149 
1150     id = of_alias_get_id(pdev->dev.of_node, "gpio");
1151     if (id < 0) {
1152         dev_err(&pdev->dev, "Couldn't get OF id\n");
1153         return id;
1154     }
1155 
1156     mvchip->clk = devm_clk_get(&pdev->dev, NULL);
1157     /* Not all SoCs require a clock.*/
1158     if (!IS_ERR(mvchip->clk))
1159         clk_prepare_enable(mvchip->clk);
1160 
1161     mvchip->soc_variant = soc_variant;
1162     mvchip->chip.label = dev_name(&pdev->dev);
1163     mvchip->chip.parent = &pdev->dev;
1164     mvchip->chip.request = gpiochip_generic_request;
1165     mvchip->chip.free = gpiochip_generic_free;
1166     mvchip->chip.get_direction = mvebu_gpio_get_direction;
1167     mvchip->chip.direction_input = mvebu_gpio_direction_input;
1168     mvchip->chip.get = mvebu_gpio_get;
1169     mvchip->chip.direction_output = mvebu_gpio_direction_output;
1170     mvchip->chip.set = mvebu_gpio_set;
1171     if (have_irqs)
1172         mvchip->chip.to_irq = mvebu_gpio_to_irq;
1173     mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
1174     mvchip->chip.ngpio = ngpios;
1175     mvchip->chip.can_sleep = false;
1176     mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
1177 
1178     if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K)
1179         err = mvebu_gpio_probe_syscon(pdev, mvchip);
1180     else
1181         err = mvebu_gpio_probe_raw(pdev, mvchip);
1182 
1183     if (err)
1184         return err;
1185 
1186     /*
1187      * Mask and clear GPIO interrupts.
1188      */
1189     switch (soc_variant) {
1190     case MVEBU_GPIO_SOC_VARIANT_ORION:
1191     case MVEBU_GPIO_SOC_VARIANT_A8K:
1192         regmap_write(mvchip->regs,
1193                  GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0);
1194         regmap_write(mvchip->regs,
1195                  GPIO_EDGE_MASK_OFF + mvchip->offset, 0);
1196         regmap_write(mvchip->regs,
1197                  GPIO_LEVEL_MASK_OFF + mvchip->offset, 0);
1198         break;
1199     case MVEBU_GPIO_SOC_VARIANT_MV78200:
1200         regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1201         for (cpu = 0; cpu < 2; cpu++) {
1202             regmap_write(mvchip->regs,
1203                      GPIO_EDGE_MASK_MV78200_OFF(cpu), 0);
1204             regmap_write(mvchip->regs,
1205                      GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0);
1206         }
1207         break;
1208     case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
1209         regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0);
1210         regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0);
1211         regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0);
1212         for (cpu = 0; cpu < 4; cpu++) {
1213             regmap_write(mvchip->percpu_regs,
1214                      GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0);
1215             regmap_write(mvchip->percpu_regs,
1216                      GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0);
1217             regmap_write(mvchip->percpu_regs,
1218                      GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0);
1219         }
1220         break;
1221     default:
1222         BUG();
1223     }
1224 
1225     devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip);
1226 
1227     /* Some MVEBU SoCs have simple PWM support for GPIO lines */
1228     if (IS_ENABLED(CONFIG_PWM)) {
1229         err = mvebu_pwm_probe(pdev, mvchip, id);
1230         if (err)
1231             return err;
1232     }
1233 
1234     /* Some gpio controllers do not provide irq support */
1235     if (!have_irqs)
1236         return 0;
1237 
1238     mvchip->domain =
1239         irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL);
1240     if (!mvchip->domain) {
1241         dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
1242             mvchip->chip.label);
1243         err = -ENODEV;
1244         goto err_pwm;
1245     }
1246 
1247     err = irq_alloc_domain_generic_chips(
1248         mvchip->domain, ngpios, 2, np->name, handle_level_irq,
1249         IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0);
1250     if (err) {
1251         dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n",
1252             mvchip->chip.label);
1253         goto err_domain;
1254     }
1255 
1256     /*
1257      * NOTE: The common accessors cannot be used because of the percpu
1258      * access to the mask registers
1259      */
1260     gc = irq_get_domain_generic_chip(mvchip->domain, 0);
1261     gc->private = mvchip;
1262     ct = &gc->chip_types[0];
1263     ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
1264     ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
1265     ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
1266     ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1267     ct->chip.name = mvchip->chip.label;
1268 
1269     ct = &gc->chip_types[1];
1270     ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
1271     ct->chip.irq_ack = mvebu_gpio_irq_ack;
1272     ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
1273     ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
1274     ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
1275     ct->handler = handle_edge_irq;
1276     ct->chip.name = mvchip->chip.label;
1277 
1278     /*
1279      * Setup the interrupt handlers. Each chip can have up to 4
1280      * interrupt handlers, with each handler dealing with 8 GPIO
1281      * pins.
1282      */
1283     for (i = 0; i < 4; i++) {
1284         int irq = platform_get_irq_optional(pdev, i);
1285 
1286         if (irq < 0)
1287             continue;
1288         irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler,
1289                          mvchip);
1290     }
1291 
1292     return 0;
1293 
1294 err_domain:
1295     irq_domain_remove(mvchip->domain);
1296 err_pwm:
1297     pwmchip_remove(&mvchip->mvpwm->chip);
1298 
1299     return err;
1300 }
1301 
1302 static struct platform_driver mvebu_gpio_driver = {
1303     .driver     = {
1304         .name       = "mvebu-gpio",
1305         .of_match_table = mvebu_gpio_of_match,
1306     },
1307     .probe      = mvebu_gpio_probe,
1308     .suspend        = mvebu_gpio_suspend,
1309     .resume         = mvebu_gpio_resume,
1310 };
1311 builtin_platform_driver(mvebu_gpio_driver);
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