drivers/gpio/gpio-mt7621.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
0004  * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
0005  */
0006
0007 #include <linux/err.h>
0008 #include <linux/gpio/driver.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spinlock.h>
0015
0016 #define MTK_BANK_CNT    3
0017 #define MTK_BANK_WIDTH  32
0018
0019 #define GPIO_BANK_STRIDE    0x04
0020 #define GPIO_REG_CTRL       0x00
0021 #define GPIO_REG_POL        0x10
0022 #define GPIO_REG_DATA       0x20
0023 #define GPIO_REG_DSET       0x30
0024 #define GPIO_REG_DCLR       0x40
0025 #define GPIO_REG_REDGE      0x50
0026 #define GPIO_REG_FEDGE      0x60
0027 #define GPIO_REG_HLVL       0x70
0028 #define GPIO_REG_LLVL       0x80
0029 #define GPIO_REG_STAT       0x90
0030 #define GPIO_REG_EDGE       0xA0
0031
0032 struct mtk_gc {
0033     struct irq_chip irq_chip;
0034     struct gpio_chip chip;
0035     spinlock_t lock;
0036     int bank;
0037     u32 rising;
0038     u32 falling;
0039     u32 hlevel;
0040     u32 llevel;
0041 };
0042
0043 /**
0044  * struct mtk - state container for
0045  * data of the platform driver. It is 3
0046  * separate gpio-chip each one with its
0047  * own irq_chip.
0048  * @dev: device instance
0049  * @base: memory base address
0050  * @gpio_irq: irq number from the device tree
0051  * @gc_map: array of the gpio chips
0052  */
0053 struct mtk {
0054     struct device *dev;
0055     void __iomem *base;
0056     int gpio_irq;
0057     struct mtk_gc gc_map[MTK_BANK_CNT];
0058 };
0059
0060 static inline struct mtk_gc *
0061 to_mediatek_gpio(struct gpio_chip *chip)
0062 {
0063     return container_of(chip, struct mtk_gc, chip);
0064 }
0065
0066 static inline void
0067 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
0068 {
0069     struct gpio_chip *gc = &rg->chip;
0070     struct mtk *mtk = gpiochip_get_data(gc);
0071
0072     offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
0073     gc->write_reg(mtk->base + offset, val);
0074 }
0075
0076 static inline u32
0077 mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
0078 {
0079     struct gpio_chip *gc = &rg->chip;
0080     struct mtk *mtk = gpiochip_get_data(gc);
0081
0082     offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
0083     return gc->read_reg(mtk->base + offset);
0084 }
0085
0086 static irqreturn_t
0087 mediatek_gpio_irq_handler(int irq, void *data)
0088 {
0089     struct gpio_chip *gc = data;
0090     struct mtk_gc *rg = to_mediatek_gpio(gc);
0091     irqreturn_t ret = IRQ_NONE;
0092     unsigned long pending;
0093     int bit;
0094
0095     pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
0096
0097     for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
0098         generic_handle_domain_irq(gc->irq.domain, bit);
0099         mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
0100         ret |= IRQ_HANDLED;
0101     }
0102
0103     return ret;
0104 }
0105
0106 static void
0107 mediatek_gpio_irq_unmask(struct irq_data *d)
0108 {
0109     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0110     struct mtk_gc *rg = to_mediatek_gpio(gc);
0111     int pin = d->hwirq;
0112     unsigned long flags;
0113     u32 rise, fall, high, low;
0114
0115     gpiochip_enable_irq(gc, d->hwirq);
0116
0117     spin_lock_irqsave(&rg->lock, flags);
0118     rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
0119     fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
0120     high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
0121     low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
0122     mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
0123     mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
0124     mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
0125     mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
0126     spin_unlock_irqrestore(&rg->lock, flags);
0127 }
0128
0129 static void
0130 mediatek_gpio_irq_mask(struct irq_data *d)
0131 {
0132     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0133     struct mtk_gc *rg = to_mediatek_gpio(gc);
0134     int pin = d->hwirq;
0135     unsigned long flags;
0136     u32 rise, fall, high, low;
0137
0138     spin_lock_irqsave(&rg->lock, flags);
0139     rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
0140     fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
0141     high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
0142     low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
0143     mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
0144     mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
0145     mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
0146     mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
0147     spin_unlock_irqrestore(&rg->lock, flags);
0148
0149     gpiochip_disable_irq(gc, d->hwirq);
0150 }
0151
0152 static int
0153 mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
0154 {
0155     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0156     struct mtk_gc *rg = to_mediatek_gpio(gc);
0157     int pin = d->hwirq;
0158     u32 mask = BIT(pin);
0159
0160     if (type == IRQ_TYPE_PROBE) {
0161         if ((rg->rising | rg->falling |
0162              rg->hlevel | rg->llevel) & mask)
0163             return 0;
0164
0165         type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
0166     }
0167
0168     rg->rising &= ~mask;
0169     rg->falling &= ~mask;
0170     rg->hlevel &= ~mask;
0171     rg->llevel &= ~mask;
0172
0173     switch (type & IRQ_TYPE_SENSE_MASK) {
0174     case IRQ_TYPE_EDGE_BOTH:
0175         rg->rising |= mask;
0176         rg->falling |= mask;
0177         break;
0178     case IRQ_TYPE_EDGE_RISING:
0179         rg->rising |= mask;
0180         break;
0181     case IRQ_TYPE_EDGE_FALLING:
0182         rg->falling |= mask;
0183         break;
0184     case IRQ_TYPE_LEVEL_HIGH:
0185         rg->hlevel |= mask;
0186         break;
0187     case IRQ_TYPE_LEVEL_LOW:
0188         rg->llevel |= mask;
0189         break;
0190     }
0191
0192     return 0;
0193 }
0194
0195 static int
0196 mediatek_gpio_xlate(struct gpio_chip *chip,
0197             const struct of_phandle_args *spec, u32 *flags)
0198 {
0199     int gpio = spec->args[0];
0200     struct mtk_gc *rg = to_mediatek_gpio(chip);
0201
0202     if (rg->bank != gpio / MTK_BANK_WIDTH)
0203         return -EINVAL;
0204
0205     if (flags)
0206         *flags = spec->args[1];
0207
0208     return gpio % MTK_BANK_WIDTH;
0209 }
0210
0211 static const struct irq_chip mt7621_irq_chip = {
0212     .name       = "mt7621-gpio",
0213     .irq_mask_ack   = mediatek_gpio_irq_mask,
0214     .irq_mask   = mediatek_gpio_irq_mask,
0215     .irq_unmask = mediatek_gpio_irq_unmask,
0216     .irq_set_type   = mediatek_gpio_irq_type,
0217     .flags      = IRQCHIP_IMMUTABLE,
0218     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0219 };
0220
0221 static int
0222 mediatek_gpio_bank_probe(struct device *dev, int bank)
0223 {
0224     struct mtk *mtk = dev_get_drvdata(dev);
0225     struct mtk_gc *rg;
0226     void __iomem *dat, *set, *ctrl, *diro;
0227     int ret;
0228
0229     rg = &mtk->gc_map[bank];
0230     memset(rg, 0, sizeof(*rg));
0231
0232     spin_lock_init(&rg->lock);
0233     rg->bank = bank;
0234
0235     dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
0236     set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
0237     ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
0238     diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
0239
0240     ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
0241              BGPIOF_NO_SET_ON_INPUT);
0242     if (ret) {
0243         dev_err(dev, "bgpio_init() failed\n");
0244         return ret;
0245     }
0246
0247     rg->chip.of_gpio_n_cells = 2;
0248     rg->chip.of_xlate = mediatek_gpio_xlate;
0249     rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
0250                     dev_name(dev), bank);
0251     if (!rg->chip.label)
0252         return -ENOMEM;
0253
0254     rg->chip.offset = bank * MTK_BANK_WIDTH;
0255
0256     if (mtk->gpio_irq) {
0257         struct gpio_irq_chip *girq;
0258
0259         /*
0260          * Directly request the irq here instead of passing
0261          * a flow-handler because the irq is shared.
0262          */
0263         ret = devm_request_irq(dev, mtk->gpio_irq,
0264                        mediatek_gpio_irq_handler, IRQF_SHARED,
0265                        rg->chip.label, &rg->chip);
0266
0267         if (ret) {
0268             dev_err(dev, "Error requesting IRQ %d: %d\n",
0269                 mtk->gpio_irq, ret);
0270             return ret;
0271         }
0272
0273         girq = &rg->chip.irq;
0274         gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
0275         /* This will let us handle the parent IRQ in the driver */
0276         girq->parent_handler = NULL;
0277         girq->num_parents = 0;
0278         girq->parents = NULL;
0279         girq->default_type = IRQ_TYPE_NONE;
0280         girq->handler = handle_simple_irq;
0281     }
0282
0283     ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
0284     if (ret < 0) {
0285         dev_err(dev, "Could not register gpio %d, ret=%d\n",
0286             rg->chip.ngpio, ret);
0287         return ret;
0288     }
0289
0290     /* set polarity to low for all gpios */
0291     mtk_gpio_w32(rg, GPIO_REG_POL, 0);
0292
0293     dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
0294
0295     return 0;
0296 }
0297
0298 static int
0299 mediatek_gpio_probe(struct platform_device *pdev)
0300 {
0301     struct device *dev = &pdev->dev;
0302     struct device_node *np = dev->of_node;
0303     struct mtk *mtk;
0304     int i;
0305     int ret;
0306
0307     mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
0308     if (!mtk)
0309         return -ENOMEM;
0310
0311     mtk->base = devm_platform_ioremap_resource(pdev, 0);
0312     if (IS_ERR(mtk->base))
0313         return PTR_ERR(mtk->base);
0314
0315     mtk->gpio_irq = irq_of_parse_and_map(np, 0);
0316     mtk->dev = dev;
0317     platform_set_drvdata(pdev, mtk);
0318
0319     for (i = 0; i < MTK_BANK_CNT; i++) {
0320         ret = mediatek_gpio_bank_probe(dev, i);
0321         if (ret)
0322             return ret;
0323     }
0324
0325     return 0;
0326 }
0327
0328 static const struct of_device_id mediatek_gpio_match[] = {
0329     { .compatible = "mediatek,mt7621-gpio" },
0330     {},
0331 };
0332 MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
0333
0334 static struct platform_driver mediatek_gpio_driver = {
0335     .probe = mediatek_gpio_probe,
0336     .driver = {
0337         .name = "mt7621_gpio",
0338         .of_match_table = mediatek_gpio_match,
0339     },
0340 };
0341
0342 builtin_platform_driver(mediatek_gpio_driver);