drivers/gpio/gpio-msc313.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (C) 2020 Daniel Palmer<daniel@thingy.jp> */
0003
0004 #include <linux/bitops.h>
0005 #include <linux/kernel.h>
0006 #include <linux/types.h>
0007 #include <linux/io.h>
0008 #include <linux/of.h>
0009 #include <linux/of_device.h>
0010 #include <linux/of_irq.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014
0015 #include <dt-bindings/gpio/msc313-gpio.h>
0016 #include <dt-bindings/interrupt-controller/arm-gic.h>
0017
0018 #define DRIVER_NAME "gpio-msc313"
0019
0020 #define MSC313_GPIO_IN  BIT(0)
0021 #define MSC313_GPIO_OUT BIT(4)
0022 #define MSC313_GPIO_OEN BIT(5)
0023
0024 /*
0025  * These bits need to be saved to correctly restore the
0026  * gpio state when resuming from suspend to memory.
0027  */
0028 #define MSC313_GPIO_BITSTOSAVE (MSC313_GPIO_OUT | MSC313_GPIO_OEN)
0029
0030 /* pad names for fuart, same for all SoCs so far */
0031 #define MSC313_PINNAME_FUART_RX     "fuart_rx"
0032 #define MSC313_PINNAME_FUART_TX     "fuart_tx"
0033 #define MSC313_PINNAME_FUART_CTS    "fuart_cts"
0034 #define MSC313_PINNAME_FUART_RTS    "fuart_rts"
0035
0036 /* pad names for sr, mercury5 is different */
0037 #define MSC313_PINNAME_SR_IO2       "sr_io2"
0038 #define MSC313_PINNAME_SR_IO3       "sr_io3"
0039 #define MSC313_PINNAME_SR_IO4       "sr_io4"
0040 #define MSC313_PINNAME_SR_IO5       "sr_io5"
0041 #define MSC313_PINNAME_SR_IO6       "sr_io6"
0042 #define MSC313_PINNAME_SR_IO7       "sr_io7"
0043 #define MSC313_PINNAME_SR_IO8       "sr_io8"
0044 #define MSC313_PINNAME_SR_IO9       "sr_io9"
0045 #define MSC313_PINNAME_SR_IO10      "sr_io10"
0046 #define MSC313_PINNAME_SR_IO11      "sr_io11"
0047 #define MSC313_PINNAME_SR_IO12      "sr_io12"
0048 #define MSC313_PINNAME_SR_IO13      "sr_io13"
0049 #define MSC313_PINNAME_SR_IO14      "sr_io14"
0050 #define MSC313_PINNAME_SR_IO15      "sr_io15"
0051 #define MSC313_PINNAME_SR_IO16      "sr_io16"
0052 #define MSC313_PINNAME_SR_IO17      "sr_io17"
0053
0054 /* pad names for sd, same for all SoCs so far */
0055 #define MSC313_PINNAME_SD_CLK       "sd_clk"
0056 #define MSC313_PINNAME_SD_CMD       "sd_cmd"
0057 #define MSC313_PINNAME_SD_D0        "sd_d0"
0058 #define MSC313_PINNAME_SD_D1        "sd_d1"
0059 #define MSC313_PINNAME_SD_D2        "sd_d2"
0060 #define MSC313_PINNAME_SD_D3        "sd_d3"
0061
0062 /* pad names for i2c1, same for all SoCs so for */
0063 #define MSC313_PINNAME_I2C1_SCL     "i2c1_scl"
0064 #define MSC313_PINNAME_I2C1_SCA     "i2c1_sda"
0065
0066 /* pad names for spi0, same for all SoCs so far */
0067 #define MSC313_PINNAME_SPI0_CZ      "spi0_cz"
0068 #define MSC313_PINNAME_SPI0_CK      "spi0_ck"
0069 #define MSC313_PINNAME_SPI0_DI      "spi0_di"
0070 #define MSC313_PINNAME_SPI0_DO      "spi0_do"
0071
0072 #define FUART_NAMES         \
0073     MSC313_PINNAME_FUART_RX,    \
0074     MSC313_PINNAME_FUART_TX,    \
0075     MSC313_PINNAME_FUART_CTS,   \
0076     MSC313_PINNAME_FUART_RTS
0077
0078 #define OFF_FUART_RX    0x50
0079 #define OFF_FUART_TX    0x54
0080 #define OFF_FUART_CTS   0x58
0081 #define OFF_FUART_RTS   0x5c
0082
0083 #define FUART_OFFSETS   \
0084     OFF_FUART_RX,   \
0085     OFF_FUART_TX,   \
0086     OFF_FUART_CTS,  \
0087     OFF_FUART_RTS
0088
0089 #define SR_NAMES        \
0090     MSC313_PINNAME_SR_IO2,  \
0091     MSC313_PINNAME_SR_IO3,  \
0092     MSC313_PINNAME_SR_IO4,  \
0093     MSC313_PINNAME_SR_IO5,  \
0094     MSC313_PINNAME_SR_IO6,  \
0095     MSC313_PINNAME_SR_IO7,  \
0096     MSC313_PINNAME_SR_IO8,  \
0097     MSC313_PINNAME_SR_IO9,  \
0098     MSC313_PINNAME_SR_IO10, \
0099     MSC313_PINNAME_SR_IO11, \
0100     MSC313_PINNAME_SR_IO12, \
0101     MSC313_PINNAME_SR_IO13, \
0102     MSC313_PINNAME_SR_IO14, \
0103     MSC313_PINNAME_SR_IO15, \
0104     MSC313_PINNAME_SR_IO16, \
0105     MSC313_PINNAME_SR_IO17
0106
0107 #define OFF_SR_IO2  0x88
0108 #define OFF_SR_IO3  0x8c
0109 #define OFF_SR_IO4  0x90
0110 #define OFF_SR_IO5  0x94
0111 #define OFF_SR_IO6  0x98
0112 #define OFF_SR_IO7  0x9c
0113 #define OFF_SR_IO8  0xa0
0114 #define OFF_SR_IO9  0xa4
0115 #define OFF_SR_IO10 0xa8
0116 #define OFF_SR_IO11 0xac
0117 #define OFF_SR_IO12 0xb0
0118 #define OFF_SR_IO13 0xb4
0119 #define OFF_SR_IO14 0xb8
0120 #define OFF_SR_IO15 0xbc
0121 #define OFF_SR_IO16 0xc0
0122 #define OFF_SR_IO17 0xc4
0123
0124 #define SR_OFFSETS  \
0125     OFF_SR_IO2, \
0126     OFF_SR_IO3, \
0127     OFF_SR_IO4, \
0128     OFF_SR_IO5, \
0129     OFF_SR_IO6, \
0130     OFF_SR_IO7, \
0131     OFF_SR_IO8, \
0132     OFF_SR_IO9, \
0133     OFF_SR_IO10,    \
0134     OFF_SR_IO11,    \
0135     OFF_SR_IO12,    \
0136     OFF_SR_IO13,    \
0137     OFF_SR_IO14,    \
0138     OFF_SR_IO15,    \
0139     OFF_SR_IO16,    \
0140     OFF_SR_IO17
0141
0142 #define SD_NAMES        \
0143     MSC313_PINNAME_SD_CLK,  \
0144     MSC313_PINNAME_SD_CMD,  \
0145     MSC313_PINNAME_SD_D0,   \
0146     MSC313_PINNAME_SD_D1,   \
0147     MSC313_PINNAME_SD_D2,   \
0148     MSC313_PINNAME_SD_D3
0149
0150 #define OFF_SD_CLK  0x140
0151 #define OFF_SD_CMD  0x144
0152 #define OFF_SD_D0   0x148
0153 #define OFF_SD_D1   0x14c
0154 #define OFF_SD_D2   0x150
0155 #define OFF_SD_D3   0x154
0156
0157 #define SD_OFFSETS  \
0158     OFF_SD_CLK, \
0159     OFF_SD_CMD, \
0160     OFF_SD_D0,  \
0161     OFF_SD_D1,  \
0162     OFF_SD_D2,  \
0163     OFF_SD_D3
0164
0165 #define I2C1_NAMES          \
0166     MSC313_PINNAME_I2C1_SCL,    \
0167     MSC313_PINNAME_I2C1_SCA
0168
0169 #define OFF_I2C1_SCL    0x188
0170 #define OFF_I2C1_SCA    0x18c
0171
0172 #define I2C1_OFFSETS    \
0173     OFF_I2C1_SCL,   \
0174     OFF_I2C1_SCA
0175
0176 #define SPI0_NAMES      \
0177     MSC313_PINNAME_SPI0_CZ, \
0178     MSC313_PINNAME_SPI0_CK, \
0179     MSC313_PINNAME_SPI0_DI, \
0180     MSC313_PINNAME_SPI0_DO
0181
0182 #define OFF_SPI0_CZ 0x1c0
0183 #define OFF_SPI0_CK 0x1c4
0184 #define OFF_SPI0_DI 0x1c8
0185 #define OFF_SPI0_DO 0x1cc
0186
0187 #define SPI0_OFFSETS    \
0188     OFF_SPI0_CZ,    \
0189     OFF_SPI0_CK,    \
0190     OFF_SPI0_DI,    \
0191     OFF_SPI0_DO
0192
0193 struct msc313_gpio_data {
0194     const char * const *names;
0195     const unsigned int *offsets;
0196     const unsigned int num;
0197 };
0198
0199 #define MSC313_GPIO_CHIPDATA(_chip) \
0200 static const struct msc313_gpio_data _chip##_data = { \
0201     .names = _chip##_names, \
0202     .offsets = _chip##_offsets, \
0203     .num = ARRAY_SIZE(_chip##_offsets), \
0204 }
0205
0206 #ifdef CONFIG_MACH_INFINITY
0207 static const char * const msc313_names[] = {
0208     FUART_NAMES,
0209     SR_NAMES,
0210     SD_NAMES,
0211     I2C1_NAMES,
0212     SPI0_NAMES,
0213 };
0214
0215 static const unsigned int msc313_offsets[] = {
0216     FUART_OFFSETS,
0217     SR_OFFSETS,
0218     SD_OFFSETS,
0219     I2C1_OFFSETS,
0220     SPI0_OFFSETS,
0221 };
0222
0223 MSC313_GPIO_CHIPDATA(msc313);
0224
0225 /*
0226  * Unlike the msc313(e) the ssd20xd have a bunch of pins
0227  * that are actually called gpio probably because they
0228  * have no dedicated function.
0229  */
0230 #define SSD20XD_PINNAME_GPIO0       "gpio0"
0231 #define SSD20XD_PINNAME_GPIO1       "gpio1"
0232 #define SSD20XD_PINNAME_GPIO2       "gpio2"
0233 #define SSD20XD_PINNAME_GPIO3       "gpio3"
0234 #define SSD20XD_PINNAME_GPIO4       "gpio4"
0235 #define SSD20XD_PINNAME_GPIO5       "gpio5"
0236 #define SSD20XD_PINNAME_GPIO6       "gpio6"
0237 #define SSD20XD_PINNAME_GPIO7       "gpio7"
0238 #define SSD20XD_PINNAME_GPIO10      "gpio10"
0239 #define SSD20XD_PINNAME_GPIO11      "gpio11"
0240 #define SSD20XD_PINNAME_GPIO12      "gpio12"
0241 #define SSD20XD_PINNAME_GPIO13      "gpio13"
0242 #define SSD20XD_PINNAME_GPIO14      "gpio14"
0243 #define SSD20XD_PINNAME_GPIO85      "gpio85"
0244 #define SSD20XD_PINNAME_GPIO86      "gpio86"
0245 #define SSD20XD_PINNAME_GPIO90      "gpio90"
0246
0247 #define SSD20XD_GPIO_NAMES SSD20XD_PINNAME_GPIO0,  \
0248                SSD20XD_PINNAME_GPIO1,  \
0249                SSD20XD_PINNAME_GPIO2,  \
0250                SSD20XD_PINNAME_GPIO3,  \
0251                SSD20XD_PINNAME_GPIO4,  \
0252                SSD20XD_PINNAME_GPIO5,  \
0253                SSD20XD_PINNAME_GPIO6,  \
0254                SSD20XD_PINNAME_GPIO7,  \
0255                SSD20XD_PINNAME_GPIO10, \
0256                SSD20XD_PINNAME_GPIO11, \
0257                SSD20XD_PINNAME_GPIO12, \
0258                SSD20XD_PINNAME_GPIO13, \
0259                SSD20XD_PINNAME_GPIO14, \
0260                SSD20XD_PINNAME_GPIO85, \
0261                SSD20XD_PINNAME_GPIO86, \
0262                SSD20XD_PINNAME_GPIO90
0263
0264 #define SSD20XD_GPIO_OFF_GPIO0 0x0
0265 #define SSD20XD_GPIO_OFF_GPIO1 0x4
0266 #define SSD20XD_GPIO_OFF_GPIO2 0x8
0267 #define SSD20XD_GPIO_OFF_GPIO3 0xc
0268 #define SSD20XD_GPIO_OFF_GPIO4 0x10
0269 #define SSD20XD_GPIO_OFF_GPIO5 0x14
0270 #define SSD20XD_GPIO_OFF_GPIO6 0x18
0271 #define SSD20XD_GPIO_OFF_GPIO7 0x1c
0272 #define SSD20XD_GPIO_OFF_GPIO10 0x28
0273 #define SSD20XD_GPIO_OFF_GPIO11 0x2c
0274 #define SSD20XD_GPIO_OFF_GPIO12 0x30
0275 #define SSD20XD_GPIO_OFF_GPIO13 0x34
0276 #define SSD20XD_GPIO_OFF_GPIO14 0x38
0277 #define SSD20XD_GPIO_OFF_GPIO85 0x100
0278 #define SSD20XD_GPIO_OFF_GPIO86 0x104
0279 #define SSD20XD_GPIO_OFF_GPIO90 0x114
0280
0281 #define SSD20XD_GPIO_OFFSETS SSD20XD_GPIO_OFF_GPIO0,  \
0282                  SSD20XD_GPIO_OFF_GPIO1,  \
0283                  SSD20XD_GPIO_OFF_GPIO2,  \
0284                  SSD20XD_GPIO_OFF_GPIO3,  \
0285                  SSD20XD_GPIO_OFF_GPIO4,  \
0286                  SSD20XD_GPIO_OFF_GPIO5,  \
0287                  SSD20XD_GPIO_OFF_GPIO6,  \
0288                  SSD20XD_GPIO_OFF_GPIO7,  \
0289                  SSD20XD_GPIO_OFF_GPIO10, \
0290                  SSD20XD_GPIO_OFF_GPIO11, \
0291                  SSD20XD_GPIO_OFF_GPIO12, \
0292                  SSD20XD_GPIO_OFF_GPIO13, \
0293                  SSD20XD_GPIO_OFF_GPIO14, \
0294                  SSD20XD_GPIO_OFF_GPIO85, \
0295                  SSD20XD_GPIO_OFF_GPIO86, \
0296                  SSD20XD_GPIO_OFF_GPIO90
0297
0298 /* "ttl" pins lcd interface pins */
0299 #define SSD20XD_PINNAME_TTL0    "ttl0"
0300 #define SSD20XD_PINNAME_TTL1    "ttl1"
0301 #define SSD20XD_PINNAME_TTL2    "ttl2"
0302 #define SSD20XD_PINNAME_TTL3    "ttl3"
0303 #define SSD20XD_PINNAME_TTL4    "ttl4"
0304 #define SSD20XD_PINNAME_TTL5    "ttl5"
0305 #define SSD20XD_PINNAME_TTL6    "ttl6"
0306 #define SSD20XD_PINNAME_TTL7    "ttl7"
0307 #define SSD20XD_PINNAME_TTL8    "ttl8"
0308 #define SSD20XD_PINNAME_TTL9    "ttl9"
0309 #define SSD20XD_PINNAME_TTL10   "ttl10"
0310 #define SSD20XD_PINNAME_TTL11   "ttl11"
0311 #define SSD20XD_PINNAME_TTL12   "ttl12"
0312 #define SSD20XD_PINNAME_TTL13   "ttl13"
0313 #define SSD20XD_PINNAME_TTL14   "ttl14"
0314 #define SSD20XD_PINNAME_TTL15   "ttl15"
0315 #define SSD20XD_PINNAME_TTL16   "ttl16"
0316 #define SSD20XD_PINNAME_TTL17   "ttl17"
0317 #define SSD20XD_PINNAME_TTL18   "ttl18"
0318 #define SSD20XD_PINNAME_TTL19   "ttl19"
0319 #define SSD20XD_PINNAME_TTL20   "ttl20"
0320 #define SSD20XD_PINNAME_TTL21   "ttl21"
0321 #define SSD20XD_PINNAME_TTL22   "ttl22"
0322 #define SSD20XD_PINNAME_TTL23   "ttl23"
0323 #define SSD20XD_PINNAME_TTL24   "ttl24"
0324 #define SSD20XD_PINNAME_TTL25   "ttl25"
0325 #define SSD20XD_PINNAME_TTL26   "ttl26"
0326 #define SSD20XD_PINNAME_TTL27   "ttl27"
0327
0328 #define SSD20XD_TTL_PINNAMES SSD20XD_PINNAME_TTL0,  \
0329                  SSD20XD_PINNAME_TTL1,  \
0330                  SSD20XD_PINNAME_TTL2,  \
0331                  SSD20XD_PINNAME_TTL3,  \
0332                  SSD20XD_PINNAME_TTL4,  \
0333                  SSD20XD_PINNAME_TTL5,  \
0334                  SSD20XD_PINNAME_TTL6,  \
0335                  SSD20XD_PINNAME_TTL7,  \
0336                  SSD20XD_PINNAME_TTL8,  \
0337                  SSD20XD_PINNAME_TTL9,  \
0338                  SSD20XD_PINNAME_TTL10, \
0339                  SSD20XD_PINNAME_TTL11, \
0340                  SSD20XD_PINNAME_TTL12, \
0341                  SSD20XD_PINNAME_TTL13, \
0342                  SSD20XD_PINNAME_TTL14, \
0343                  SSD20XD_PINNAME_TTL15, \
0344                  SSD20XD_PINNAME_TTL16, \
0345                  SSD20XD_PINNAME_TTL17, \
0346                  SSD20XD_PINNAME_TTL18, \
0347                  SSD20XD_PINNAME_TTL19, \
0348                  SSD20XD_PINNAME_TTL20, \
0349                  SSD20XD_PINNAME_TTL21, \
0350                  SSD20XD_PINNAME_TTL22, \
0351                  SSD20XD_PINNAME_TTL23, \
0352                  SSD20XD_PINNAME_TTL24, \
0353                  SSD20XD_PINNAME_TTL25, \
0354                  SSD20XD_PINNAME_TTL26, \
0355                  SSD20XD_PINNAME_TTL27
0356
0357 #define SSD20XD_TTL_OFFSET_TTL0     0x80
0358 #define SSD20XD_TTL_OFFSET_TTL1     0x84
0359 #define SSD20XD_TTL_OFFSET_TTL2     0x88
0360 #define SSD20XD_TTL_OFFSET_TTL3     0x8c
0361 #define SSD20XD_TTL_OFFSET_TTL4     0x90
0362 #define SSD20XD_TTL_OFFSET_TTL5     0x94
0363 #define SSD20XD_TTL_OFFSET_TTL6     0x98
0364 #define SSD20XD_TTL_OFFSET_TTL7     0x9c
0365 #define SSD20XD_TTL_OFFSET_TTL8     0xa0
0366 #define SSD20XD_TTL_OFFSET_TTL9     0xa4
0367 #define SSD20XD_TTL_OFFSET_TTL10    0xa8
0368 #define SSD20XD_TTL_OFFSET_TTL11    0xac
0369 #define SSD20XD_TTL_OFFSET_TTL12    0xb0
0370 #define SSD20XD_TTL_OFFSET_TTL13    0xb4
0371 #define SSD20XD_TTL_OFFSET_TTL14    0xb8
0372 #define SSD20XD_TTL_OFFSET_TTL15    0xbc
0373 #define SSD20XD_TTL_OFFSET_TTL16    0xc0
0374 #define SSD20XD_TTL_OFFSET_TTL17    0xc4
0375 #define SSD20XD_TTL_OFFSET_TTL18    0xc8
0376 #define SSD20XD_TTL_OFFSET_TTL19    0xcc
0377 #define SSD20XD_TTL_OFFSET_TTL20    0xd0
0378 #define SSD20XD_TTL_OFFSET_TTL21    0xd4
0379 #define SSD20XD_TTL_OFFSET_TTL22    0xd8
0380 #define SSD20XD_TTL_OFFSET_TTL23    0xdc
0381 #define SSD20XD_TTL_OFFSET_TTL24    0xe0
0382 #define SSD20XD_TTL_OFFSET_TTL25    0xe4
0383 #define SSD20XD_TTL_OFFSET_TTL26    0xe8
0384 #define SSD20XD_TTL_OFFSET_TTL27    0xec
0385
0386 #define SSD20XD_TTL_OFFSETS SSD20XD_TTL_OFFSET_TTL0,  \
0387                 SSD20XD_TTL_OFFSET_TTL1,  \
0388                 SSD20XD_TTL_OFFSET_TTL2,  \
0389                 SSD20XD_TTL_OFFSET_TTL3,  \
0390                 SSD20XD_TTL_OFFSET_TTL4,  \
0391                 SSD20XD_TTL_OFFSET_TTL5,  \
0392                 SSD20XD_TTL_OFFSET_TTL6,  \
0393                 SSD20XD_TTL_OFFSET_TTL7,  \
0394                 SSD20XD_TTL_OFFSET_TTL8,  \
0395                 SSD20XD_TTL_OFFSET_TTL9,  \
0396                 SSD20XD_TTL_OFFSET_TTL10, \
0397                 SSD20XD_TTL_OFFSET_TTL11, \
0398                 SSD20XD_TTL_OFFSET_TTL12, \
0399                 SSD20XD_TTL_OFFSET_TTL13, \
0400                 SSD20XD_TTL_OFFSET_TTL14, \
0401                 SSD20XD_TTL_OFFSET_TTL15, \
0402                 SSD20XD_TTL_OFFSET_TTL16, \
0403                 SSD20XD_TTL_OFFSET_TTL17, \
0404                 SSD20XD_TTL_OFFSET_TTL18, \
0405                 SSD20XD_TTL_OFFSET_TTL19, \
0406                 SSD20XD_TTL_OFFSET_TTL20, \
0407                 SSD20XD_TTL_OFFSET_TTL21, \
0408                 SSD20XD_TTL_OFFSET_TTL22, \
0409                 SSD20XD_TTL_OFFSET_TTL23, \
0410                 SSD20XD_TTL_OFFSET_TTL24, \
0411                 SSD20XD_TTL_OFFSET_TTL25, \
0412                 SSD20XD_TTL_OFFSET_TTL26, \
0413                 SSD20XD_TTL_OFFSET_TTL27
0414
0415 /* On the ssd20xd the two normal uarts have dedicated pins */
0416 #define SSD20XD_PINNAME_UART0_RX    "uart0_rx"
0417 #define SSD20XD_PINNAME_UART0_TX    "uart0_tx"
0418
0419 #define SSD20XD_UART0_NAMES   \
0420     SSD20XD_PINNAME_UART0_RX, \
0421     SSD20XD_PINNAME_UART0_TX
0422
0423 #define SSD20XD_PINNAME_UART1_RX    "uart1_rx"
0424 #define SSD20XD_PINNAME_UART1_TX    "uart1_tx"
0425
0426 #define SSD20XD_UART1_NAMES   \
0427     SSD20XD_PINNAME_UART1_RX, \
0428     SSD20XD_PINNAME_UART1_TX
0429
0430 #define SSD20XD_OFF_UART0_RX    0x60
0431 #define SSD20XD_OFF_UART0_TX    0x64
0432
0433 #define SSD20XD_UART0_OFFSETS \
0434     SSD20XD_OFF_UART0_RX, \
0435     SSD20XD_OFF_UART0_TX
0436
0437 #define SSD20XD_OFF_UART1_RX    0x68
0438 #define SSD20XD_OFF_UART1_TX    0x6c
0439
0440 #define SSD20XD_UART1_OFFSETS \
0441     SSD20XD_OFF_UART1_RX, \
0442     SSD20XD_OFF_UART1_TX
0443
0444 /*
0445  * ssd20x has the same pin names but different ordering
0446  * of the registers that control the gpio.
0447  */
0448 #define SSD20XD_OFF_SD_D0   0x140
0449 #define SSD20XD_OFF_SD_D1   0x144
0450 #define SSD20XD_OFF_SD_D2   0x148
0451 #define SSD20XD_OFF_SD_D3   0x14c
0452 #define SSD20XD_OFF_SD_CMD  0x150
0453 #define SSD20XD_OFF_SD_CLK  0x154
0454
0455 #define SSD20XD_SD_OFFSETS  SSD20XD_OFF_SD_CLK, \
0456                 SSD20XD_OFF_SD_CMD, \
0457                 SSD20XD_OFF_SD_D0,  \
0458                 SSD20XD_OFF_SD_D1,  \
0459                 SSD20XD_OFF_SD_D2,  \
0460                 SSD20XD_OFF_SD_D3
0461
0462 static const char * const ssd20xd_names[] = {
0463     FUART_NAMES,
0464     SD_NAMES,
0465     SSD20XD_UART0_NAMES,
0466     SSD20XD_UART1_NAMES,
0467     SSD20XD_TTL_PINNAMES,
0468     SSD20XD_GPIO_NAMES,
0469 };
0470
0471 static const unsigned int ssd20xd_offsets[] = {
0472     FUART_OFFSETS,
0473     SSD20XD_SD_OFFSETS,
0474     SSD20XD_UART0_OFFSETS,
0475     SSD20XD_UART1_OFFSETS,
0476     SSD20XD_TTL_OFFSETS,
0477     SSD20XD_GPIO_OFFSETS,
0478 };
0479
0480 MSC313_GPIO_CHIPDATA(ssd20xd);
0481 #endif
0482
0483 struct msc313_gpio {
0484     void __iomem *base;
0485     const struct msc313_gpio_data *gpio_data;
0486     u8 *saved;
0487 };
0488
0489 static void msc313_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
0490 {
0491     struct msc313_gpio *gpio = gpiochip_get_data(chip);
0492     u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
0493
0494     if (value)
0495         gpioreg |= MSC313_GPIO_OUT;
0496     else
0497         gpioreg &= ~MSC313_GPIO_OUT;
0498
0499     writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
0500 }
0501
0502 static int msc313_gpio_get(struct gpio_chip *chip, unsigned int offset)
0503 {
0504     struct msc313_gpio *gpio = gpiochip_get_data(chip);
0505
0506     return readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]) & MSC313_GPIO_IN;
0507 }
0508
0509 static int msc313_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0510 {
0511     struct msc313_gpio *gpio = gpiochip_get_data(chip);
0512     u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
0513
0514     gpioreg |= MSC313_GPIO_OEN;
0515     writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
0516
0517     return 0;
0518 }
0519
0520 static int msc313_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
0521 {
0522     struct msc313_gpio *gpio = gpiochip_get_data(chip);
0523     u8 gpioreg = readb_relaxed(gpio->base + gpio->gpio_data->offsets[offset]);
0524
0525     gpioreg &= ~MSC313_GPIO_OEN;
0526     if (value)
0527         gpioreg |= MSC313_GPIO_OUT;
0528     else
0529         gpioreg &= ~MSC313_GPIO_OUT;
0530     writeb_relaxed(gpioreg, gpio->base + gpio->gpio_data->offsets[offset]);
0531
0532     return 0;
0533 }
0534
0535 /*
0536  * The interrupt handling happens in the parent interrupt controller,
0537  * we don't do anything here.
0538  */
0539 static struct irq_chip msc313_gpio_irqchip = {
0540     .name = "GPIO",
0541     .irq_eoi = irq_chip_eoi_parent,
0542     .irq_mask = irq_chip_mask_parent,
0543     .irq_unmask = irq_chip_unmask_parent,
0544     .irq_set_type = irq_chip_set_type_parent,
0545     .irq_set_affinity = irq_chip_set_affinity_parent,
0546 };
0547
0548 /*
0549  * The parent interrupt controller needs the GIC interrupt type set to GIC_SPI
0550  * so we need to provide the fwspec. Essentially gpiochip_populate_parent_fwspec_twocell
0551  * that puts GIC_SPI into the first cell.
0552  */
0553 static int msc313_gpio_populate_parent_fwspec(struct gpio_chip *gc,
0554                           union gpio_irq_fwspec *gfwspec,
0555                           unsigned int parent_hwirq,
0556                           unsigned int parent_type)
0557 {
0558     struct irq_fwspec *fwspec = &gfwspec->fwspec;
0559
0560     fwspec->fwnode = gc->irq.parent_domain->fwnode;
0561     fwspec->param_count = 3;
0562     fwspec->param[0] = GIC_SPI;
0563     fwspec->param[1] = parent_hwirq;
0564     fwspec->param[2] = parent_type;
0565
0566     return 0;
0567 }
0568
0569 static int msc313e_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
0570                          unsigned int child,
0571                          unsigned int child_type,
0572                          unsigned int *parent,
0573                          unsigned int *parent_type)
0574 {
0575     struct msc313_gpio *priv = gpiochip_get_data(chip);
0576     unsigned int offset = priv->gpio_data->offsets[child];
0577
0578     /*
0579      * only the spi0 pins have interrupts on the parent
0580      * on all of the known chips and so far they are all
0581      * mapped to the same place
0582      */
0583     if (offset >= OFF_SPI0_CZ && offset <= OFF_SPI0_DO) {
0584         *parent_type = child_type;
0585         *parent = ((offset - OFF_SPI0_CZ) >> 2) + 28;
0586         return 0;
0587     }
0588
0589     return -EINVAL;
0590 }
0591
0592 static int msc313_gpio_probe(struct platform_device *pdev)
0593 {
0594     const struct msc313_gpio_data *match_data;
0595     struct msc313_gpio *gpio;
0596     struct gpio_chip *gpiochip;
0597     struct gpio_irq_chip *gpioirqchip;
0598     struct irq_domain *parent_domain;
0599     struct device_node *parent_node;
0600     struct device *dev = &pdev->dev;
0601
0602     match_data = of_device_get_match_data(dev);
0603     if (!match_data)
0604         return -EINVAL;
0605
0606     parent_node = of_irq_find_parent(dev->of_node);
0607     if (!parent_node)
0608         return -ENODEV;
0609
0610     parent_domain = irq_find_host(parent_node);
0611     if (!parent_domain)
0612         return -ENODEV;
0613
0614     gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);
0615     if (!gpio)
0616         return -ENOMEM;
0617
0618     gpio->gpio_data = match_data;
0619
0620     gpio->saved = devm_kcalloc(dev, gpio->gpio_data->num, sizeof(*gpio->saved), GFP_KERNEL);
0621     if (!gpio->saved)
0622         return -ENOMEM;
0623
0624     gpio->base = devm_platform_ioremap_resource(pdev, 0);
0625     if (IS_ERR(gpio->base))
0626         return PTR_ERR(gpio->base);
0627
0628     platform_set_drvdata(pdev, gpio);
0629
0630     gpiochip = devm_kzalloc(dev, sizeof(*gpiochip), GFP_KERNEL);
0631     if (!gpiochip)
0632         return -ENOMEM;
0633
0634     gpiochip->label = DRIVER_NAME;
0635     gpiochip->parent = dev;
0636     gpiochip->request = gpiochip_generic_request;
0637     gpiochip->free = gpiochip_generic_free;
0638     gpiochip->direction_input = msc313_gpio_direction_input;
0639     gpiochip->direction_output = msc313_gpio_direction_output;
0640     gpiochip->get = msc313_gpio_get;
0641     gpiochip->set = msc313_gpio_set;
0642     gpiochip->base = -1;
0643     gpiochip->ngpio = gpio->gpio_data->num;
0644     gpiochip->names = gpio->gpio_data->names;
0645
0646     gpioirqchip = &gpiochip->irq;
0647     gpioirqchip->chip = &msc313_gpio_irqchip;
0648     gpioirqchip->fwnode = of_node_to_fwnode(dev->of_node);
0649     gpioirqchip->parent_domain = parent_domain;
0650     gpioirqchip->child_to_parent_hwirq = msc313e_gpio_child_to_parent_hwirq;
0651     gpioirqchip->populate_parent_alloc_arg = msc313_gpio_populate_parent_fwspec;
0652     gpioirqchip->handler = handle_bad_irq;
0653     gpioirqchip->default_type = IRQ_TYPE_NONE;
0654
0655     return devm_gpiochip_add_data(dev, gpiochip, gpio);
0656 }
0657
0658 static int msc313_gpio_remove(struct platform_device *pdev)
0659 {
0660     return 0;
0661 }
0662
0663 static const struct of_device_id msc313_gpio_of_match[] = {
0664 #ifdef CONFIG_MACH_INFINITY
0665     {
0666         .compatible = "mstar,msc313-gpio",
0667         .data = &msc313_data,
0668     },
0669     {
0670         .compatible = "sstar,ssd20xd-gpio",
0671         .data = &ssd20xd_data,
0672     },
0673 #endif
0674     { }
0675 };
0676
0677 /*
0678  * The GPIO controller loses the state of the registers when the
0679  * SoC goes into suspend to memory mode so we need to save some
0680  * of the register bits before suspending and put it back when resuming
0681  */
0682 static int __maybe_unused msc313_gpio_suspend(struct device *dev)
0683 {
0684     struct msc313_gpio *gpio = dev_get_drvdata(dev);
0685     int i;
0686
0687     for (i = 0; i < gpio->gpio_data->num; i++)
0688         gpio->saved[i] = readb_relaxed(gpio->base + gpio->gpio_data->offsets[i]) & MSC313_GPIO_BITSTOSAVE;
0689
0690     return 0;
0691 }
0692
0693 static int __maybe_unused msc313_gpio_resume(struct device *dev)
0694 {
0695     struct msc313_gpio *gpio = dev_get_drvdata(dev);
0696     int i;
0697
0698     for (i = 0; i < gpio->gpio_data->num; i++)
0699         writeb_relaxed(gpio->saved[i], gpio->base + gpio->gpio_data->offsets[i]);
0700
0701     return 0;
0702 }
0703
0704 static SIMPLE_DEV_PM_OPS(msc313_gpio_ops, msc313_gpio_suspend, msc313_gpio_resume);
0705
0706 static struct platform_driver msc313_gpio_driver = {
0707     .driver = {
0708         .name = DRIVER_NAME,
0709         .of_match_table = msc313_gpio_of_match,
0710         .pm = &msc313_gpio_ops,
0711     },
0712     .probe = msc313_gpio_probe,
0713     .remove = msc313_gpio_remove,
0714 };
0715 builtin_platform_driver(msc313_gpio_driver);