drivers/gpio/gpio-mpc8xxx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
0004  *
0005  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
0006  * Copyright (C) 2016 Freescale Semiconductor Inc.
0007  */
0008
0009 #include <linux/acpi.h>
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/io.h>
0014 #include <linux/of.h>
0015 #include <linux/of_gpio.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/property.h>
0020 #include <linux/mod_devicetable.h>
0021 #include <linux/slab.h>
0022 #include <linux/irq.h>
0023 #include <linux/gpio/driver.h>
0024 #include <linux/bitops.h>
0025 #include <linux/interrupt.h>
0026
0027 #define MPC8XXX_GPIO_PINS   32
0028
0029 #define GPIO_DIR        0x00
0030 #define GPIO_ODR        0x04
0031 #define GPIO_DAT        0x08
0032 #define GPIO_IER        0x0c
0033 #define GPIO_IMR        0x10
0034 #define GPIO_ICR        0x14
0035 #define GPIO_ICR2       0x18
0036 #define GPIO_IBE        0x18
0037
0038 struct mpc8xxx_gpio_chip {
0039     struct gpio_chip    gc;
0040     void __iomem *regs;
0041     raw_spinlock_t lock;
0042
0043     int (*direction_output)(struct gpio_chip *chip,
0044                 unsigned offset, int value);
0045
0046     struct irq_domain *irq;
0047     int irqn;
0048 };
0049
0050 /*
0051  * This hardware has a big endian bit assignment such that GPIO line 0 is
0052  * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
0053  * This inline helper give the right bitmask for a certain line.
0054  */
0055 static inline u32 mpc_pin2mask(unsigned int offset)
0056 {
0057     return BIT(31 - offset);
0058 }
0059
0060 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
0061  * defined as output cannot be determined by reading GPDAT register,
0062  * so we use shadow data register instead. The status of input pins
0063  * is determined by reading GPDAT register.
0064  */
0065 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
0066 {
0067     u32 val;
0068     struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0069     u32 out_mask, out_shadow;
0070
0071     out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR);
0072     val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask;
0073     out_shadow = gc->bgpio_data & out_mask;
0074
0075     return !!((val | out_shadow) & mpc_pin2mask(gpio));
0076 }
0077
0078 static int mpc5121_gpio_dir_out(struct gpio_chip *gc,
0079                 unsigned int gpio, int val)
0080 {
0081     struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0082     /* GPIO 28..31 are input only on MPC5121 */
0083     if (gpio >= 28)
0084         return -EINVAL;
0085
0086     return mpc8xxx_gc->direction_output(gc, gpio, val);
0087 }
0088
0089 static int mpc5125_gpio_dir_out(struct gpio_chip *gc,
0090                 unsigned int gpio, int val)
0091 {
0092     struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0093     /* GPIO 0..3 are input only on MPC5125 */
0094     if (gpio <= 3)
0095         return -EINVAL;
0096
0097     return mpc8xxx_gc->direction_output(gc, gpio, val);
0098 }
0099
0100 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
0101 {
0102     struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);
0103
0104     if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
0105         return irq_create_mapping(mpc8xxx_gc->irq, offset);
0106     else
0107         return -ENXIO;
0108 }
0109
0110 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data)
0111 {
0112     struct mpc8xxx_gpio_chip *mpc8xxx_gc = data;
0113     struct gpio_chip *gc = &mpc8xxx_gc->gc;
0114     unsigned long mask;
0115     int i;
0116
0117     mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER)
0118         & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR);
0119     for_each_set_bit(i, &mask, 32)
0120         generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i);
0121
0122     return IRQ_HANDLED;
0123 }
0124
0125 static void mpc8xxx_irq_unmask(struct irq_data *d)
0126 {
0127     struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
0128     struct gpio_chip *gc = &mpc8xxx_gc->gc;
0129     unsigned long flags;
0130
0131     raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0132
0133     gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
0134         gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
0135         | mpc_pin2mask(irqd_to_hwirq(d)));
0136
0137     raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0138 }
0139
0140 static void mpc8xxx_irq_mask(struct irq_data *d)
0141 {
0142     struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
0143     struct gpio_chip *gc = &mpc8xxx_gc->gc;
0144     unsigned long flags;
0145
0146     raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0147
0148     gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR,
0149         gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR)
0150         & ~mpc_pin2mask(irqd_to_hwirq(d)));
0151
0152     raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0153 }
0154
0155 static void mpc8xxx_irq_ack(struct irq_data *d)
0156 {
0157     struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
0158     struct gpio_chip *gc = &mpc8xxx_gc->gc;
0159
0160     gc->write_reg(mpc8xxx_gc->regs + GPIO_IER,
0161               mpc_pin2mask(irqd_to_hwirq(d)));
0162 }
0163
0164 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
0165 {
0166     struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
0167     struct gpio_chip *gc = &mpc8xxx_gc->gc;
0168     unsigned long flags;
0169
0170     switch (flow_type) {
0171     case IRQ_TYPE_EDGE_FALLING:
0172     case IRQ_TYPE_LEVEL_LOW:
0173         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0174         gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
0175             gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
0176             | mpc_pin2mask(irqd_to_hwirq(d)));
0177         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0178         break;
0179
0180     case IRQ_TYPE_EDGE_BOTH:
0181         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0182         gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
0183             gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
0184             & ~mpc_pin2mask(irqd_to_hwirq(d)));
0185         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0186         break;
0187
0188     default:
0189         return -EINVAL;
0190     }
0191
0192     return 0;
0193 }
0194
0195 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
0196 {
0197     struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
0198     struct gpio_chip *gc = &mpc8xxx_gc->gc;
0199     unsigned long gpio = irqd_to_hwirq(d);
0200     void __iomem *reg;
0201     unsigned int shift;
0202     unsigned long flags;
0203
0204     if (gpio < 16) {
0205         reg = mpc8xxx_gc->regs + GPIO_ICR;
0206         shift = (15 - gpio) * 2;
0207     } else {
0208         reg = mpc8xxx_gc->regs + GPIO_ICR2;
0209         shift = (15 - (gpio % 16)) * 2;
0210     }
0211
0212     switch (flow_type) {
0213     case IRQ_TYPE_EDGE_FALLING:
0214     case IRQ_TYPE_LEVEL_LOW:
0215         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0216         gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
0217             | (2 << shift));
0218         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0219         break;
0220
0221     case IRQ_TYPE_EDGE_RISING:
0222     case IRQ_TYPE_LEVEL_HIGH:
0223         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0224         gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))
0225             | (1 << shift));
0226         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0227         break;
0228
0229     case IRQ_TYPE_EDGE_BOTH:
0230         raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
0231         gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)));
0232         raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
0233         break;
0234
0235     default:
0236         return -EINVAL;
0237     }
0238
0239     return 0;
0240 }
0241
0242 static struct irq_chip mpc8xxx_irq_chip = {
0243     .name       = "mpc8xxx-gpio",
0244     .irq_unmask = mpc8xxx_irq_unmask,
0245     .irq_mask   = mpc8xxx_irq_mask,
0246     .irq_ack    = mpc8xxx_irq_ack,
0247     /* this might get overwritten in mpc8xxx_probe() */
0248     .irq_set_type   = mpc8xxx_irq_set_type,
0249 };
0250
0251 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
0252                 irq_hw_number_t hwirq)
0253 {
0254     irq_set_chip_data(irq, h->host_data);
0255     irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq);
0256
0257     return 0;
0258 }
0259
0260 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
0261     .map    = mpc8xxx_gpio_irq_map,
0262     .xlate  = irq_domain_xlate_twocell,
0263 };
0264
0265 struct mpc8xxx_gpio_devtype {
0266     int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int);
0267     int (*gpio_get)(struct gpio_chip *, unsigned int);
0268     int (*irq_set_type)(struct irq_data *, unsigned int);
0269 };
0270
0271 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
0272     .gpio_dir_out = mpc5121_gpio_dir_out,
0273     .irq_set_type = mpc512x_irq_set_type,
0274 };
0275
0276 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
0277     .gpio_dir_out = mpc5125_gpio_dir_out,
0278     .irq_set_type = mpc512x_irq_set_type,
0279 };
0280
0281 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = {
0282     .gpio_get = mpc8572_gpio_get,
0283 };
0284
0285 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = {
0286     .irq_set_type = mpc8xxx_irq_set_type,
0287 };
0288
0289 static const struct of_device_id mpc8xxx_gpio_ids[] = {
0290     { .compatible = "fsl,mpc8349-gpio", },
0291     { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, },
0292     { .compatible = "fsl,mpc8610-gpio", },
0293     { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
0294     { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
0295     { .compatible = "fsl,pq3-gpio",     },
0296     { .compatible = "fsl,ls1028a-gpio", },
0297     { .compatible = "fsl,ls1088a-gpio", },
0298     { .compatible = "fsl,qoriq-gpio",   },
0299     {}
0300 };
0301
0302 static int mpc8xxx_probe(struct platform_device *pdev)
0303 {
0304     struct device_node *np = pdev->dev.of_node;
0305     struct mpc8xxx_gpio_chip *mpc8xxx_gc;
0306     struct gpio_chip    *gc;
0307     const struct mpc8xxx_gpio_devtype *devtype = NULL;
0308     struct fwnode_handle *fwnode;
0309     int ret;
0310
0311     mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL);
0312     if (!mpc8xxx_gc)
0313         return -ENOMEM;
0314
0315     platform_set_drvdata(pdev, mpc8xxx_gc);
0316
0317     raw_spin_lock_init(&mpc8xxx_gc->lock);
0318
0319     mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0);
0320     if (IS_ERR(mpc8xxx_gc->regs))
0321         return PTR_ERR(mpc8xxx_gc->regs);
0322
0323     gc = &mpc8xxx_gc->gc;
0324     gc->parent = &pdev->dev;
0325
0326     if (device_property_read_bool(&pdev->dev, "little-endian")) {
0327         ret = bgpio_init(gc, &pdev->dev, 4,
0328                  mpc8xxx_gc->regs + GPIO_DAT,
0329                  NULL, NULL,
0330                  mpc8xxx_gc->regs + GPIO_DIR, NULL,
0331                  BGPIOF_BIG_ENDIAN);
0332         if (ret)
0333             return ret;
0334         dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n");
0335     } else {
0336         ret = bgpio_init(gc, &pdev->dev, 4,
0337                  mpc8xxx_gc->regs + GPIO_DAT,
0338                  NULL, NULL,
0339                  mpc8xxx_gc->regs + GPIO_DIR, NULL,
0340                  BGPIOF_BIG_ENDIAN
0341                  | BGPIOF_BIG_ENDIAN_BYTE_ORDER);
0342         if (ret)
0343             return ret;
0344         dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n");
0345     }
0346
0347     mpc8xxx_gc->direction_output = gc->direction_output;
0348
0349     devtype = device_get_match_data(&pdev->dev);
0350     if (!devtype)
0351         devtype = &mpc8xxx_gpio_devtype_default;
0352
0353     /*
0354      * It's assumed that only a single type of gpio controller is available
0355      * on the current machine, so overwriting global data is fine.
0356      */
0357     if (devtype->irq_set_type)
0358         mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type;
0359
0360     if (devtype->gpio_dir_out)
0361         gc->direction_output = devtype->gpio_dir_out;
0362     if (devtype->gpio_get)
0363         gc->get = devtype->gpio_get;
0364
0365     gc->to_irq = mpc8xxx_gpio_to_irq;
0366
0367     /*
0368      * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
0369      * the input enable of each individual GPIO port.  When an individual
0370      * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
0371      * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
0372      * the port value to the GPIO Data Register.
0373      */
0374     fwnode = dev_fwnode(&pdev->dev);
0375     if (of_device_is_compatible(np, "fsl,qoriq-gpio") ||
0376         of_device_is_compatible(np, "fsl,ls1028a-gpio") ||
0377         of_device_is_compatible(np, "fsl,ls1088a-gpio") ||
0378         is_acpi_node(fwnode))
0379         gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);
0380
0381     ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc);
0382     if (ret) {
0383         dev_err(&pdev->dev,
0384             "GPIO chip registration failed with status %d\n", ret);
0385         return ret;
0386     }
0387
0388     mpc8xxx_gc->irqn = platform_get_irq(pdev, 0);
0389     if (mpc8xxx_gc->irqn < 0)
0390         return mpc8xxx_gc->irqn;
0391
0392     mpc8xxx_gc->irq = irq_domain_create_linear(fwnode,
0393                            MPC8XXX_GPIO_PINS,
0394                            &mpc8xxx_gpio_irq_ops,
0395                            mpc8xxx_gc);
0396
0397     if (!mpc8xxx_gc->irq)
0398         return 0;
0399
0400     /* ack and mask all irqs */
0401     gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
0402     gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
0403
0404     ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
0405                    mpc8xxx_gpio_irq_cascade,
0406                    IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade",
0407                    mpc8xxx_gc);
0408     if (ret) {
0409         dev_err(&pdev->dev,
0410             "failed to devm_request_irq(%d), ret = %d\n",
0411             mpc8xxx_gc->irqn, ret);
0412         goto err;
0413     }
0414
0415     return 0;
0416 err:
0417     irq_domain_remove(mpc8xxx_gc->irq);
0418     return ret;
0419 }
0420
0421 static int mpc8xxx_remove(struct platform_device *pdev)
0422 {
0423     struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev);
0424
0425     if (mpc8xxx_gc->irq) {
0426         irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL);
0427         irq_domain_remove(mpc8xxx_gc->irq);
0428     }
0429
0430     return 0;
0431 }
0432
0433 #ifdef CONFIG_ACPI
0434 static const struct acpi_device_id gpio_acpi_ids[] = {
0435     {"NXP0031",},
0436     { }
0437 };
0438 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids);
0439 #endif
0440
0441 static struct platform_driver mpc8xxx_plat_driver = {
0442     .probe      = mpc8xxx_probe,
0443     .remove     = mpc8xxx_remove,
0444     .driver     = {
0445         .name = "gpio-mpc8xxx",
0446         .of_match_table = mpc8xxx_gpio_ids,
0447         .acpi_match_table = ACPI_PTR(gpio_acpi_ids),
0448     },
0449 };
0450
0451 static int __init mpc8xxx_init(void)
0452 {
0453     return platform_driver_register(&mpc8xxx_plat_driver);
0454 }
0455
0456 arch_initcall(mpc8xxx_init);