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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Generic driver for memory-mapped GPIO controllers.
0004  *
0005  * Copyright 2008 MontaVista Software, Inc.
0006  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
0007  *
0008  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
0009  * ...``                                                         ```````..
0010  * ..The simplest form of a GPIO controller that the driver supports is``
0011  *  `.just a single "data" register, where GPIO state can be read and/or `
0012  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
0013  *        `````````
0014                                     ___
0015 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
0016 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
0017 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
0018                                                  `....trivial..'~`.```.```
0019  *                                                    ```````
0020  *  .```````~~~~`..`.``.``.
0021  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
0022  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
0023  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
0024  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
0025  *     ``.`.``...```                  ```.. output pins are also supported.`
0026  *                        ^^             `````.`````````.,``~``~``~~``````
0027  *                                                   .                  ^^
0028  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
0029  * .. The expectation is that in at least some cases .    ,-~~~-,
0030  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
0031  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
0032  *  ..````````......```````````                             \o_
0033  *                                                           |
0034  *                              ^^                          / \
0035  *
0036  *           ...`````~~`.....``.`..........``````.`.``.```........``.
0037  *            `  8, 16, 32 and 64 bits registers are supported, and``.
0038  *            . the number of GPIOs is determined by the width of   ~
0039  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
0040  *               `.......````.```
0041  */
0042 
0043 #include <linux/init.h>
0044 #include <linux/err.h>
0045 #include <linux/bug.h>
0046 #include <linux/kernel.h>
0047 #include <linux/module.h>
0048 #include <linux/spinlock.h>
0049 #include <linux/compiler.h>
0050 #include <linux/types.h>
0051 #include <linux/errno.h>
0052 #include <linux/log2.h>
0053 #include <linux/ioport.h>
0054 #include <linux/io.h>
0055 #include <linux/gpio/driver.h>
0056 #include <linux/slab.h>
0057 #include <linux/bitops.h>
0058 #include <linux/platform_device.h>
0059 #include <linux/mod_devicetable.h>
0060 #include <linux/of.h>
0061 #include <linux/of_device.h>
0062 
0063 static void bgpio_write8(void __iomem *reg, unsigned long data)
0064 {
0065     writeb(data, reg);
0066 }
0067 
0068 static unsigned long bgpio_read8(void __iomem *reg)
0069 {
0070     return readb(reg);
0071 }
0072 
0073 static void bgpio_write16(void __iomem *reg, unsigned long data)
0074 {
0075     writew(data, reg);
0076 }
0077 
0078 static unsigned long bgpio_read16(void __iomem *reg)
0079 {
0080     return readw(reg);
0081 }
0082 
0083 static void bgpio_write32(void __iomem *reg, unsigned long data)
0084 {
0085     writel(data, reg);
0086 }
0087 
0088 static unsigned long bgpio_read32(void __iomem *reg)
0089 {
0090     return readl(reg);
0091 }
0092 
0093 #if BITS_PER_LONG >= 64
0094 static void bgpio_write64(void __iomem *reg, unsigned long data)
0095 {
0096     writeq(data, reg);
0097 }
0098 
0099 static unsigned long bgpio_read64(void __iomem *reg)
0100 {
0101     return readq(reg);
0102 }
0103 #endif /* BITS_PER_LONG >= 64 */
0104 
0105 static void bgpio_write16be(void __iomem *reg, unsigned long data)
0106 {
0107     iowrite16be(data, reg);
0108 }
0109 
0110 static unsigned long bgpio_read16be(void __iomem *reg)
0111 {
0112     return ioread16be(reg);
0113 }
0114 
0115 static void bgpio_write32be(void __iomem *reg, unsigned long data)
0116 {
0117     iowrite32be(data, reg);
0118 }
0119 
0120 static unsigned long bgpio_read32be(void __iomem *reg)
0121 {
0122     return ioread32be(reg);
0123 }
0124 
0125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
0126 {
0127     if (gc->be_bits)
0128         return BIT(gc->bgpio_bits - 1 - line);
0129     return BIT(line);
0130 }
0131 
0132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
0133 {
0134     unsigned long pinmask = bgpio_line2mask(gc, gpio);
0135     bool dir = !!(gc->bgpio_dir & pinmask);
0136 
0137     if (dir)
0138         return !!(gc->read_reg(gc->reg_set) & pinmask);
0139     else
0140         return !!(gc->read_reg(gc->reg_dat) & pinmask);
0141 }
0142 
0143 /*
0144  * This assumes that the bits in the GPIO register are in native endianness.
0145  * We only assign the function pointer if we have that.
0146  */
0147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
0148                   unsigned long *bits)
0149 {
0150     unsigned long get_mask = 0;
0151     unsigned long set_mask = 0;
0152 
0153     /* Make sure we first clear any bits that are zero when we read the register */
0154     *bits &= ~*mask;
0155 
0156     set_mask = *mask & gc->bgpio_dir;
0157     get_mask = *mask & ~gc->bgpio_dir;
0158 
0159     if (set_mask)
0160         *bits |= gc->read_reg(gc->reg_set) & set_mask;
0161     if (get_mask)
0162         *bits |= gc->read_reg(gc->reg_dat) & get_mask;
0163 
0164     return 0;
0165 }
0166 
0167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
0168 {
0169     return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
0170 }
0171 
0172 /*
0173  * This only works if the bits in the GPIO register are in native endianness.
0174  */
0175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
0176                   unsigned long *bits)
0177 {
0178     /* Make sure we first clear any bits that are zero when we read the register */
0179     *bits &= ~*mask;
0180     *bits |= gc->read_reg(gc->reg_dat) & *mask;
0181     return 0;
0182 }
0183 
0184 /*
0185  * With big endian mirrored bit order it becomes more tedious.
0186  */
0187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
0188                  unsigned long *bits)
0189 {
0190     unsigned long readmask = 0;
0191     unsigned long val;
0192     int bit;
0193 
0194     /* Make sure we first clear any bits that are zero when we read the register */
0195     *bits &= ~*mask;
0196 
0197     /* Create a mirrored mask */
0198     for_each_set_bit(bit, mask, gc->ngpio)
0199         readmask |= bgpio_line2mask(gc, bit);
0200 
0201     /* Read the register */
0202     val = gc->read_reg(gc->reg_dat) & readmask;
0203 
0204     /*
0205      * Mirror the result into the "bits" result, this will give line 0
0206      * in bit 0 ... line 31 in bit 31 for a 32bit register.
0207      */
0208     for_each_set_bit(bit, &val, gc->ngpio)
0209         *bits |= bgpio_line2mask(gc, bit);
0210 
0211     return 0;
0212 }
0213 
0214 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
0215 {
0216 }
0217 
0218 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
0219 {
0220     unsigned long mask = bgpio_line2mask(gc, gpio);
0221     unsigned long flags;
0222 
0223     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0224 
0225     if (val)
0226         gc->bgpio_data |= mask;
0227     else
0228         gc->bgpio_data &= ~mask;
0229 
0230     gc->write_reg(gc->reg_dat, gc->bgpio_data);
0231 
0232     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0233 }
0234 
0235 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
0236                  int val)
0237 {
0238     unsigned long mask = bgpio_line2mask(gc, gpio);
0239 
0240     if (val)
0241         gc->write_reg(gc->reg_set, mask);
0242     else
0243         gc->write_reg(gc->reg_clr, mask);
0244 }
0245 
0246 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
0247 {
0248     unsigned long mask = bgpio_line2mask(gc, gpio);
0249     unsigned long flags;
0250 
0251     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0252 
0253     if (val)
0254         gc->bgpio_data |= mask;
0255     else
0256         gc->bgpio_data &= ~mask;
0257 
0258     gc->write_reg(gc->reg_set, gc->bgpio_data);
0259 
0260     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0261 }
0262 
0263 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
0264                      unsigned long *mask, unsigned long *bits,
0265                      unsigned long *set_mask,
0266                      unsigned long *clear_mask)
0267 {
0268     int i;
0269 
0270     *set_mask = 0;
0271     *clear_mask = 0;
0272 
0273     for_each_set_bit(i, mask, gc->bgpio_bits) {
0274         if (test_bit(i, bits))
0275             *set_mask |= bgpio_line2mask(gc, i);
0276         else
0277             *clear_mask |= bgpio_line2mask(gc, i);
0278     }
0279 }
0280 
0281 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
0282                       unsigned long *mask,
0283                       unsigned long *bits,
0284                       void __iomem *reg)
0285 {
0286     unsigned long flags;
0287     unsigned long set_mask, clear_mask;
0288 
0289     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0290 
0291     bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
0292 
0293     gc->bgpio_data |= set_mask;
0294     gc->bgpio_data &= ~clear_mask;
0295 
0296     gc->write_reg(reg, gc->bgpio_data);
0297 
0298     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0299 }
0300 
0301 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
0302                    unsigned long *bits)
0303 {
0304     bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
0305 }
0306 
0307 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
0308                    unsigned long *bits)
0309 {
0310     bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
0311 }
0312 
0313 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
0314                       unsigned long *mask,
0315                       unsigned long *bits)
0316 {
0317     unsigned long set_mask, clear_mask;
0318 
0319     bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
0320 
0321     if (set_mask)
0322         gc->write_reg(gc->reg_set, set_mask);
0323     if (clear_mask)
0324         gc->write_reg(gc->reg_clr, clear_mask);
0325 }
0326 
0327 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
0328 {
0329     return 0;
0330 }
0331 
0332 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
0333                 int val)
0334 {
0335     return -EINVAL;
0336 }
0337 
0338 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
0339                 int val)
0340 {
0341     gc->set(gc, gpio, val);
0342 
0343     return 0;
0344 }
0345 
0346 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
0347 {
0348     unsigned long flags;
0349 
0350     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0351 
0352     gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
0353 
0354     if (gc->reg_dir_in)
0355         gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
0356     if (gc->reg_dir_out)
0357         gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
0358 
0359     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0360 
0361     return 0;
0362 }
0363 
0364 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
0365 {
0366     /* Return 0 if output, 1 if input */
0367     if (gc->bgpio_dir_unreadable) {
0368         if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
0369             return GPIO_LINE_DIRECTION_OUT;
0370         return GPIO_LINE_DIRECTION_IN;
0371     }
0372 
0373     if (gc->reg_dir_out) {
0374         if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
0375             return GPIO_LINE_DIRECTION_OUT;
0376         return GPIO_LINE_DIRECTION_IN;
0377     }
0378 
0379     if (gc->reg_dir_in)
0380         if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
0381             return GPIO_LINE_DIRECTION_OUT;
0382 
0383     return GPIO_LINE_DIRECTION_IN;
0384 }
0385 
0386 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
0387 {
0388     unsigned long flags;
0389 
0390     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0391 
0392     gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
0393 
0394     if (gc->reg_dir_in)
0395         gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
0396     if (gc->reg_dir_out)
0397         gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
0398 
0399     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0400 }
0401 
0402 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,
0403                    int val)
0404 {
0405     bgpio_dir_out(gc, gpio, val);
0406     gc->set(gc, gpio, val);
0407     return 0;
0408 }
0409 
0410 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio,
0411                    int val)
0412 {
0413     gc->set(gc, gpio, val);
0414     bgpio_dir_out(gc, gpio, val);
0415     return 0;
0416 }
0417 
0418 static int bgpio_setup_accessors(struct device *dev,
0419                  struct gpio_chip *gc,
0420                  bool byte_be)
0421 {
0422 
0423     switch (gc->bgpio_bits) {
0424     case 8:
0425         gc->read_reg    = bgpio_read8;
0426         gc->write_reg   = bgpio_write8;
0427         break;
0428     case 16:
0429         if (byte_be) {
0430             gc->read_reg    = bgpio_read16be;
0431             gc->write_reg   = bgpio_write16be;
0432         } else {
0433             gc->read_reg    = bgpio_read16;
0434             gc->write_reg   = bgpio_write16;
0435         }
0436         break;
0437     case 32:
0438         if (byte_be) {
0439             gc->read_reg    = bgpio_read32be;
0440             gc->write_reg   = bgpio_write32be;
0441         } else {
0442             gc->read_reg    = bgpio_read32;
0443             gc->write_reg   = bgpio_write32;
0444         }
0445         break;
0446 #if BITS_PER_LONG >= 64
0447     case 64:
0448         if (byte_be) {
0449             dev_err(dev,
0450                 "64 bit big endian byte order unsupported\n");
0451             return -EINVAL;
0452         } else {
0453             gc->read_reg    = bgpio_read64;
0454             gc->write_reg   = bgpio_write64;
0455         }
0456         break;
0457 #endif /* BITS_PER_LONG >= 64 */
0458     default:
0459         dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
0460         return -EINVAL;
0461     }
0462 
0463     return 0;
0464 }
0465 
0466 /*
0467  * Create the device and allocate the resources.  For setting GPIO's there are
0468  * three supported configurations:
0469  *
0470  *  - single input/output register resource (named "dat").
0471  *  - set/clear pair (named "set" and "clr").
0472  *  - single output register resource and single input resource ("set" and
0473  *  dat").
0474  *
0475  * For the single output register, this drives a 1 by setting a bit and a zero
0476  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
0477  * in the set register and clears it by setting a bit in the clear register.
0478  * The configuration is detected by which resources are present.
0479  *
0480  * For setting the GPIO direction, there are three supported configurations:
0481  *
0482  *  - simple bidirection GPIO that requires no configuration.
0483  *  - an output direction register (named "dirout") where a 1 bit
0484  *  indicates the GPIO is an output.
0485  *  - an input direction register (named "dirin") where a 1 bit indicates
0486  *  the GPIO is an input.
0487  */
0488 static int bgpio_setup_io(struct gpio_chip *gc,
0489               void __iomem *dat,
0490               void __iomem *set,
0491               void __iomem *clr,
0492               unsigned long flags)
0493 {
0494 
0495     gc->reg_dat = dat;
0496     if (!gc->reg_dat)
0497         return -EINVAL;
0498 
0499     if (set && clr) {
0500         gc->reg_set = set;
0501         gc->reg_clr = clr;
0502         gc->set = bgpio_set_with_clear;
0503         gc->set_multiple = bgpio_set_multiple_with_clear;
0504     } else if (set && !clr) {
0505         gc->reg_set = set;
0506         gc->set = bgpio_set_set;
0507         gc->set_multiple = bgpio_set_multiple_set;
0508     } else if (flags & BGPIOF_NO_OUTPUT) {
0509         gc->set = bgpio_set_none;
0510         gc->set_multiple = NULL;
0511     } else {
0512         gc->set = bgpio_set;
0513         gc->set_multiple = bgpio_set_multiple;
0514     }
0515 
0516     if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
0517         (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
0518         gc->get = bgpio_get_set;
0519         if (!gc->be_bits)
0520             gc->get_multiple = bgpio_get_set_multiple;
0521         /*
0522          * We deliberately avoid assigning the ->get_multiple() call
0523          * for big endian mirrored registers which are ALSO reflecting
0524          * their value in the set register when used as output. It is
0525          * simply too much complexity, let the GPIO core fall back to
0526          * reading each line individually in that fringe case.
0527          */
0528     } else {
0529         gc->get = bgpio_get;
0530         if (gc->be_bits)
0531             gc->get_multiple = bgpio_get_multiple_be;
0532         else
0533             gc->get_multiple = bgpio_get_multiple;
0534     }
0535 
0536     return 0;
0537 }
0538 
0539 static int bgpio_setup_direction(struct gpio_chip *gc,
0540                  void __iomem *dirout,
0541                  void __iomem *dirin,
0542                  unsigned long flags)
0543 {
0544     if (dirout || dirin) {
0545         gc->reg_dir_out = dirout;
0546         gc->reg_dir_in = dirin;
0547         if (flags & BGPIOF_NO_SET_ON_INPUT)
0548             gc->direction_output = bgpio_dir_out_dir_first;
0549         else
0550             gc->direction_output = bgpio_dir_out_val_first;
0551         gc->direction_input = bgpio_dir_in;
0552         gc->get_direction = bgpio_get_dir;
0553     } else {
0554         if (flags & BGPIOF_NO_OUTPUT)
0555             gc->direction_output = bgpio_dir_out_err;
0556         else
0557             gc->direction_output = bgpio_simple_dir_out;
0558         gc->direction_input = bgpio_simple_dir_in;
0559     }
0560 
0561     return 0;
0562 }
0563 
0564 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
0565 {
0566     if (gpio_pin < chip->ngpio)
0567         return 0;
0568 
0569     return -EINVAL;
0570 }
0571 
0572 /**
0573  * bgpio_init() - Initialize generic GPIO accessor functions
0574  * @gc: the GPIO chip to set up
0575  * @dev: the parent device of the new GPIO chip (compulsory)
0576  * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
0577  * @dat: MMIO address for the register to READ the value of the GPIO lines, it
0578  *  is expected that a 1 in the corresponding bit in this register means the
0579  *  line is asserted
0580  * @set: MMIO address for the register to SET the value of the GPIO lines, it is
0581  *  expected that we write the line with 1 in this register to drive the GPIO line
0582  *  high.
0583  * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
0584  *  expected that we write the line with 1 in this register to drive the GPIO line
0585  *  low. It is allowed to leave this address as NULL, in that case the SET register
0586  *  will be assumed to also clear the GPIO lines, by actively writing the line
0587  *  with 0.
0588  * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
0589  *  that setting a line to 1 in this register will turn that line into an
0590  *  output line. Conversely, setting the line to 0 will turn that line into
0591  *  an input.
0592  * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
0593  *  that setting a line to 1 in this register will turn that line into an
0594  *  input line. Conversely, setting the line to 0 will turn that line into
0595  *  an output.
0596  * @flags: Different flags that will affect the behaviour of the device, such as
0597  *  endianness etc.
0598  */
0599 int bgpio_init(struct gpio_chip *gc, struct device *dev,
0600            unsigned long sz, void __iomem *dat, void __iomem *set,
0601            void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
0602            unsigned long flags)
0603 {
0604     int ret;
0605 
0606     if (!is_power_of_2(sz))
0607         return -EINVAL;
0608 
0609     gc->bgpio_bits = sz * 8;
0610     if (gc->bgpio_bits > BITS_PER_LONG)
0611         return -EINVAL;
0612 
0613     raw_spin_lock_init(&gc->bgpio_lock);
0614     gc->parent = dev;
0615     gc->label = dev_name(dev);
0616     gc->base = -1;
0617     gc->ngpio = gc->bgpio_bits;
0618     gc->request = bgpio_request;
0619     gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
0620 
0621     ret = bgpio_setup_io(gc, dat, set, clr, flags);
0622     if (ret)
0623         return ret;
0624 
0625     ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
0626     if (ret)
0627         return ret;
0628 
0629     ret = bgpio_setup_direction(gc, dirout, dirin, flags);
0630     if (ret)
0631         return ret;
0632 
0633     gc->bgpio_data = gc->read_reg(gc->reg_dat);
0634     if (gc->set == bgpio_set_set &&
0635             !(flags & BGPIOF_UNREADABLE_REG_SET))
0636         gc->bgpio_data = gc->read_reg(gc->reg_set);
0637 
0638     if (flags & BGPIOF_UNREADABLE_REG_DIR)
0639         gc->bgpio_dir_unreadable = true;
0640 
0641     /*
0642      * Inspect hardware to find initial direction setting.
0643      */
0644     if ((gc->reg_dir_out || gc->reg_dir_in) &&
0645         !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
0646         if (gc->reg_dir_out)
0647             gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
0648         else if (gc->reg_dir_in)
0649             gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
0650         /*
0651          * If we have two direction registers, synchronise
0652          * input setting to output setting, the library
0653          * can not handle a line being input and output at
0654          * the same time.
0655          */
0656         if (gc->reg_dir_out && gc->reg_dir_in)
0657             gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
0658     }
0659 
0660     return ret;
0661 }
0662 EXPORT_SYMBOL_GPL(bgpio_init);
0663 
0664 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
0665 
0666 static void __iomem *bgpio_map(struct platform_device *pdev,
0667                    const char *name,
0668                    resource_size_t sane_sz)
0669 {
0670     struct resource *r;
0671     resource_size_t sz;
0672 
0673     r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
0674     if (!r)
0675         return NULL;
0676 
0677     sz = resource_size(r);
0678     if (sz != sane_sz)
0679         return IOMEM_ERR_PTR(-EINVAL);
0680 
0681     return devm_ioremap_resource(&pdev->dev, r);
0682 }
0683 
0684 #ifdef CONFIG_OF
0685 static const struct of_device_id bgpio_of_match[] = {
0686     { .compatible = "brcm,bcm6345-gpio" },
0687     { .compatible = "wd,mbl-gpio" },
0688     { .compatible = "ni,169445-nand-gpio" },
0689     { }
0690 };
0691 MODULE_DEVICE_TABLE(of, bgpio_of_match);
0692 
0693 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
0694                       unsigned long *flags)
0695 {
0696     struct bgpio_pdata *pdata;
0697 
0698     if (!of_match_device(bgpio_of_match, &pdev->dev))
0699         return NULL;
0700 
0701     pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
0702                  GFP_KERNEL);
0703     if (!pdata)
0704         return ERR_PTR(-ENOMEM);
0705 
0706     pdata->base = -1;
0707 
0708     if (of_device_is_big_endian(pdev->dev.of_node))
0709         *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
0710 
0711     if (of_property_read_bool(pdev->dev.of_node, "no-output"))
0712         *flags |= BGPIOF_NO_OUTPUT;
0713 
0714     return pdata;
0715 }
0716 #else
0717 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
0718                       unsigned long *flags)
0719 {
0720     return NULL;
0721 }
0722 #endif /* CONFIG_OF */
0723 
0724 static int bgpio_pdev_probe(struct platform_device *pdev)
0725 {
0726     struct device *dev = &pdev->dev;
0727     struct resource *r;
0728     void __iomem *dat;
0729     void __iomem *set;
0730     void __iomem *clr;
0731     void __iomem *dirout;
0732     void __iomem *dirin;
0733     unsigned long sz;
0734     unsigned long flags = 0;
0735     int err;
0736     struct gpio_chip *gc;
0737     struct bgpio_pdata *pdata;
0738 
0739     pdata = bgpio_parse_dt(pdev, &flags);
0740     if (IS_ERR(pdata))
0741         return PTR_ERR(pdata);
0742 
0743     if (!pdata) {
0744         pdata = dev_get_platdata(dev);
0745         flags = pdev->id_entry->driver_data;
0746     }
0747 
0748     r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
0749     if (!r)
0750         return -EINVAL;
0751 
0752     sz = resource_size(r);
0753 
0754     dat = bgpio_map(pdev, "dat", sz);
0755     if (IS_ERR(dat))
0756         return PTR_ERR(dat);
0757 
0758     set = bgpio_map(pdev, "set", sz);
0759     if (IS_ERR(set))
0760         return PTR_ERR(set);
0761 
0762     clr = bgpio_map(pdev, "clr", sz);
0763     if (IS_ERR(clr))
0764         return PTR_ERR(clr);
0765 
0766     dirout = bgpio_map(pdev, "dirout", sz);
0767     if (IS_ERR(dirout))
0768         return PTR_ERR(dirout);
0769 
0770     dirin = bgpio_map(pdev, "dirin", sz);
0771     if (IS_ERR(dirin))
0772         return PTR_ERR(dirin);
0773 
0774     gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
0775     if (!gc)
0776         return -ENOMEM;
0777 
0778     err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
0779     if (err)
0780         return err;
0781 
0782     if (pdata) {
0783         if (pdata->label)
0784             gc->label = pdata->label;
0785         gc->base = pdata->base;
0786         if (pdata->ngpio > 0)
0787             gc->ngpio = pdata->ngpio;
0788     }
0789 
0790     platform_set_drvdata(pdev, gc);
0791 
0792     return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
0793 }
0794 
0795 static const struct platform_device_id bgpio_id_table[] = {
0796     {
0797         .name       = "basic-mmio-gpio",
0798         .driver_data    = 0,
0799     }, {
0800         .name       = "basic-mmio-gpio-be",
0801         .driver_data    = BGPIOF_BIG_ENDIAN,
0802     },
0803     { }
0804 };
0805 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
0806 
0807 static struct platform_driver bgpio_driver = {
0808     .driver = {
0809         .name = "basic-mmio-gpio",
0810         .of_match_table = of_match_ptr(bgpio_of_match),
0811     },
0812     .id_table = bgpio_id_table,
0813     .probe = bgpio_pdev_probe,
0814 };
0815 
0816 module_platform_driver(bgpio_driver);
0817 
0818 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
0819 
0820 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
0821 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
0822 MODULE_LICENSE("GPL");
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