drivers/gpio/gpio-mlxbf2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /*
0004  * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
0005  */
0006
0007 #include <linux/bitfield.h>
0008 #include <linux/bitops.h>
0009 #include <linux/device.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/ioport.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/module.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pm.h>
0019 #include <linux/resource.h>
0020 #include <linux/spinlock.h>
0021 #include <linux/types.h>
0022
0023 /*
0024  * There are 3 YU GPIO blocks:
0025  * gpio[0]: HOST_GPIO0->HOST_GPIO31
0026  * gpio[1]: HOST_GPIO32->HOST_GPIO63
0027  * gpio[2]: HOST_GPIO64->HOST_GPIO69
0028  */
0029 #define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
0030
0031 /*
0032  * arm_gpio_lock register:
0033  * bit[31]  lock status: active if set
0034  * bit[15:0]    set lock
0035  * The lock is enabled only if 0xd42f is written to this field
0036  */
0037 #define YU_ARM_GPIO_LOCK_ADDR       0x2801088
0038 #define YU_ARM_GPIO_LOCK_SIZE       0x8
0039 #define YU_LOCK_ACTIVE_BIT(val)     (val >> 31)
0040 #define YU_ARM_GPIO_LOCK_ACQUIRE    0xd42f
0041 #define YU_ARM_GPIO_LOCK_RELEASE    0x0
0042
0043 /*
0044  * gpio[x] block registers and their offset
0045  */
0046 #define YU_GPIO_DATAIN          0x04
0047 #define YU_GPIO_MODE1           0x08
0048 #define YU_GPIO_MODE0           0x0c
0049 #define YU_GPIO_DATASET         0x14
0050 #define YU_GPIO_DATACLEAR       0x18
0051 #define YU_GPIO_CAUSE_RISE_EN       0x44
0052 #define YU_GPIO_CAUSE_FALL_EN       0x48
0053 #define YU_GPIO_MODE1_CLEAR     0x50
0054 #define YU_GPIO_MODE0_SET       0x54
0055 #define YU_GPIO_MODE0_CLEAR     0x58
0056 #define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0   0x80
0057 #define YU_GPIO_CAUSE_OR_EVTEN0     0x94
0058 #define YU_GPIO_CAUSE_OR_CLRCAUSE   0x98
0059
0060 struct mlxbf2_gpio_context_save_regs {
0061     u32 gpio_mode0;
0062     u32 gpio_mode1;
0063 };
0064
0065 /* BlueField-2 gpio block context structure. */
0066 struct mlxbf2_gpio_context {
0067     struct gpio_chip gc;
0068     struct irq_chip irq_chip;
0069
0070     /* YU GPIO blocks address */
0071     void __iomem *gpio_io;
0072
0073     struct mlxbf2_gpio_context_save_regs *csave_regs;
0074 };
0075
0076 /* BlueField-2 gpio shared structure. */
0077 struct mlxbf2_gpio_param {
0078     void __iomem *io;
0079     struct resource *res;
0080     struct mutex *lock;
0081 };
0082
0083 static struct resource yu_arm_gpio_lock_res =
0084     DEFINE_RES_MEM_NAMED(YU_ARM_GPIO_LOCK_ADDR, YU_ARM_GPIO_LOCK_SIZE, "YU_ARM_GPIO_LOCK");
0085
0086 static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
0087
0088 static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
0089     .res = &yu_arm_gpio_lock_res,
0090     .lock = &yu_arm_gpio_lock_mutex,
0091 };
0092
0093 /* Request memory region and map yu_arm_gpio_lock resource */
0094 static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
0095 {
0096     struct device *dev = &pdev->dev;
0097     struct resource *res;
0098     resource_size_t size;
0099     int ret = 0;
0100
0101     mutex_lock(yu_arm_gpio_lock_param.lock);
0102
0103     /* Check if the memory map already exists */
0104     if (yu_arm_gpio_lock_param.io)
0105         goto exit;
0106
0107     res = yu_arm_gpio_lock_param.res;
0108     size = resource_size(res);
0109
0110     if (!devm_request_mem_region(dev, res->start, size, res->name)) {
0111         ret = -EFAULT;
0112         goto exit;
0113     }
0114
0115     yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
0116     if (!yu_arm_gpio_lock_param.io)
0117         ret = -ENOMEM;
0118
0119 exit:
0120     mutex_unlock(yu_arm_gpio_lock_param.lock);
0121
0122     return ret;
0123 }
0124
0125 /*
0126  * Acquire the YU arm_gpio_lock to be able to change the direction
0127  * mode. If the lock_active bit is already set, return an error.
0128  */
0129 static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
0130 {
0131     u32 arm_gpio_lock_val;
0132
0133     mutex_lock(yu_arm_gpio_lock_param.lock);
0134     raw_spin_lock(&gs->gc.bgpio_lock);
0135
0136     arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
0137
0138     /*
0139      * When lock active bit[31] is set, ModeX is write enabled
0140      */
0141     if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
0142         raw_spin_unlock(&gs->gc.bgpio_lock);
0143         mutex_unlock(yu_arm_gpio_lock_param.lock);
0144         return -EINVAL;
0145     }
0146
0147     writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
0148
0149     return 0;
0150 }
0151
0152 /*
0153  * Release the YU arm_gpio_lock after changing the direction mode.
0154  */
0155 static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
0156     __releases(&gs->gc.bgpio_lock)
0157     __releases(yu_arm_gpio_lock_param.lock)
0158 {
0159     writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
0160     raw_spin_unlock(&gs->gc.bgpio_lock);
0161     mutex_unlock(yu_arm_gpio_lock_param.lock);
0162 }
0163
0164 /*
0165  * mode0 and mode1 are both locked by the gpio_lock field.
0166  *
0167  * Together, mode0 and mode1 define the gpio Mode dependeing also
0168  * on Reg_DataOut.
0169  *
0170  * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
0171  *
0172  * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
0173  * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
0174  * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
0175  * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
0176  */
0177
0178 /*
0179  * Set input direction:
0180  * {mode1,mode0} = {0,0}
0181  */
0182 static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
0183                        unsigned int offset)
0184 {
0185     struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
0186     int ret;
0187
0188     /*
0189      * Although the arm_gpio_lock was set in the probe function, check again
0190      * if it is still enabled to be able to write to the ModeX registers.
0191      */
0192     ret = mlxbf2_gpio_lock_acquire(gs);
0193     if (ret < 0)
0194         return ret;
0195
0196     writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
0197     writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
0198
0199     mlxbf2_gpio_lock_release(gs);
0200
0201     return ret;
0202 }
0203
0204 /*
0205  * Set output direction:
0206  * {mode1,mode0} = {0,1}
0207  */
0208 static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
0209                     unsigned int offset,
0210                     int value)
0211 {
0212     struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
0213     int ret = 0;
0214
0215     /*
0216      * Although the arm_gpio_lock was set in the probe function,
0217      * check again it is still enabled to be able to write to the
0218      * ModeX registers.
0219      */
0220     ret = mlxbf2_gpio_lock_acquire(gs);
0221     if (ret < 0)
0222         return ret;
0223
0224     writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
0225     writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
0226
0227     mlxbf2_gpio_lock_release(gs);
0228
0229     return ret;
0230 }
0231
0232 static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
0233 {
0234     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0235     struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
0236     int offset = irqd_to_hwirq(irqd);
0237     unsigned long flags;
0238     u32 val;
0239
0240     raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
0241     val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
0242     val |= BIT(offset);
0243     writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
0244
0245     val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
0246     val |= BIT(offset);
0247     writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
0248     raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
0249 }
0250
0251 static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
0252 {
0253     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0254     struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
0255     int offset = irqd_to_hwirq(irqd);
0256     unsigned long flags;
0257     u32 val;
0258
0259     raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
0260     val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
0261     val &= ~BIT(offset);
0262     writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
0263     raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
0264 }
0265
0266 static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
0267 {
0268     struct mlxbf2_gpio_context *gs = ptr;
0269     struct gpio_chip *gc = &gs->gc;
0270     unsigned long pending;
0271     u32 level;
0272
0273     pending = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0);
0274     writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
0275
0276     for_each_set_bit(level, &pending, gc->ngpio) {
0277         int gpio_irq = irq_find_mapping(gc->irq.domain, level);
0278         generic_handle_irq(gpio_irq);
0279     }
0280
0281     return IRQ_RETVAL(pending);
0282 }
0283
0284 static int
0285 mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
0286 {
0287     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0288     struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
0289     int offset = irqd_to_hwirq(irqd);
0290     unsigned long flags;
0291     bool fall = false;
0292     bool rise = false;
0293     u32 val;
0294
0295     switch (type & IRQ_TYPE_SENSE_MASK) {
0296     case IRQ_TYPE_EDGE_BOTH:
0297         fall = true;
0298         rise = true;
0299         break;
0300     case IRQ_TYPE_EDGE_RISING:
0301         rise = true;
0302         break;
0303     case IRQ_TYPE_EDGE_FALLING:
0304         fall = true;
0305         break;
0306     default:
0307         return -EINVAL;
0308     }
0309
0310     raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
0311     if (fall) {
0312         val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
0313         val |= BIT(offset);
0314         writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
0315     }
0316
0317     if (rise) {
0318         val = readl(gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
0319         val |= BIT(offset);
0320         writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
0321     }
0322     raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
0323
0324     return 0;
0325 }
0326
0327 /* BlueField-2 GPIO driver initialization routine. */
0328 static int
0329 mlxbf2_gpio_probe(struct platform_device *pdev)
0330 {
0331     struct mlxbf2_gpio_context *gs;
0332     struct device *dev = &pdev->dev;
0333     struct gpio_irq_chip *girq;
0334     struct gpio_chip *gc;
0335     unsigned int npins;
0336     const char *name;
0337     int ret, irq;
0338
0339     name = dev_name(dev);
0340
0341     gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
0342     if (!gs)
0343         return -ENOMEM;
0344
0345     /* YU GPIO block address */
0346     gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
0347     if (IS_ERR(gs->gpio_io))
0348         return PTR_ERR(gs->gpio_io);
0349
0350     ret = mlxbf2_gpio_get_lock_res(pdev);
0351     if (ret) {
0352         dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n");
0353         return ret;
0354     }
0355
0356     if (device_property_read_u32(dev, "npins", &npins))
0357         npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
0358
0359     gc = &gs->gc;
0360
0361     ret = bgpio_init(gc, dev, 4,
0362             gs->gpio_io + YU_GPIO_DATAIN,
0363             gs->gpio_io + YU_GPIO_DATASET,
0364             gs->gpio_io + YU_GPIO_DATACLEAR,
0365             NULL,
0366             NULL,
0367             0);
0368
0369     if (ret) {
0370         dev_err(dev, "bgpio_init failed\n");
0371         return ret;
0372     }
0373
0374     gc->direction_input = mlxbf2_gpio_direction_input;
0375     gc->direction_output = mlxbf2_gpio_direction_output;
0376     gc->ngpio = npins;
0377     gc->owner = THIS_MODULE;
0378
0379     irq = platform_get_irq(pdev, 0);
0380     if (irq >= 0) {
0381         gs->irq_chip.name = name;
0382         gs->irq_chip.irq_set_type = mlxbf2_gpio_irq_set_type;
0383         gs->irq_chip.irq_enable = mlxbf2_gpio_irq_enable;
0384         gs->irq_chip.irq_disable = mlxbf2_gpio_irq_disable;
0385
0386         girq = &gs->gc.irq;
0387         girq->chip = &gs->irq_chip;
0388         girq->handler = handle_simple_irq;
0389         girq->default_type = IRQ_TYPE_NONE;
0390         /* This will let us handle the parent IRQ in the driver */
0391         girq->num_parents = 0;
0392         girq->parents = NULL;
0393         girq->parent_handler = NULL;
0394
0395         /*
0396          * Directly request the irq here instead of passing
0397          * a flow-handler because the irq is shared.
0398          */
0399         ret = devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler,
0400                        IRQF_SHARED, name, gs);
0401         if (ret) {
0402             dev_err(dev, "failed to request IRQ");
0403             return ret;
0404         }
0405     }
0406
0407     platform_set_drvdata(pdev, gs);
0408
0409     ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
0410     if (ret) {
0411         dev_err(dev, "Failed adding memory mapped gpiochip\n");
0412         return ret;
0413     }
0414
0415     return 0;
0416 }
0417
0418 static int __maybe_unused mlxbf2_gpio_suspend(struct device *dev)
0419 {
0420     struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
0421
0422     gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
0423         YU_GPIO_MODE0);
0424     gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
0425         YU_GPIO_MODE1);
0426
0427     return 0;
0428 }
0429
0430 static int __maybe_unused mlxbf2_gpio_resume(struct device *dev)
0431 {
0432     struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
0433
0434     writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
0435         YU_GPIO_MODE0);
0436     writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
0437         YU_GPIO_MODE1);
0438
0439     return 0;
0440 }
0441 static SIMPLE_DEV_PM_OPS(mlxbf2_pm_ops, mlxbf2_gpio_suspend, mlxbf2_gpio_resume);
0442
0443 static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
0444     { "MLNXBF22", 0 },
0445     {},
0446 };
0447 MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
0448
0449 static struct platform_driver mlxbf2_gpio_driver = {
0450     .driver = {
0451         .name = "mlxbf2_gpio",
0452         .acpi_match_table = mlxbf2_gpio_acpi_match,
0453         .pm = &mlxbf2_pm_ops,
0454     },
0455     .probe    = mlxbf2_gpio_probe,
0456 };
0457
0458 module_platform_driver(mlxbf2_gpio_driver);
0459
0460 MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
0461 MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
0462 MODULE_LICENSE("GPL v2");