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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
0004  */
0005 #include <linux/module.h>
0006 #include <linux/kernel.h>
0007 #include <linux/slab.h>
0008 #include <linux/pci.h>
0009 #include <linux/gpio/driver.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/irq.h>
0012 
0013 #define IOH_EDGE_FALLING    0
0014 #define IOH_EDGE_RISING     BIT(0)
0015 #define IOH_LEVEL_L     BIT(1)
0016 #define IOH_LEVEL_H     (BIT(0) | BIT(1))
0017 #define IOH_EDGE_BOTH       BIT(2)
0018 #define IOH_IM_MASK     (BIT(0) | BIT(1) | BIT(2))
0019 
0020 #define IOH_IRQ_BASE        0
0021 
0022 struct ioh_reg_comn {
0023     u32 ien;
0024     u32 istatus;
0025     u32 idisp;
0026     u32 iclr;
0027     u32 imask;
0028     u32 imaskclr;
0029     u32 po;
0030     u32 pi;
0031     u32 pm;
0032     u32 im_0;
0033     u32 im_1;
0034     u32 reserved;
0035 };
0036 
0037 struct ioh_regs {
0038     struct ioh_reg_comn regs[8];
0039     u32 reserve1[16];
0040     u32 ioh_sel_reg[4];
0041     u32 reserve2[11];
0042     u32 srst;
0043 };
0044 
0045 /**
0046  * struct ioh_gpio_reg_data - The register store data.
0047  * @ien_reg:    To store contents of interrupt enable register.
0048  * @imask_reg:  To store contents of interrupt mask regist
0049  * @po_reg: To store contents of PO register.
0050  * @pm_reg: To store contents of PM register.
0051  * @im0_reg:    To store contents of interrupt mode regist0
0052  * @im1_reg:    To store contents of interrupt mode regist1
0053  * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
0054  */
0055 struct ioh_gpio_reg_data {
0056     u32 ien_reg;
0057     u32 imask_reg;
0058     u32 po_reg;
0059     u32 pm_reg;
0060     u32 im0_reg;
0061     u32 im1_reg;
0062     u32 use_sel_reg;
0063 };
0064 
0065 /**
0066  * struct ioh_gpio - GPIO private data structure.
0067  * @base:           PCI base address of Memory mapped I/O register.
0068  * @reg:            Memory mapped IOH GPIO register list.
0069  * @dev:            Pointer to device structure.
0070  * @gpio:           Data for GPIO infrastructure.
0071  * @ioh_gpio_reg:       Memory mapped Register data is saved here
0072  *              when suspend.
0073  * @gpio_use_sel:       Save GPIO_USE_SEL1~4 register for PM
0074  * @ch:             Indicate GPIO channel
0075  * @irq_base:       Save base of IRQ number for interrupt
0076  * @spinlock:       Used for register access protection
0077  */
0078 struct ioh_gpio {
0079     void __iomem *base;
0080     struct ioh_regs __iomem *reg;
0081     struct device *dev;
0082     struct gpio_chip gpio;
0083     struct ioh_gpio_reg_data ioh_gpio_reg;
0084     u32 gpio_use_sel;
0085     int ch;
0086     int irq_base;
0087     spinlock_t spinlock;
0088 };
0089 
0090 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
0091 
0092 static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
0093 {
0094     u32 reg_val;
0095     struct ioh_gpio *chip = gpiochip_get_data(gpio);
0096     unsigned long flags;
0097 
0098     spin_lock_irqsave(&chip->spinlock, flags);
0099     reg_val = ioread32(&chip->reg->regs[chip->ch].po);
0100     if (val)
0101         reg_val |= BIT(nr);
0102     else
0103         reg_val &= ~BIT(nr);
0104 
0105     iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
0106     spin_unlock_irqrestore(&chip->spinlock, flags);
0107 }
0108 
0109 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
0110 {
0111     struct ioh_gpio *chip = gpiochip_get_data(gpio);
0112 
0113     return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr));
0114 }
0115 
0116 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
0117                      int val)
0118 {
0119     struct ioh_gpio *chip = gpiochip_get_data(gpio);
0120     u32 pm;
0121     u32 reg_val;
0122     unsigned long flags;
0123 
0124     spin_lock_irqsave(&chip->spinlock, flags);
0125     pm = ioread32(&chip->reg->regs[chip->ch].pm);
0126     pm &= BIT(num_ports[chip->ch]) - 1;
0127     pm |= BIT(nr);
0128     iowrite32(pm, &chip->reg->regs[chip->ch].pm);
0129 
0130     reg_val = ioread32(&chip->reg->regs[chip->ch].po);
0131     if (val)
0132         reg_val |= BIT(nr);
0133     else
0134         reg_val &= ~BIT(nr);
0135     iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
0136 
0137     spin_unlock_irqrestore(&chip->spinlock, flags);
0138 
0139     return 0;
0140 }
0141 
0142 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
0143 {
0144     struct ioh_gpio *chip = gpiochip_get_data(gpio);
0145     u32 pm;
0146     unsigned long flags;
0147 
0148     spin_lock_irqsave(&chip->spinlock, flags);
0149     pm = ioread32(&chip->reg->regs[chip->ch].pm);
0150     pm &= BIT(num_ports[chip->ch]) - 1;
0151     pm &= ~BIT(nr);
0152     iowrite32(pm, &chip->reg->regs[chip->ch].pm);
0153     spin_unlock_irqrestore(&chip->spinlock, flags);
0154 
0155     return 0;
0156 }
0157 
0158 /*
0159  * Save register configuration and disable interrupts.
0160  */
0161 static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
0162 {
0163     int i;
0164 
0165     for (i = 0; i < 8; i ++, chip++) {
0166         chip->ioh_gpio_reg.po_reg =
0167                     ioread32(&chip->reg->regs[chip->ch].po);
0168         chip->ioh_gpio_reg.pm_reg =
0169                     ioread32(&chip->reg->regs[chip->ch].pm);
0170         chip->ioh_gpio_reg.ien_reg =
0171                        ioread32(&chip->reg->regs[chip->ch].ien);
0172         chip->ioh_gpio_reg.imask_reg =
0173                      ioread32(&chip->reg->regs[chip->ch].imask);
0174         chip->ioh_gpio_reg.im0_reg =
0175                       ioread32(&chip->reg->regs[chip->ch].im_0);
0176         chip->ioh_gpio_reg.im1_reg =
0177                       ioread32(&chip->reg->regs[chip->ch].im_1);
0178         if (i < 4)
0179             chip->ioh_gpio_reg.use_sel_reg =
0180                        ioread32(&chip->reg->ioh_sel_reg[i]);
0181     }
0182 }
0183 
0184 /*
0185  * This function restores the register configuration of the GPIO device.
0186  */
0187 static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
0188 {
0189     int i;
0190 
0191     for (i = 0; i < 8; i ++, chip++) {
0192         iowrite32(chip->ioh_gpio_reg.po_reg,
0193               &chip->reg->regs[chip->ch].po);
0194         iowrite32(chip->ioh_gpio_reg.pm_reg,
0195               &chip->reg->regs[chip->ch].pm);
0196         iowrite32(chip->ioh_gpio_reg.ien_reg,
0197               &chip->reg->regs[chip->ch].ien);
0198         iowrite32(chip->ioh_gpio_reg.imask_reg,
0199               &chip->reg->regs[chip->ch].imask);
0200         iowrite32(chip->ioh_gpio_reg.im0_reg,
0201               &chip->reg->regs[chip->ch].im_0);
0202         iowrite32(chip->ioh_gpio_reg.im1_reg,
0203               &chip->reg->regs[chip->ch].im_1);
0204         if (i < 4)
0205             iowrite32(chip->ioh_gpio_reg.use_sel_reg,
0206                   &chip->reg->ioh_sel_reg[i]);
0207     }
0208 }
0209 
0210 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
0211 {
0212     struct ioh_gpio *chip = gpiochip_get_data(gpio);
0213     return chip->irq_base + offset;
0214 }
0215 
0216 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
0217 {
0218     struct gpio_chip *gpio = &chip->gpio;
0219 
0220     gpio->label = dev_name(chip->dev);
0221     gpio->owner = THIS_MODULE;
0222     gpio->direction_input = ioh_gpio_direction_input;
0223     gpio->get = ioh_gpio_get;
0224     gpio->direction_output = ioh_gpio_direction_output;
0225     gpio->set = ioh_gpio_set;
0226     gpio->dbg_show = NULL;
0227     gpio->base = -1;
0228     gpio->ngpio = num_port;
0229     gpio->can_sleep = false;
0230     gpio->to_irq = ioh_gpio_to_irq;
0231 }
0232 
0233 static int ioh_irq_type(struct irq_data *d, unsigned int type)
0234 {
0235     u32 im;
0236     void __iomem *im_reg;
0237     u32 ien;
0238     u32 im_pos;
0239     int ch;
0240     unsigned long flags;
0241     u32 val;
0242     int irq = d->irq;
0243     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0244     struct ioh_gpio *chip = gc->private;
0245 
0246     ch = irq - chip->irq_base;
0247     if (irq <= chip->irq_base + 7) {
0248         im_reg = &chip->reg->regs[chip->ch].im_0;
0249         im_pos = ch;
0250     } else {
0251         im_reg = &chip->reg->regs[chip->ch].im_1;
0252         im_pos = ch - 8;
0253     }
0254     dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
0255         __func__, irq, type, ch, im_pos, type);
0256 
0257     spin_lock_irqsave(&chip->spinlock, flags);
0258 
0259     switch (type) {
0260     case IRQ_TYPE_EDGE_RISING:
0261         val = IOH_EDGE_RISING;
0262         break;
0263     case IRQ_TYPE_EDGE_FALLING:
0264         val = IOH_EDGE_FALLING;
0265         break;
0266     case IRQ_TYPE_EDGE_BOTH:
0267         val = IOH_EDGE_BOTH;
0268         break;
0269     case IRQ_TYPE_LEVEL_HIGH:
0270         val = IOH_LEVEL_H;
0271         break;
0272     case IRQ_TYPE_LEVEL_LOW:
0273         val = IOH_LEVEL_L;
0274         break;
0275     case IRQ_TYPE_PROBE:
0276         goto end;
0277     default:
0278         dev_warn(chip->dev, "%s: unknown type(%dd)",
0279             __func__, type);
0280         goto end;
0281     }
0282 
0283     /* Set interrupt mode */
0284     im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
0285     iowrite32(im | (val << (im_pos * 4)), im_reg);
0286 
0287     /* iclr */
0288     iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
0289 
0290     /* IMASKCLR */
0291     iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
0292 
0293     /* Enable interrupt */
0294     ien = ioread32(&chip->reg->regs[chip->ch].ien);
0295     iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
0296 end:
0297     spin_unlock_irqrestore(&chip->spinlock, flags);
0298 
0299     return 0;
0300 }
0301 
0302 static void ioh_irq_unmask(struct irq_data *d)
0303 {
0304     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0305     struct ioh_gpio *chip = gc->private;
0306 
0307     iowrite32(BIT(d->irq - chip->irq_base),
0308           &chip->reg->regs[chip->ch].imaskclr);
0309 }
0310 
0311 static void ioh_irq_mask(struct irq_data *d)
0312 {
0313     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0314     struct ioh_gpio *chip = gc->private;
0315 
0316     iowrite32(BIT(d->irq - chip->irq_base),
0317           &chip->reg->regs[chip->ch].imask);
0318 }
0319 
0320 static void ioh_irq_disable(struct irq_data *d)
0321 {
0322     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0323     struct ioh_gpio *chip = gc->private;
0324     unsigned long flags;
0325     u32 ien;
0326 
0327     spin_lock_irqsave(&chip->spinlock, flags);
0328     ien = ioread32(&chip->reg->regs[chip->ch].ien);
0329     ien &= ~BIT(d->irq - chip->irq_base);
0330     iowrite32(ien, &chip->reg->regs[chip->ch].ien);
0331     spin_unlock_irqrestore(&chip->spinlock, flags);
0332 }
0333 
0334 static void ioh_irq_enable(struct irq_data *d)
0335 {
0336     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0337     struct ioh_gpio *chip = gc->private;
0338     unsigned long flags;
0339     u32 ien;
0340 
0341     spin_lock_irqsave(&chip->spinlock, flags);
0342     ien = ioread32(&chip->reg->regs[chip->ch].ien);
0343     ien |= BIT(d->irq - chip->irq_base);
0344     iowrite32(ien, &chip->reg->regs[chip->ch].ien);
0345     spin_unlock_irqrestore(&chip->spinlock, flags);
0346 }
0347 
0348 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
0349 {
0350     struct ioh_gpio *chip = dev_id;
0351     u32 reg_val;
0352     int i, j;
0353     int ret = IRQ_NONE;
0354 
0355     for (i = 0; i < 8; i++, chip++) {
0356         reg_val = ioread32(&chip->reg->regs[i].istatus);
0357         for (j = 0; j < num_ports[i]; j++) {
0358             if (reg_val & BIT(j)) {
0359                 dev_dbg(chip->dev,
0360                     "%s:[%d]:irq=%d status=0x%x\n",
0361                     __func__, j, irq, reg_val);
0362                 iowrite32(BIT(j),
0363                       &chip->reg->regs[chip->ch].iclr);
0364                 generic_handle_irq(chip->irq_base + j);
0365                 ret = IRQ_HANDLED;
0366             }
0367         }
0368     }
0369     return ret;
0370 }
0371 
0372 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
0373                        unsigned int irq_start,
0374                        unsigned int num)
0375 {
0376     struct irq_chip_generic *gc;
0377     struct irq_chip_type *ct;
0378     int rv;
0379 
0380     gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
0381                      chip->base, handle_simple_irq);
0382     if (!gc)
0383         return -ENOMEM;
0384 
0385     gc->private = chip;
0386     ct = gc->chip_types;
0387 
0388     ct->chip.irq_mask = ioh_irq_mask;
0389     ct->chip.irq_unmask = ioh_irq_unmask;
0390     ct->chip.irq_set_type = ioh_irq_type;
0391     ct->chip.irq_disable = ioh_irq_disable;
0392     ct->chip.irq_enable = ioh_irq_enable;
0393 
0394     rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
0395                      IRQ_GC_INIT_MASK_CACHE,
0396                      IRQ_NOREQUEST | IRQ_NOPROBE, 0);
0397 
0398     return rv;
0399 }
0400 
0401 static int ioh_gpio_probe(struct pci_dev *pdev,
0402                     const struct pci_device_id *id)
0403 {
0404     struct device *dev = &pdev->dev;
0405     int ret;
0406     int i, j;
0407     struct ioh_gpio *chip;
0408     void __iomem *base;
0409     void *chip_save;
0410     int irq_base;
0411 
0412     ret = pcim_enable_device(pdev);
0413     if (ret) {
0414         dev_err(dev, "%s : pcim_enable_device failed", __func__);
0415         return ret;
0416     }
0417 
0418     ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
0419     if (ret) {
0420         dev_err(dev, "pcim_iomap_regions failed-%d", ret);
0421         return ret;
0422     }
0423 
0424     base = pcim_iomap_table(pdev)[1];
0425     if (!base) {
0426         dev_err(dev, "%s : pcim_iomap_table failed", __func__);
0427         return -ENOMEM;
0428     }
0429 
0430     chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL);
0431     if (chip_save == NULL) {
0432         return -ENOMEM;
0433     }
0434 
0435     chip = chip_save;
0436     for (i = 0; i < 8; i++, chip++) {
0437         chip->dev = dev;
0438         chip->base = base;
0439         chip->reg = chip->base;
0440         chip->ch = i;
0441         spin_lock_init(&chip->spinlock);
0442         ioh_gpio_setup(chip, num_ports[i]);
0443         ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
0444         if (ret) {
0445             dev_err(dev, "IOH gpio: Failed to register GPIO\n");
0446             return ret;
0447         }
0448     }
0449 
0450     chip = chip_save;
0451     for (j = 0; j < 8; j++, chip++) {
0452         irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE,
0453                         num_ports[j], NUMA_NO_NODE);
0454         if (irq_base < 0) {
0455             dev_warn(dev,
0456                 "ml_ioh_gpio: Failed to get IRQ base num\n");
0457             return irq_base;
0458         }
0459         chip->irq_base = irq_base;
0460 
0461         ret = ioh_gpio_alloc_generic_chip(chip,
0462                           irq_base, num_ports[j]);
0463         if (ret)
0464             return ret;
0465     }
0466 
0467     chip = chip_save;
0468     ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler,
0469                    IRQF_SHARED, KBUILD_MODNAME, chip);
0470     if (ret != 0) {
0471         dev_err(dev, "%s request_irq failed\n", __func__);
0472         return ret;
0473     }
0474 
0475     pci_set_drvdata(pdev, chip);
0476 
0477     return 0;
0478 }
0479 
0480 static int __maybe_unused ioh_gpio_suspend(struct device *dev)
0481 {
0482     struct ioh_gpio *chip = dev_get_drvdata(dev);
0483     unsigned long flags;
0484 
0485     spin_lock_irqsave(&chip->spinlock, flags);
0486     ioh_gpio_save_reg_conf(chip);
0487     spin_unlock_irqrestore(&chip->spinlock, flags);
0488 
0489     return 0;
0490 }
0491 
0492 static int __maybe_unused ioh_gpio_resume(struct device *dev)
0493 {
0494     struct ioh_gpio *chip = dev_get_drvdata(dev);
0495     unsigned long flags;
0496 
0497     spin_lock_irqsave(&chip->spinlock, flags);
0498     iowrite32(0x01, &chip->reg->srst);
0499     iowrite32(0x00, &chip->reg->srst);
0500     ioh_gpio_restore_reg_conf(chip);
0501     spin_unlock_irqrestore(&chip->spinlock, flags);
0502 
0503     return 0;
0504 }
0505 
0506 static SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume);
0507 
0508 static const struct pci_device_id ioh_gpio_pcidev_id[] = {
0509     { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
0510     { 0, }
0511 };
0512 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
0513 
0514 static struct pci_driver ioh_gpio_driver = {
0515     .name = "ml_ioh_gpio",
0516     .id_table = ioh_gpio_pcidev_id,
0517     .probe = ioh_gpio_probe,
0518     .driver = {
0519         .pm = &ioh_gpio_pm_ops,
0520     },
0521 };
0522 
0523 module_pci_driver(ioh_gpio_driver);
0524 
0525 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
0526 MODULE_LICENSE("GPL");
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