drivers/gpio/gpio-merrifield.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Merrifield SoC GPIO driver
0004  *
0005  * Copyright (c) 2016 Intel Corporation.
0006  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0007  */
0008
0009 #include <linux/acpi.h>
0010 #include <linux/bitops.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/module.h>
0015 #include <linux/pci.h>
0016 #include <linux/pinctrl/consumer.h>
0017
0018 #define GCCR        0x000   /* controller configuration */
0019 #define GPLR        0x004   /* pin level r/o */
0020 #define GPDR        0x01c   /* pin direction */
0021 #define GPSR        0x034   /* pin set w/o */
0022 #define GPCR        0x04c   /* pin clear w/o */
0023 #define GRER        0x064   /* rising edge detect */
0024 #define GFER        0x07c   /* falling edge detect */
0025 #define GFBR        0x094   /* glitch filter bypass */
0026 #define GIMR        0x0ac   /* interrupt mask */
0027 #define GISR        0x0c4   /* interrupt source */
0028 #define GITR        0x300   /* input type */
0029 #define GLPR        0x318   /* level input polarity */
0030 #define GWMR        0x400   /* wake mask */
0031 #define GWSR        0x418   /* wake source */
0032 #define GSIR        0xc00   /* secure input */
0033
0034 /* Intel Merrifield has 192 GPIO pins */
0035 #define MRFLD_NGPIO 192
0036
0037 struct mrfld_gpio_pinrange {
0038     unsigned int gpio_base;
0039     unsigned int pin_base;
0040     unsigned int npins;
0041 };
0042
0043 #define GPIO_PINRANGE(gstart, gend, pstart)     \
0044     {                       \
0045         .gpio_base = (gstart),          \
0046         .pin_base = (pstart),           \
0047         .npins = (gend) - (gstart) + 1,     \
0048     }
0049
0050 struct mrfld_gpio {
0051     struct gpio_chip    chip;
0052     void __iomem        *reg_base;
0053     raw_spinlock_t      lock;
0054     struct device       *dev;
0055 };
0056
0057 static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
0058     GPIO_PINRANGE(0, 11, 146),
0059     GPIO_PINRANGE(12, 13, 144),
0060     GPIO_PINRANGE(14, 15, 35),
0061     GPIO_PINRANGE(16, 16, 164),
0062     GPIO_PINRANGE(17, 18, 105),
0063     GPIO_PINRANGE(19, 22, 101),
0064     GPIO_PINRANGE(23, 30, 107),
0065     GPIO_PINRANGE(32, 43, 67),
0066     GPIO_PINRANGE(44, 63, 195),
0067     GPIO_PINRANGE(64, 67, 140),
0068     GPIO_PINRANGE(68, 69, 165),
0069     GPIO_PINRANGE(70, 71, 65),
0070     GPIO_PINRANGE(72, 76, 228),
0071     GPIO_PINRANGE(77, 86, 37),
0072     GPIO_PINRANGE(87, 87, 48),
0073     GPIO_PINRANGE(88, 88, 47),
0074     GPIO_PINRANGE(89, 96, 49),
0075     GPIO_PINRANGE(97, 97, 34),
0076     GPIO_PINRANGE(102, 119, 83),
0077     GPIO_PINRANGE(120, 123, 79),
0078     GPIO_PINRANGE(124, 135, 115),
0079     GPIO_PINRANGE(137, 142, 158),
0080     GPIO_PINRANGE(154, 163, 24),
0081     GPIO_PINRANGE(164, 176, 215),
0082     GPIO_PINRANGE(177, 189, 127),
0083     GPIO_PINRANGE(190, 191, 178),
0084 };
0085
0086 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset,
0087                   unsigned int reg_type_offset)
0088 {
0089     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0090     u8 reg = offset / 32;
0091
0092     return priv->reg_base + reg_type_offset + reg * 4;
0093 }
0094
0095 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset)
0096 {
0097     void __iomem *gplr = gpio_reg(chip, offset, GPLR);
0098
0099     return !!(readl(gplr) & BIT(offset % 32));
0100 }
0101
0102 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset,
0103                int value)
0104 {
0105     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0106     void __iomem *gpsr, *gpcr;
0107     unsigned long flags;
0108
0109     raw_spin_lock_irqsave(&priv->lock, flags);
0110
0111     if (value) {
0112         gpsr = gpio_reg(chip, offset, GPSR);
0113         writel(BIT(offset % 32), gpsr);
0114     } else {
0115         gpcr = gpio_reg(chip, offset, GPCR);
0116         writel(BIT(offset % 32), gpcr);
0117     }
0118
0119     raw_spin_unlock_irqrestore(&priv->lock, flags);
0120 }
0121
0122 static int mrfld_gpio_direction_input(struct gpio_chip *chip,
0123                       unsigned int offset)
0124 {
0125     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0126     void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
0127     unsigned long flags;
0128     u32 value;
0129
0130     raw_spin_lock_irqsave(&priv->lock, flags);
0131
0132     value = readl(gpdr);
0133     value &= ~BIT(offset % 32);
0134     writel(value, gpdr);
0135
0136     raw_spin_unlock_irqrestore(&priv->lock, flags);
0137
0138     return 0;
0139 }
0140
0141 static int mrfld_gpio_direction_output(struct gpio_chip *chip,
0142                        unsigned int offset, int value)
0143 {
0144     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0145     void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
0146     unsigned long flags;
0147
0148     mrfld_gpio_set(chip, offset, value);
0149
0150     raw_spin_lock_irqsave(&priv->lock, flags);
0151
0152     value = readl(gpdr);
0153     value |= BIT(offset % 32);
0154     writel(value, gpdr);
0155
0156     raw_spin_unlock_irqrestore(&priv->lock, flags);
0157
0158     return 0;
0159 }
0160
0161 static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0162 {
0163     void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
0164
0165     if (readl(gpdr) & BIT(offset % 32))
0166         return GPIO_LINE_DIRECTION_OUT;
0167
0168     return GPIO_LINE_DIRECTION_IN;
0169 }
0170
0171 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
0172                    unsigned int debounce)
0173 {
0174     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0175     void __iomem *gfbr = gpio_reg(chip, offset, GFBR);
0176     unsigned long flags;
0177     u32 value;
0178
0179     raw_spin_lock_irqsave(&priv->lock, flags);
0180
0181     if (debounce)
0182         value = readl(gfbr) & ~BIT(offset % 32);
0183     else
0184         value = readl(gfbr) | BIT(offset % 32);
0185     writel(value, gfbr);
0186
0187     raw_spin_unlock_irqrestore(&priv->lock, flags);
0188
0189     return 0;
0190 }
0191
0192 static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
0193                  unsigned long config)
0194 {
0195     u32 debounce;
0196
0197     if ((pinconf_to_config_param(config) == PIN_CONFIG_BIAS_DISABLE) ||
0198         (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_UP) ||
0199         (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_DOWN))
0200         return gpiochip_generic_config(chip, offset, config);
0201
0202     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0203         return -ENOTSUPP;
0204
0205     debounce = pinconf_to_config_argument(config);
0206     return mrfld_gpio_set_debounce(chip, offset, debounce);
0207 }
0208
0209 static void mrfld_irq_ack(struct irq_data *d)
0210 {
0211     struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
0212     u32 gpio = irqd_to_hwirq(d);
0213     void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR);
0214     unsigned long flags;
0215
0216     raw_spin_lock_irqsave(&priv->lock, flags);
0217
0218     writel(BIT(gpio % 32), gisr);
0219
0220     raw_spin_unlock_irqrestore(&priv->lock, flags);
0221 }
0222
0223 static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask)
0224 {
0225     void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR);
0226     unsigned long flags;
0227     u32 value;
0228
0229     raw_spin_lock_irqsave(&priv->lock, flags);
0230
0231     if (unmask)
0232         value = readl(gimr) | BIT(gpio % 32);
0233     else
0234         value = readl(gimr) & ~BIT(gpio % 32);
0235     writel(value, gimr);
0236
0237     raw_spin_unlock_irqrestore(&priv->lock, flags);
0238 }
0239
0240 static void mrfld_irq_mask(struct irq_data *d)
0241 {
0242     struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
0243     u32 gpio = irqd_to_hwirq(d);
0244
0245     mrfld_irq_unmask_mask(priv, gpio, false);
0246     gpiochip_disable_irq(&priv->chip, gpio);
0247 }
0248
0249 static void mrfld_irq_unmask(struct irq_data *d)
0250 {
0251     struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d);
0252     u32 gpio = irqd_to_hwirq(d);
0253
0254     gpiochip_enable_irq(&priv->chip, gpio);
0255     mrfld_irq_unmask_mask(priv, gpio, true);
0256 }
0257
0258 static int mrfld_irq_set_type(struct irq_data *d, unsigned int type)
0259 {
0260     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0261     struct mrfld_gpio *priv = gpiochip_get_data(gc);
0262     u32 gpio = irqd_to_hwirq(d);
0263     void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
0264     void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
0265     void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR);
0266     void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR);
0267     unsigned long flags;
0268     u32 value;
0269
0270     raw_spin_lock_irqsave(&priv->lock, flags);
0271
0272     if (type & IRQ_TYPE_EDGE_RISING)
0273         value = readl(grer) | BIT(gpio % 32);
0274     else
0275         value = readl(grer) & ~BIT(gpio % 32);
0276     writel(value, grer);
0277
0278     if (type & IRQ_TYPE_EDGE_FALLING)
0279         value = readl(gfer) | BIT(gpio % 32);
0280     else
0281         value = readl(gfer) & ~BIT(gpio % 32);
0282     writel(value, gfer);
0283
0284     /*
0285      * To prevent glitches from triggering an unintended level interrupt,
0286      * configure GLPR register first and then configure GITR.
0287      */
0288     if (type & IRQ_TYPE_LEVEL_LOW)
0289         value = readl(glpr) | BIT(gpio % 32);
0290     else
0291         value = readl(glpr) & ~BIT(gpio % 32);
0292     writel(value, glpr);
0293
0294     if (type & IRQ_TYPE_LEVEL_MASK) {
0295         value = readl(gitr) | BIT(gpio % 32);
0296         writel(value, gitr);
0297
0298         irq_set_handler_locked(d, handle_level_irq);
0299     } else if (type & IRQ_TYPE_EDGE_BOTH) {
0300         value = readl(gitr) & ~BIT(gpio % 32);
0301         writel(value, gitr);
0302
0303         irq_set_handler_locked(d, handle_edge_irq);
0304     }
0305
0306     raw_spin_unlock_irqrestore(&priv->lock, flags);
0307
0308     return 0;
0309 }
0310
0311 static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on)
0312 {
0313     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0314     struct mrfld_gpio *priv = gpiochip_get_data(gc);
0315     u32 gpio = irqd_to_hwirq(d);
0316     void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR);
0317     void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR);
0318     unsigned long flags;
0319     u32 value;
0320
0321     raw_spin_lock_irqsave(&priv->lock, flags);
0322
0323     /* Clear the existing wake status */
0324     writel(BIT(gpio % 32), gwsr);
0325
0326     if (on)
0327         value = readl(gwmr) | BIT(gpio % 32);
0328     else
0329         value = readl(gwmr) & ~BIT(gpio % 32);
0330     writel(value, gwmr);
0331
0332     raw_spin_unlock_irqrestore(&priv->lock, flags);
0333
0334     dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio);
0335     return 0;
0336 }
0337
0338 static const struct irq_chip mrfld_irqchip = {
0339     .name       = "gpio-merrifield",
0340     .irq_ack    = mrfld_irq_ack,
0341     .irq_mask   = mrfld_irq_mask,
0342     .irq_unmask = mrfld_irq_unmask,
0343     .irq_set_type   = mrfld_irq_set_type,
0344     .irq_set_wake   = mrfld_irq_set_wake,
0345     .flags      = IRQCHIP_IMMUTABLE,
0346     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0347 };
0348
0349 static void mrfld_irq_handler(struct irq_desc *desc)
0350 {
0351     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0352     struct mrfld_gpio *priv = gpiochip_get_data(gc);
0353     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0354     unsigned long base, gpio;
0355
0356     chained_irq_enter(irqchip, desc);
0357
0358     /* Check GPIO controller to check which pin triggered the interrupt */
0359     for (base = 0; base < priv->chip.ngpio; base += 32) {
0360         void __iomem *gisr = gpio_reg(&priv->chip, base, GISR);
0361         void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR);
0362         unsigned long pending, enabled;
0363
0364         pending = readl(gisr);
0365         enabled = readl(gimr);
0366
0367         /* Only interrupts that are enabled */
0368         pending &= enabled;
0369
0370         for_each_set_bit(gpio, &pending, 32)
0371             generic_handle_domain_irq(gc->irq.domain, base + gpio);
0372     }
0373
0374     chained_irq_exit(irqchip, desc);
0375 }
0376
0377 static int mrfld_irq_init_hw(struct gpio_chip *chip)
0378 {
0379     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0380     void __iomem *reg;
0381     unsigned int base;
0382
0383     for (base = 0; base < priv->chip.ngpio; base += 32) {
0384         /* Clear the rising-edge detect register */
0385         reg = gpio_reg(&priv->chip, base, GRER);
0386         writel(0, reg);
0387         /* Clear the falling-edge detect register */
0388         reg = gpio_reg(&priv->chip, base, GFER);
0389         writel(0, reg);
0390     }
0391
0392     return 0;
0393 }
0394
0395 static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
0396 {
0397     struct acpi_device *adev;
0398     const char *name;
0399
0400     adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
0401     if (adev) {
0402         name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
0403         acpi_dev_put(adev);
0404     } else {
0405         name = "pinctrl-merrifield";
0406     }
0407
0408     return name;
0409 }
0410
0411 static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
0412 {
0413     struct mrfld_gpio *priv = gpiochip_get_data(chip);
0414     const struct mrfld_gpio_pinrange *range;
0415     const char *pinctrl_dev_name;
0416     unsigned int i;
0417     int retval;
0418
0419     pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
0420     if (!pinctrl_dev_name)
0421         return -ENOMEM;
0422
0423     for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
0424         range = &mrfld_gpio_ranges[i];
0425         retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
0426                         range->gpio_base,
0427                         range->pin_base,
0428                         range->npins);
0429         if (retval) {
0430             dev_err(priv->dev, "failed to add GPIO pin range\n");
0431             return retval;
0432         }
0433     }
0434
0435     return 0;
0436 }
0437
0438 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0439 {
0440     struct gpio_irq_chip *girq;
0441     struct mrfld_gpio *priv;
0442     u32 gpio_base, irq_base;
0443     void __iomem *base;
0444     int retval;
0445
0446     retval = pcim_enable_device(pdev);
0447     if (retval)
0448         return retval;
0449
0450     retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev));
0451     if (retval) {
0452         dev_err(&pdev->dev, "I/O memory mapping error\n");
0453         return retval;
0454     }
0455
0456     base = pcim_iomap_table(pdev)[1];
0457
0458     irq_base = readl(base + 0 * sizeof(u32));
0459     gpio_base = readl(base + 1 * sizeof(u32));
0460
0461     /* Release the IO mapping, since we already get the info from BAR1 */
0462     pcim_iounmap_regions(pdev, BIT(1));
0463
0464     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0465     if (!priv)
0466         return -ENOMEM;
0467
0468     priv->dev = &pdev->dev;
0469     priv->reg_base = pcim_iomap_table(pdev)[0];
0470
0471     priv->chip.label = dev_name(&pdev->dev);
0472     priv->chip.parent = &pdev->dev;
0473     priv->chip.request = gpiochip_generic_request;
0474     priv->chip.free = gpiochip_generic_free;
0475     priv->chip.direction_input = mrfld_gpio_direction_input;
0476     priv->chip.direction_output = mrfld_gpio_direction_output;
0477     priv->chip.get = mrfld_gpio_get;
0478     priv->chip.set = mrfld_gpio_set;
0479     priv->chip.get_direction = mrfld_gpio_get_direction;
0480     priv->chip.set_config = mrfld_gpio_set_config;
0481     priv->chip.base = gpio_base;
0482     priv->chip.ngpio = MRFLD_NGPIO;
0483     priv->chip.can_sleep = false;
0484     priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
0485
0486     raw_spin_lock_init(&priv->lock);
0487
0488     retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
0489     if (retval < 0)
0490         return retval;
0491
0492     girq = &priv->chip.irq;
0493     gpio_irq_chip_set_chip(girq, &mrfld_irqchip);
0494     girq->init_hw = mrfld_irq_init_hw;
0495     girq->parent_handler = mrfld_irq_handler;
0496     girq->num_parents = 1;
0497     girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
0498                      sizeof(*girq->parents), GFP_KERNEL);
0499     if (!girq->parents)
0500         return -ENOMEM;
0501     girq->parents[0] = pci_irq_vector(pdev, 0);
0502     girq->first = irq_base;
0503     girq->default_type = IRQ_TYPE_NONE;
0504     girq->handler = handle_bad_irq;
0505
0506     retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
0507     if (retval) {
0508         dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
0509         return retval;
0510     }
0511
0512     pci_set_drvdata(pdev, priv);
0513     return 0;
0514 }
0515
0516 static const struct pci_device_id mrfld_gpio_ids[] = {
0517     { PCI_VDEVICE(INTEL, 0x1199) },
0518     { }
0519 };
0520 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids);
0521
0522 static struct pci_driver mrfld_gpio_driver = {
0523     .name       = "gpio-merrifield",
0524     .id_table   = mrfld_gpio_ids,
0525     .probe      = mrfld_gpio_probe,
0526 };
0527
0528 module_pci_driver(mrfld_gpio_driver);
0529
0530 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
0531 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver");
0532 MODULE_LICENSE("GPL v2");