drivers/gpio/gpio-max77620.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MAXIM MAX77620 GPIO driver
0004  *
0005  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
0006  */
0007
0008 #include <linux/gpio/driver.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/mfd/max77620.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014
0015 #define GPIO_REG_ADDR(offset) (MAX77620_REG_GPIO0 + offset)
0016
0017 struct max77620_gpio {
0018     struct gpio_chip    gpio_chip;
0019     struct regmap       *rmap;
0020     struct device       *dev;
0021     struct mutex        buslock; /* irq_bus_lock */
0022     unsigned int        irq_type[MAX77620_GPIO_NR];
0023     bool            irq_enabled[MAX77620_GPIO_NR];
0024 };
0025
0026 static irqreturn_t max77620_gpio_irqhandler(int irq, void *data)
0027 {
0028     struct max77620_gpio *gpio = data;
0029     unsigned int value, offset;
0030     unsigned long pending;
0031     int err;
0032
0033     err = regmap_read(gpio->rmap, MAX77620_REG_IRQ_LVL2_GPIO, &value);
0034     if (err < 0) {
0035         dev_err(gpio->dev, "REG_IRQ_LVL2_GPIO read failed: %d\n", err);
0036         return IRQ_NONE;
0037     }
0038
0039     pending = value;
0040
0041     for_each_set_bit(offset, &pending, MAX77620_GPIO_NR) {
0042         unsigned int virq;
0043
0044         virq = irq_find_mapping(gpio->gpio_chip.irq.domain, offset);
0045         handle_nested_irq(virq);
0046     }
0047
0048     return IRQ_HANDLED;
0049 }
0050
0051 static void max77620_gpio_irq_mask(struct irq_data *data)
0052 {
0053     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0054     struct max77620_gpio *gpio = gpiochip_get_data(chip);
0055
0056     gpio->irq_enabled[data->hwirq] = false;
0057     gpiochip_disable_irq(chip, data->hwirq);
0058 }
0059
0060 static void max77620_gpio_irq_unmask(struct irq_data *data)
0061 {
0062     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0063     struct max77620_gpio *gpio = gpiochip_get_data(chip);
0064
0065     gpiochip_enable_irq(chip, data->hwirq);
0066     gpio->irq_enabled[data->hwirq] = true;
0067 }
0068
0069 static int max77620_gpio_set_irq_type(struct irq_data *data, unsigned int type)
0070 {
0071     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0072     struct max77620_gpio *gpio = gpiochip_get_data(chip);
0073     unsigned int irq_type;
0074
0075     switch (type) {
0076     case IRQ_TYPE_EDGE_RISING:
0077         irq_type = MAX77620_CNFG_GPIO_INT_RISING;
0078         break;
0079
0080     case IRQ_TYPE_EDGE_FALLING:
0081         irq_type = MAX77620_CNFG_GPIO_INT_FALLING;
0082         break;
0083
0084     case IRQ_TYPE_EDGE_BOTH:
0085         irq_type = MAX77620_CNFG_GPIO_INT_RISING |
0086                MAX77620_CNFG_GPIO_INT_FALLING;
0087         break;
0088
0089     default:
0090         return -EINVAL;
0091     }
0092
0093     gpio->irq_type[data->hwirq] = irq_type;
0094
0095     return 0;
0096 }
0097
0098 static void max77620_gpio_bus_lock(struct irq_data *data)
0099 {
0100     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0101     struct max77620_gpio *gpio = gpiochip_get_data(chip);
0102
0103     mutex_lock(&gpio->buslock);
0104 }
0105
0106 static void max77620_gpio_bus_sync_unlock(struct irq_data *data)
0107 {
0108     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0109     struct max77620_gpio *gpio = gpiochip_get_data(chip);
0110     unsigned int value, offset = data->hwirq;
0111     int err;
0112
0113     value = gpio->irq_enabled[offset] ? gpio->irq_type[offset] : 0;
0114
0115     err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(offset),
0116                  MAX77620_CNFG_GPIO_INT_MASK, value);
0117     if (err < 0)
0118         dev_err(chip->parent, "failed to update interrupt mask: %d\n",
0119             err);
0120
0121     mutex_unlock(&gpio->buslock);
0122 }
0123
0124 static const struct irq_chip max77620_gpio_irqchip = {
0125     .name       = "max77620-gpio",
0126     .irq_mask   = max77620_gpio_irq_mask,
0127     .irq_unmask = max77620_gpio_irq_unmask,
0128     .irq_set_type   = max77620_gpio_set_irq_type,
0129     .irq_bus_lock   = max77620_gpio_bus_lock,
0130     .irq_bus_sync_unlock = max77620_gpio_bus_sync_unlock,
0131     .flags      = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
0132     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0133 };
0134
0135 static int max77620_gpio_dir_input(struct gpio_chip *gc, unsigned int offset)
0136 {
0137     struct max77620_gpio *mgpio = gpiochip_get_data(gc);
0138     int ret;
0139
0140     ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0141                  MAX77620_CNFG_GPIO_DIR_MASK,
0142                  MAX77620_CNFG_GPIO_DIR_INPUT);
0143     if (ret < 0)
0144         dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
0145
0146     return ret;
0147 }
0148
0149 static int max77620_gpio_get(struct gpio_chip *gc, unsigned int offset)
0150 {
0151     struct max77620_gpio *mgpio = gpiochip_get_data(gc);
0152     unsigned int val;
0153     int ret;
0154
0155     ret = regmap_read(mgpio->rmap, GPIO_REG_ADDR(offset), &val);
0156     if (ret < 0) {
0157         dev_err(mgpio->dev, "CNFG_GPIOx read failed: %d\n", ret);
0158         return ret;
0159     }
0160
0161     if  (val & MAX77620_CNFG_GPIO_DIR_MASK)
0162         return !!(val & MAX77620_CNFG_GPIO_INPUT_VAL_MASK);
0163     else
0164         return !!(val & MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK);
0165 }
0166
0167 static int max77620_gpio_dir_output(struct gpio_chip *gc, unsigned int offset,
0168                     int value)
0169 {
0170     struct max77620_gpio *mgpio = gpiochip_get_data(gc);
0171     u8 val;
0172     int ret;
0173
0174     val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
0175                 MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
0176
0177     ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0178                  MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
0179     if (ret < 0) {
0180         dev_err(mgpio->dev, "CNFG_GPIOx val update failed: %d\n", ret);
0181         return ret;
0182     }
0183
0184     ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0185                  MAX77620_CNFG_GPIO_DIR_MASK,
0186                  MAX77620_CNFG_GPIO_DIR_OUTPUT);
0187     if (ret < 0)
0188         dev_err(mgpio->dev, "CNFG_GPIOx dir update failed: %d\n", ret);
0189
0190     return ret;
0191 }
0192
0193 static int max77620_gpio_set_debounce(struct max77620_gpio *mgpio,
0194                       unsigned int offset,
0195                       unsigned int debounce)
0196 {
0197     u8 val;
0198     int ret;
0199
0200     switch (debounce) {
0201     case 0:
0202         val = MAX77620_CNFG_GPIO_DBNC_None;
0203         break;
0204     case 1 ... 8000:
0205         val = MAX77620_CNFG_GPIO_DBNC_8ms;
0206         break;
0207     case 8001 ... 16000:
0208         val = MAX77620_CNFG_GPIO_DBNC_16ms;
0209         break;
0210     case 16001 ... 32000:
0211         val = MAX77620_CNFG_GPIO_DBNC_32ms;
0212         break;
0213     default:
0214         dev_err(mgpio->dev, "Illegal value %u\n", debounce);
0215         return -EINVAL;
0216     }
0217
0218     ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0219                  MAX77620_CNFG_GPIO_DBNC_MASK, val);
0220     if (ret < 0)
0221         dev_err(mgpio->dev, "CNFG_GPIOx_DBNC update failed: %d\n", ret);
0222
0223     return ret;
0224 }
0225
0226 static void max77620_gpio_set(struct gpio_chip *gc, unsigned int offset,
0227                   int value)
0228 {
0229     struct max77620_gpio *mgpio = gpiochip_get_data(gc);
0230     u8 val;
0231     int ret;
0232
0233     val = (value) ? MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH :
0234                 MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW;
0235
0236     ret = regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0237                  MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK, val);
0238     if (ret < 0)
0239         dev_err(mgpio->dev, "CNFG_GPIO_OUT update failed: %d\n", ret);
0240 }
0241
0242 static int max77620_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
0243                     unsigned long config)
0244 {
0245     struct max77620_gpio *mgpio = gpiochip_get_data(gc);
0246
0247     switch (pinconf_to_config_param(config)) {
0248     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0249         return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0250                       MAX77620_CNFG_GPIO_DRV_MASK,
0251                       MAX77620_CNFG_GPIO_DRV_OPENDRAIN);
0252     case PIN_CONFIG_DRIVE_PUSH_PULL:
0253         return regmap_update_bits(mgpio->rmap, GPIO_REG_ADDR(offset),
0254                       MAX77620_CNFG_GPIO_DRV_MASK,
0255                       MAX77620_CNFG_GPIO_DRV_PUSHPULL);
0256     case PIN_CONFIG_INPUT_DEBOUNCE:
0257         return max77620_gpio_set_debounce(mgpio, offset,
0258             pinconf_to_config_argument(config));
0259     default:
0260         break;
0261     }
0262
0263     return -ENOTSUPP;
0264 }
0265
0266 static int max77620_gpio_irq_init_hw(struct gpio_chip *gc)
0267 {
0268     struct max77620_gpio *gpio = gpiochip_get_data(gc);
0269     unsigned int i;
0270     int err;
0271
0272     /*
0273      * GPIO interrupts may be left ON after bootloader, hence let's
0274      * pre-initialize hardware to the expected state by disabling all
0275      * the interrupts.
0276      */
0277     for (i = 0; i < MAX77620_GPIO_NR; i++) {
0278         err = regmap_update_bits(gpio->rmap, GPIO_REG_ADDR(i),
0279                      MAX77620_CNFG_GPIO_INT_MASK, 0);
0280         if (err < 0) {
0281             dev_err(gpio->dev,
0282                 "failed to disable interrupt: %d\n", err);
0283             return err;
0284         }
0285     }
0286
0287     return 0;
0288 }
0289
0290 static int max77620_gpio_probe(struct platform_device *pdev)
0291 {
0292     struct max77620_chip *chip =  dev_get_drvdata(pdev->dev.parent);
0293     struct max77620_gpio *mgpio;
0294     struct gpio_irq_chip *girq;
0295     unsigned int gpio_irq;
0296     int ret;
0297
0298     ret = platform_get_irq(pdev, 0);
0299     if (ret < 0)
0300         return ret;
0301
0302     gpio_irq = ret;
0303
0304     mgpio = devm_kzalloc(&pdev->dev, sizeof(*mgpio), GFP_KERNEL);
0305     if (!mgpio)
0306         return -ENOMEM;
0307
0308     mutex_init(&mgpio->buslock);
0309     mgpio->rmap = chip->rmap;
0310     mgpio->dev = &pdev->dev;
0311
0312     mgpio->gpio_chip.label = pdev->name;
0313     mgpio->gpio_chip.parent = pdev->dev.parent;
0314     mgpio->gpio_chip.direction_input = max77620_gpio_dir_input;
0315     mgpio->gpio_chip.get = max77620_gpio_get;
0316     mgpio->gpio_chip.direction_output = max77620_gpio_dir_output;
0317     mgpio->gpio_chip.set = max77620_gpio_set;
0318     mgpio->gpio_chip.set_config = max77620_gpio_set_config;
0319     mgpio->gpio_chip.ngpio = MAX77620_GPIO_NR;
0320     mgpio->gpio_chip.can_sleep = 1;
0321     mgpio->gpio_chip.base = -1;
0322
0323     girq = &mgpio->gpio_chip.irq;
0324     gpio_irq_chip_set_chip(girq, &max77620_gpio_irqchip);
0325     /* This will let us handle the parent IRQ in the driver */
0326     girq->parent_handler = NULL;
0327     girq->num_parents = 0;
0328     girq->parents = NULL;
0329     girq->default_type = IRQ_TYPE_NONE;
0330     girq->handler = handle_edge_irq;
0331     girq->init_hw = max77620_gpio_irq_init_hw;
0332     girq->threaded = true;
0333
0334     platform_set_drvdata(pdev, mgpio);
0335
0336     ret = devm_gpiochip_add_data(&pdev->dev, &mgpio->gpio_chip, mgpio);
0337     if (ret < 0) {
0338         dev_err(&pdev->dev, "gpio_init: Failed to add max77620_gpio\n");
0339         return ret;
0340     }
0341
0342     ret = devm_request_threaded_irq(&pdev->dev, gpio_irq, NULL,
0343                     max77620_gpio_irqhandler, IRQF_ONESHOT,
0344                     "max77620-gpio", mgpio);
0345     if (ret < 0) {
0346         dev_err(&pdev->dev, "failed to request IRQ: %d\n", ret);
0347         return ret;
0348     }
0349
0350     return 0;
0351 }
0352
0353 static const struct platform_device_id max77620_gpio_devtype[] = {
0354     { .name = "max77620-gpio", },
0355     { .name = "max20024-gpio", },
0356     {},
0357 };
0358 MODULE_DEVICE_TABLE(platform, max77620_gpio_devtype);
0359
0360 static struct platform_driver max77620_gpio_driver = {
0361     .driver.name    = "max77620-gpio",
0362     .probe      = max77620_gpio_probe,
0363     .id_table   = max77620_gpio_devtype,
0364 };
0365
0366 module_platform_driver(max77620_gpio_driver);
0367
0368 MODULE_DESCRIPTION("GPIO interface for MAX77620 and MAX20024 PMIC");
0369 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
0370 MODULE_AUTHOR("Chaitanya Bandi <bandik@nvidia.com>");
0371 MODULE_LICENSE("GPL v2");