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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * GPIO driver for LPC32xx SoC
0004  *
0005  * Author: Kevin Wells <kevin.wells@nxp.com>
0006  *
0007  * Copyright (C) 2010 NXP Semiconductors
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/errno.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/module.h>
0018 
0019 #define LPC32XX_GPIO_P3_INP_STATE       (0x000)
0020 #define LPC32XX_GPIO_P3_OUTP_SET        (0x004)
0021 #define LPC32XX_GPIO_P3_OUTP_CLR        (0x008)
0022 #define LPC32XX_GPIO_P3_OUTP_STATE      (0x00C)
0023 #define LPC32XX_GPIO_P2_DIR_SET         (0x010)
0024 #define LPC32XX_GPIO_P2_DIR_CLR         (0x014)
0025 #define LPC32XX_GPIO_P2_DIR_STATE       (0x018)
0026 #define LPC32XX_GPIO_P2_INP_STATE       (0x01C)
0027 #define LPC32XX_GPIO_P2_OUTP_SET        (0x020)
0028 #define LPC32XX_GPIO_P2_OUTP_CLR        (0x024)
0029 #define LPC32XX_GPIO_P2_MUX_SET         (0x028)
0030 #define LPC32XX_GPIO_P2_MUX_CLR         (0x02C)
0031 #define LPC32XX_GPIO_P2_MUX_STATE       (0x030)
0032 #define LPC32XX_GPIO_P0_INP_STATE       (0x040)
0033 #define LPC32XX_GPIO_P0_OUTP_SET        (0x044)
0034 #define LPC32XX_GPIO_P0_OUTP_CLR        (0x048)
0035 #define LPC32XX_GPIO_P0_OUTP_STATE      (0x04C)
0036 #define LPC32XX_GPIO_P0_DIR_SET         (0x050)
0037 #define LPC32XX_GPIO_P0_DIR_CLR         (0x054)
0038 #define LPC32XX_GPIO_P0_DIR_STATE       (0x058)
0039 #define LPC32XX_GPIO_P1_INP_STATE       (0x060)
0040 #define LPC32XX_GPIO_P1_OUTP_SET        (0x064)
0041 #define LPC32XX_GPIO_P1_OUTP_CLR        (0x068)
0042 #define LPC32XX_GPIO_P1_OUTP_STATE      (0x06C)
0043 #define LPC32XX_GPIO_P1_DIR_SET         (0x070)
0044 #define LPC32XX_GPIO_P1_DIR_CLR         (0x074)
0045 #define LPC32XX_GPIO_P1_DIR_STATE       (0x078)
0046 
0047 #define GPIO012_PIN_TO_BIT(x)           (1 << (x))
0048 #define GPIO3_PIN_TO_BIT(x)         (1 << ((x) + 25))
0049 #define GPO3_PIN_TO_BIT(x)          (1 << (x))
0050 #define GPIO012_PIN_IN_SEL(x, y)        (((x) >> (y)) & 1)
0051 #define GPIO3_PIN_IN_SHIFT(x)           ((x) == 5 ? 24 : 10 + (x))
0052 #define GPIO3_PIN_IN_SEL(x, y)          (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
0053 #define GPIO3_PIN5_IN_SEL(x)            (((x) >> 24) & 1)
0054 #define GPI3_PIN_IN_SEL(x, y)           (((x) >> (y)) & 1)
0055 #define GPO3_PIN_IN_SEL(x, y)           (((x) >> (y)) & 1)
0056 
0057 #define LPC32XX_GPIO_P0_MAX 8
0058 #define LPC32XX_GPIO_P1_MAX 24
0059 #define LPC32XX_GPIO_P2_MAX 13
0060 #define LPC32XX_GPIO_P3_MAX 6
0061 #define LPC32XX_GPI_P3_MAX  29
0062 #define LPC32XX_GPO_P3_MAX  24
0063 
0064 #define LPC32XX_GPIO_P0_GRP 0
0065 #define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
0066 #define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
0067 #define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
0068 #define LPC32XX_GPI_P3_GRP  (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
0069 #define LPC32XX_GPO_P3_GRP  (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
0070 
0071 struct gpio_regs {
0072     unsigned long inp_state;
0073     unsigned long outp_state;
0074     unsigned long outp_set;
0075     unsigned long outp_clr;
0076     unsigned long dir_set;
0077     unsigned long dir_clr;
0078 };
0079 
0080 /*
0081  * GPIO names
0082  */
0083 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
0084     "p0.0", "p0.1", "p0.2", "p0.3",
0085     "p0.4", "p0.5", "p0.6", "p0.7"
0086 };
0087 
0088 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
0089     "p1.0", "p1.1", "p1.2", "p1.3",
0090     "p1.4", "p1.5", "p1.6", "p1.7",
0091     "p1.8", "p1.9", "p1.10", "p1.11",
0092     "p1.12", "p1.13", "p1.14", "p1.15",
0093     "p1.16", "p1.17", "p1.18", "p1.19",
0094     "p1.20", "p1.21", "p1.22", "p1.23",
0095 };
0096 
0097 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
0098     "p2.0", "p2.1", "p2.2", "p2.3",
0099     "p2.4", "p2.5", "p2.6", "p2.7",
0100     "p2.8", "p2.9", "p2.10", "p2.11",
0101     "p2.12"
0102 };
0103 
0104 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
0105     "gpio00", "gpio01", "gpio02", "gpio03",
0106     "gpio04", "gpio05"
0107 };
0108 
0109 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
0110     "gpi00", "gpi01", "gpi02", "gpi03",
0111     "gpi04", "gpi05", "gpi06", "gpi07",
0112     "gpi08", "gpi09",  NULL,    NULL,
0113      NULL,    NULL,    NULL,   "gpi15",
0114     "gpi16", "gpi17", "gpi18", "gpi19",
0115     "gpi20", "gpi21", "gpi22", "gpi23",
0116     "gpi24", "gpi25", "gpi26", "gpi27",
0117     "gpi28"
0118 };
0119 
0120 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
0121     "gpo00", "gpo01", "gpo02", "gpo03",
0122     "gpo04", "gpo05", "gpo06", "gpo07",
0123     "gpo08", "gpo09", "gpo10", "gpo11",
0124     "gpo12", "gpo13", "gpo14", "gpo15",
0125     "gpo16", "gpo17", "gpo18", "gpo19",
0126     "gpo20", "gpo21", "gpo22", "gpo23"
0127 };
0128 
0129 static struct gpio_regs gpio_grp_regs_p0 = {
0130     .inp_state  = LPC32XX_GPIO_P0_INP_STATE,
0131     .outp_set   = LPC32XX_GPIO_P0_OUTP_SET,
0132     .outp_clr   = LPC32XX_GPIO_P0_OUTP_CLR,
0133     .dir_set    = LPC32XX_GPIO_P0_DIR_SET,
0134     .dir_clr    = LPC32XX_GPIO_P0_DIR_CLR,
0135 };
0136 
0137 static struct gpio_regs gpio_grp_regs_p1 = {
0138     .inp_state  = LPC32XX_GPIO_P1_INP_STATE,
0139     .outp_set   = LPC32XX_GPIO_P1_OUTP_SET,
0140     .outp_clr   = LPC32XX_GPIO_P1_OUTP_CLR,
0141     .dir_set    = LPC32XX_GPIO_P1_DIR_SET,
0142     .dir_clr    = LPC32XX_GPIO_P1_DIR_CLR,
0143 };
0144 
0145 static struct gpio_regs gpio_grp_regs_p2 = {
0146     .inp_state  = LPC32XX_GPIO_P2_INP_STATE,
0147     .outp_set   = LPC32XX_GPIO_P2_OUTP_SET,
0148     .outp_clr   = LPC32XX_GPIO_P2_OUTP_CLR,
0149     .dir_set    = LPC32XX_GPIO_P2_DIR_SET,
0150     .dir_clr    = LPC32XX_GPIO_P2_DIR_CLR,
0151 };
0152 
0153 static struct gpio_regs gpio_grp_regs_p3 = {
0154     .inp_state  = LPC32XX_GPIO_P3_INP_STATE,
0155     .outp_state = LPC32XX_GPIO_P3_OUTP_STATE,
0156     .outp_set   = LPC32XX_GPIO_P3_OUTP_SET,
0157     .outp_clr   = LPC32XX_GPIO_P3_OUTP_CLR,
0158     .dir_set    = LPC32XX_GPIO_P2_DIR_SET,
0159     .dir_clr    = LPC32XX_GPIO_P2_DIR_CLR,
0160 };
0161 
0162 struct lpc32xx_gpio_chip {
0163     struct gpio_chip    chip;
0164     struct gpio_regs    *gpio_grp;
0165     void __iomem        *reg_base;
0166 };
0167 
0168 static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
0169 {
0170     return __raw_readl(group->reg_base + offset);
0171 }
0172 
0173 static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
0174 {
0175     __raw_writel(val, group->reg_base + offset);
0176 }
0177 
0178 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
0179     unsigned pin, int input)
0180 {
0181     if (input)
0182         gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
0183             group->gpio_grp->dir_clr);
0184     else
0185         gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
0186             group->gpio_grp->dir_set);
0187 }
0188 
0189 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
0190     unsigned pin, int input)
0191 {
0192     u32 u = GPIO3_PIN_TO_BIT(pin);
0193 
0194     if (input)
0195         gpreg_write(group, u, group->gpio_grp->dir_clr);
0196     else
0197         gpreg_write(group, u, group->gpio_grp->dir_set);
0198 }
0199 
0200 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
0201     unsigned pin, int high)
0202 {
0203     if (high)
0204         gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
0205             group->gpio_grp->outp_set);
0206     else
0207         gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
0208             group->gpio_grp->outp_clr);
0209 }
0210 
0211 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
0212     unsigned pin, int high)
0213 {
0214     u32 u = GPIO3_PIN_TO_BIT(pin);
0215 
0216     if (high)
0217         gpreg_write(group, u, group->gpio_grp->outp_set);
0218     else
0219         gpreg_write(group, u, group->gpio_grp->outp_clr);
0220 }
0221 
0222 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
0223     unsigned pin, int high)
0224 {
0225     if (high)
0226         gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
0227     else
0228         gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
0229 }
0230 
0231 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
0232     unsigned pin)
0233 {
0234     return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
0235         pin);
0236 }
0237 
0238 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
0239     unsigned pin)
0240 {
0241     int state = gpreg_read(group, group->gpio_grp->inp_state);
0242 
0243     /*
0244      * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
0245      * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
0246      */
0247     return GPIO3_PIN_IN_SEL(state, pin);
0248 }
0249 
0250 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
0251     unsigned pin)
0252 {
0253     return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
0254 }
0255 
0256 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
0257     unsigned pin)
0258 {
0259     return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
0260 }
0261 
0262 /*
0263  * GPIO primitives.
0264  */
0265 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
0266     unsigned pin)
0267 {
0268     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0269 
0270     __set_gpio_dir_p012(group, pin, 1);
0271 
0272     return 0;
0273 }
0274 
0275 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
0276     unsigned pin)
0277 {
0278     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0279 
0280     __set_gpio_dir_p3(group, pin, 1);
0281 
0282     return 0;
0283 }
0284 
0285 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
0286     unsigned pin)
0287 {
0288     return 0;
0289 }
0290 
0291 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
0292 {
0293     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0294 
0295     return !!__get_gpio_state_p012(group, pin);
0296 }
0297 
0298 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
0299 {
0300     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0301 
0302     return !!__get_gpio_state_p3(group, pin);
0303 }
0304 
0305 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
0306 {
0307     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0308 
0309     return !!__get_gpi_state_p3(group, pin);
0310 }
0311 
0312 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
0313     int value)
0314 {
0315     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0316 
0317     __set_gpio_level_p012(group, pin, value);
0318     __set_gpio_dir_p012(group, pin, 0);
0319 
0320     return 0;
0321 }
0322 
0323 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
0324     int value)
0325 {
0326     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0327 
0328     __set_gpio_level_p3(group, pin, value);
0329     __set_gpio_dir_p3(group, pin, 0);
0330 
0331     return 0;
0332 }
0333 
0334 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
0335     int value)
0336 {
0337     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0338 
0339     __set_gpo_level_p3(group, pin, value);
0340     return 0;
0341 }
0342 
0343 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
0344     int value)
0345 {
0346     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0347 
0348     __set_gpio_level_p012(group, pin, value);
0349 }
0350 
0351 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
0352     int value)
0353 {
0354     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0355 
0356     __set_gpio_level_p3(group, pin, value);
0357 }
0358 
0359 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
0360     int value)
0361 {
0362     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0363 
0364     __set_gpo_level_p3(group, pin, value);
0365 }
0366 
0367 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin)
0368 {
0369     struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip);
0370 
0371     return !!__get_gpo_state_p3(group, pin);
0372 }
0373 
0374 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
0375 {
0376     if (pin < chip->ngpio)
0377         return 0;
0378 
0379     return -EINVAL;
0380 }
0381 
0382 static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset)
0383 {
0384     return -ENXIO;
0385 }
0386 
0387 static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset)
0388 {
0389     return -ENXIO;
0390 }
0391 
0392 static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset)
0393 {
0394     return -ENXIO;
0395 }
0396 
0397 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
0398     {
0399         .chip = {
0400             .label          = "gpio_p0",
0401             .direction_input    = lpc32xx_gpio_dir_input_p012,
0402             .get            = lpc32xx_gpio_get_value_p012,
0403             .direction_output   = lpc32xx_gpio_dir_output_p012,
0404             .set            = lpc32xx_gpio_set_value_p012,
0405             .request        = lpc32xx_gpio_request,
0406             .to_irq         = lpc32xx_gpio_to_irq_p01,
0407             .base           = LPC32XX_GPIO_P0_GRP,
0408             .ngpio          = LPC32XX_GPIO_P0_MAX,
0409             .names          = gpio_p0_names,
0410             .can_sleep      = false,
0411         },
0412         .gpio_grp = &gpio_grp_regs_p0,
0413     },
0414     {
0415         .chip = {
0416             .label          = "gpio_p1",
0417             .direction_input    = lpc32xx_gpio_dir_input_p012,
0418             .get            = lpc32xx_gpio_get_value_p012,
0419             .direction_output   = lpc32xx_gpio_dir_output_p012,
0420             .set            = lpc32xx_gpio_set_value_p012,
0421             .request        = lpc32xx_gpio_request,
0422             .to_irq         = lpc32xx_gpio_to_irq_p01,
0423             .base           = LPC32XX_GPIO_P1_GRP,
0424             .ngpio          = LPC32XX_GPIO_P1_MAX,
0425             .names          = gpio_p1_names,
0426             .can_sleep      = false,
0427         },
0428         .gpio_grp = &gpio_grp_regs_p1,
0429     },
0430     {
0431         .chip = {
0432             .label          = "gpio_p2",
0433             .direction_input    = lpc32xx_gpio_dir_input_p012,
0434             .get            = lpc32xx_gpio_get_value_p012,
0435             .direction_output   = lpc32xx_gpio_dir_output_p012,
0436             .set            = lpc32xx_gpio_set_value_p012,
0437             .request        = lpc32xx_gpio_request,
0438             .base           = LPC32XX_GPIO_P2_GRP,
0439             .ngpio          = LPC32XX_GPIO_P2_MAX,
0440             .names          = gpio_p2_names,
0441             .can_sleep      = false,
0442         },
0443         .gpio_grp = &gpio_grp_regs_p2,
0444     },
0445     {
0446         .chip = {
0447             .label          = "gpio_p3",
0448             .direction_input    = lpc32xx_gpio_dir_input_p3,
0449             .get            = lpc32xx_gpio_get_value_p3,
0450             .direction_output   = lpc32xx_gpio_dir_output_p3,
0451             .set            = lpc32xx_gpio_set_value_p3,
0452             .request        = lpc32xx_gpio_request,
0453             .to_irq         = lpc32xx_gpio_to_irq_gpio_p3,
0454             .base           = LPC32XX_GPIO_P3_GRP,
0455             .ngpio          = LPC32XX_GPIO_P3_MAX,
0456             .names          = gpio_p3_names,
0457             .can_sleep      = false,
0458         },
0459         .gpio_grp = &gpio_grp_regs_p3,
0460     },
0461     {
0462         .chip = {
0463             .label          = "gpi_p3",
0464             .direction_input    = lpc32xx_gpio_dir_in_always,
0465             .get            = lpc32xx_gpi_get_value,
0466             .request        = lpc32xx_gpio_request,
0467             .to_irq         = lpc32xx_gpio_to_irq_gpi_p3,
0468             .base           = LPC32XX_GPI_P3_GRP,
0469             .ngpio          = LPC32XX_GPI_P3_MAX,
0470             .names          = gpi_p3_names,
0471             .can_sleep      = false,
0472         },
0473         .gpio_grp = &gpio_grp_regs_p3,
0474     },
0475     {
0476         .chip = {
0477             .label          = "gpo_p3",
0478             .direction_output   = lpc32xx_gpio_dir_out_always,
0479             .set            = lpc32xx_gpo_set_value,
0480             .get            = lpc32xx_gpo_get_value,
0481             .request        = lpc32xx_gpio_request,
0482             .base           = LPC32XX_GPO_P3_GRP,
0483             .ngpio          = LPC32XX_GPO_P3_MAX,
0484             .names          = gpo_p3_names,
0485             .can_sleep      = false,
0486         },
0487         .gpio_grp = &gpio_grp_regs_p3,
0488     },
0489 };
0490 
0491 static int lpc32xx_of_xlate(struct gpio_chip *gc,
0492                 const struct of_phandle_args *gpiospec, u32 *flags)
0493 {
0494     /* Is this the correct bank? */
0495     u32 bank = gpiospec->args[0];
0496     if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) ||
0497         (gc != &lpc32xx_gpiochip[bank].chip)))
0498         return -EINVAL;
0499 
0500     if (flags)
0501         *flags = gpiospec->args[2];
0502     return gpiospec->args[1];
0503 }
0504 
0505 static int lpc32xx_gpio_probe(struct platform_device *pdev)
0506 {
0507     int i;
0508     void __iomem *reg_base;
0509 
0510     reg_base = devm_platform_ioremap_resource(pdev, 0);
0511     if (IS_ERR(reg_base))
0512         return PTR_ERR(reg_base);
0513 
0514     for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
0515         lpc32xx_gpiochip[i].chip.parent = &pdev->dev;
0516         if (pdev->dev.of_node) {
0517             lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
0518             lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
0519             lpc32xx_gpiochip[i].reg_base = reg_base;
0520         }
0521         devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
0522                   &lpc32xx_gpiochip[i]);
0523     }
0524 
0525     return 0;
0526 }
0527 
0528 #ifdef CONFIG_OF
0529 static const struct of_device_id lpc32xx_gpio_of_match[] = {
0530     { .compatible = "nxp,lpc3220-gpio", },
0531     { },
0532 };
0533 #endif
0534 
0535 static struct platform_driver lpc32xx_gpio_driver = {
0536     .driver     = {
0537         .name   = "lpc32xx-gpio",
0538         .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
0539     },
0540     .probe      = lpc32xx_gpio_probe,
0541 };
0542 
0543 module_platform_driver(lpc32xx_gpio_driver);
0544 
0545 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
0546 MODULE_LICENSE("GPL");
0547 MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");
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