drivers/gpio/gpio-ixp4xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // IXP4 GPIO driver
0004 // Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
0005 //
0006 // based on previous work and know-how from:
0007 // Deepak Saxena <dsaxena@plexity.net>
0008
0009 #include <linux/gpio/driver.h>
0010 #include <linux/io.h>
0011 #include <linux/irq.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/irqchip.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/bitops.h>
0017
0018 #define IXP4XX_REG_GPOUT    0x00
0019 #define IXP4XX_REG_GPOE     0x04
0020 #define IXP4XX_REG_GPIN     0x08
0021 #define IXP4XX_REG_GPIS     0x0C
0022 #define IXP4XX_REG_GPIT1    0x10
0023 #define IXP4XX_REG_GPIT2    0x14
0024 #define IXP4XX_REG_GPCLK    0x18
0025 #define IXP4XX_REG_GPDBSEL  0x1C
0026
0027 /*
0028  * The hardware uses 3 bits to indicate interrupt "style".
0029  * we clear and set these three bits accordingly. The lower 24
0030  * bits in two registers (GPIT1 and GPIT2) are used to set up
0031  * the style for 8 lines each for a total of 16 GPIO lines.
0032  */
0033 #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH   0x0
0034 #define IXP4XX_GPIO_STYLE_ACTIVE_LOW    0x1
0035 #define IXP4XX_GPIO_STYLE_RISING_EDGE   0x2
0036 #define IXP4XX_GPIO_STYLE_FALLING_EDGE  0x3
0037 #define IXP4XX_GPIO_STYLE_TRANSITIONAL  0x4
0038 #define IXP4XX_GPIO_STYLE_MASK      GENMASK(2, 0)
0039 #define IXP4XX_GPIO_STYLE_SIZE      3
0040
0041 /**
0042  * struct ixp4xx_gpio - IXP4 GPIO state container
0043  * @dev: containing device for this instance
0044  * @fwnode: the fwnode for this GPIO chip
0045  * @gc: gpiochip for this instance
0046  * @base: remapped I/O-memory base
0047  * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
0048  * 0: level triggered
0049  */
0050 struct ixp4xx_gpio {
0051     struct device *dev;
0052     struct fwnode_handle *fwnode;
0053     struct gpio_chip gc;
0054     void __iomem *base;
0055     unsigned long long irq_edge;
0056 };
0057
0058 static void ixp4xx_gpio_irq_ack(struct irq_data *d)
0059 {
0060     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0061     struct ixp4xx_gpio *g = gpiochip_get_data(gc);
0062
0063     __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
0064 }
0065
0066 static void ixp4xx_gpio_mask_irq(struct irq_data *d)
0067 {
0068     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0069
0070     irq_chip_mask_parent(d);
0071     gpiochip_disable_irq(gc, d->hwirq);
0072 }
0073
0074 static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
0075 {
0076     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0077     struct ixp4xx_gpio *g = gpiochip_get_data(gc);
0078
0079     /* ACK when unmasking if not edge-triggered */
0080     if (!(g->irq_edge & BIT(d->hwirq)))
0081         ixp4xx_gpio_irq_ack(d);
0082
0083     gpiochip_enable_irq(gc, d->hwirq);
0084     irq_chip_unmask_parent(d);
0085 }
0086
0087 static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0088 {
0089     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0090     struct ixp4xx_gpio *g = gpiochip_get_data(gc);
0091     int line = d->hwirq;
0092     unsigned long flags;
0093     u32 int_style;
0094     u32 int_reg;
0095     u32 val;
0096
0097     switch (type) {
0098     case IRQ_TYPE_EDGE_BOTH:
0099         irq_set_handler_locked(d, handle_edge_irq);
0100         int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
0101         g->irq_edge |= BIT(d->hwirq);
0102         break;
0103     case IRQ_TYPE_EDGE_RISING:
0104         irq_set_handler_locked(d, handle_edge_irq);
0105         int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
0106         g->irq_edge |= BIT(d->hwirq);
0107         break;
0108     case IRQ_TYPE_EDGE_FALLING:
0109         irq_set_handler_locked(d, handle_edge_irq);
0110         int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
0111         g->irq_edge |= BIT(d->hwirq);
0112         break;
0113     case IRQ_TYPE_LEVEL_HIGH:
0114         irq_set_handler_locked(d, handle_level_irq);
0115         int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
0116         g->irq_edge &= ~BIT(d->hwirq);
0117         break;
0118     case IRQ_TYPE_LEVEL_LOW:
0119         irq_set_handler_locked(d, handle_level_irq);
0120         int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
0121         g->irq_edge &= ~BIT(d->hwirq);
0122         break;
0123     default:
0124         return -EINVAL;
0125     }
0126
0127     if (line >= 8) {
0128         /* pins 8-15 */
0129         line -= 8;
0130         int_reg = IXP4XX_REG_GPIT2;
0131     } else {
0132         /* pins 0-7 */
0133         int_reg = IXP4XX_REG_GPIT1;
0134     }
0135
0136     raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags);
0137
0138     /* Clear the style for the appropriate pin */
0139     val = __raw_readl(g->base + int_reg);
0140     val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE));
0141     __raw_writel(val, g->base + int_reg);
0142
0143     __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS);
0144
0145     /* Set the new style */
0146     val = __raw_readl(g->base + int_reg);
0147     val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
0148     __raw_writel(val, g->base + int_reg);
0149
0150     /* Force-configure this line as an input */
0151     val = __raw_readl(g->base + IXP4XX_REG_GPOE);
0152     val |= BIT(d->hwirq);
0153     __raw_writel(val, g->base + IXP4XX_REG_GPOE);
0154
0155     raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags);
0156
0157     /* This parent only accept level high (asserted) */
0158     return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
0159 }
0160
0161 static const struct irq_chip ixp4xx_gpio_irqchip = {
0162     .name = "IXP4GPIO",
0163     .irq_ack = ixp4xx_gpio_irq_ack,
0164     .irq_mask = ixp4xx_gpio_mask_irq,
0165     .irq_unmask = ixp4xx_gpio_irq_unmask,
0166     .irq_set_type = ixp4xx_gpio_irq_set_type,
0167     .flags = IRQCHIP_IMMUTABLE,
0168     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0169 };
0170
0171 static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
0172                          unsigned int child,
0173                          unsigned int child_type,
0174                          unsigned int *parent,
0175                          unsigned int *parent_type)
0176 {
0177     /* All these interrupts are level high in the CPU */
0178     *parent_type = IRQ_TYPE_LEVEL_HIGH;
0179
0180     /* GPIO lines 0..12 have dedicated IRQs */
0181     if (child == 0) {
0182         *parent = 6;
0183         return 0;
0184     }
0185     if (child == 1) {
0186         *parent = 7;
0187         return 0;
0188     }
0189     if (child >= 2 && child <= 12) {
0190         *parent = child + 17;
0191         return 0;
0192     }
0193     return -EINVAL;
0194 }
0195
0196 static int ixp4xx_gpio_probe(struct platform_device *pdev)
0197 {
0198     unsigned long flags;
0199     struct device *dev = &pdev->dev;
0200     struct device_node *np = dev->of_node;
0201     struct irq_domain *parent;
0202     struct resource *res;
0203     struct ixp4xx_gpio *g;
0204     struct gpio_irq_chip *girq;
0205     struct device_node *irq_parent;
0206     int ret;
0207
0208     g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
0209     if (!g)
0210         return -ENOMEM;
0211     g->dev = dev;
0212
0213     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0214     g->base = devm_ioremap_resource(dev, res);
0215     if (IS_ERR(g->base))
0216         return PTR_ERR(g->base);
0217
0218     irq_parent = of_irq_find_parent(np);
0219     if (!irq_parent) {
0220         dev_err(dev, "no IRQ parent node\n");
0221         return -ENODEV;
0222     }
0223     parent = irq_find_host(irq_parent);
0224     if (!parent) {
0225         dev_err(dev, "no IRQ parent domain\n");
0226         return -ENODEV;
0227     }
0228     g->fwnode = of_node_to_fwnode(np);
0229
0230     /*
0231      * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on
0232      * specific machines.
0233      */
0234     if (of_machine_is_compatible("dlink,dsm-g600-a") ||
0235         of_machine_is_compatible("iom,nas-100d"))
0236         __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
0237
0238     /*
0239      * This is a very special big-endian ARM issue: when the IXP4xx is
0240      * run in big endian mode, all registers in the machine are switched
0241      * around to the CPU-native endianness. As you see mostly in the
0242      * driver we use __raw_readl()/__raw_writel() to access the registers
0243      * in the appropriate order. With the GPIO library we need to specify
0244      * byte order explicitly, so this flag needs to be set when compiling
0245      * for big endian.
0246      */
0247 #if defined(CONFIG_CPU_BIG_ENDIAN)
0248     flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
0249 #else
0250     flags = 0;
0251 #endif
0252
0253     /* Populate and register gpio chip */
0254     ret = bgpio_init(&g->gc, dev, 4,
0255              g->base + IXP4XX_REG_GPIN,
0256              g->base + IXP4XX_REG_GPOUT,
0257              NULL,
0258              NULL,
0259              g->base + IXP4XX_REG_GPOE,
0260              flags);
0261     if (ret) {
0262         dev_err(dev, "unable to init generic GPIO\n");
0263         return ret;
0264     }
0265     g->gc.ngpio = 16;
0266     g->gc.label = "IXP4XX_GPIO_CHIP";
0267     /*
0268      * TODO: when we have migrated to device tree and all GPIOs
0269      * are fetched using phandles, set this to -1 to get rid of
0270      * the fixed gpiochip base.
0271      */
0272     g->gc.base = 0;
0273     g->gc.parent = &pdev->dev;
0274     g->gc.owner = THIS_MODULE;
0275
0276     girq = &g->gc.irq;
0277     gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip);
0278     girq->fwnode = g->fwnode;
0279     girq->parent_domain = parent;
0280     girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
0281     girq->handler = handle_bad_irq;
0282     girq->default_type = IRQ_TYPE_NONE;
0283
0284     ret = devm_gpiochip_add_data(dev, &g->gc, g);
0285     if (ret) {
0286         dev_err(dev, "failed to add SoC gpiochip\n");
0287         return ret;
0288     }
0289
0290     platform_set_drvdata(pdev, g);
0291     dev_info(dev, "IXP4 GPIO registered\n");
0292
0293     return 0;
0294 }
0295
0296 static const struct of_device_id ixp4xx_gpio_of_match[] = {
0297     {
0298         .compatible = "intel,ixp4xx-gpio",
0299     },
0300     {},
0301 };
0302
0303
0304 static struct platform_driver ixp4xx_gpio_driver = {
0305     .driver = {
0306         .name       = "ixp4xx-gpio",
0307         .of_match_table = of_match_ptr(ixp4xx_gpio_of_match),
0308     },
0309     .probe = ixp4xx_gpio_probe,
0310 };
0311 builtin_platform_driver(ixp4xx_gpio_driver);