drivers/gpio/gpio-hisi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Copyright (c) 2020 HiSilicon Limited. */
0003 #include <linux/gpio/driver.h>
0004 #include <linux/module.h>
0005 #include <linux/mod_devicetable.h>
0006 #include <linux/platform_device.h>
0007 #include <linux/property.h>
0008
0009 #define HISI_GPIO_SWPORT_DR_SET_WX  0x000
0010 #define HISI_GPIO_SWPORT_DR_CLR_WX  0x004
0011 #define HISI_GPIO_SWPORT_DDR_SET_WX 0x010
0012 #define HISI_GPIO_SWPORT_DDR_CLR_WX 0x014
0013 #define HISI_GPIO_SWPORT_DDR_ST_WX  0x018
0014 #define HISI_GPIO_INTEN_SET_WX      0x020
0015 #define HISI_GPIO_INTEN_CLR_WX      0x024
0016 #define HISI_GPIO_INTMASK_SET_WX    0x030
0017 #define HISI_GPIO_INTMASK_CLR_WX    0x034
0018 #define HISI_GPIO_INTTYPE_EDGE_SET_WX   0x040
0019 #define HISI_GPIO_INTTYPE_EDGE_CLR_WX   0x044
0020 #define HISI_GPIO_INT_POLARITY_SET_WX   0x050
0021 #define HISI_GPIO_INT_POLARITY_CLR_WX   0x054
0022 #define HISI_GPIO_DEBOUNCE_SET_WX   0x060
0023 #define HISI_GPIO_DEBOUNCE_CLR_WX   0x064
0024 #define HISI_GPIO_INTSTATUS_WX      0x070
0025 #define HISI_GPIO_PORTA_EOI_WX      0x078
0026 #define HISI_GPIO_EXT_PORT_WX       0x080
0027 #define HISI_GPIO_INTCOMB_MASK_WX   0x0a0
0028 #define HISI_GPIO_INT_DEDGE_SET     0x0b0
0029 #define HISI_GPIO_INT_DEDGE_CLR     0x0b4
0030 #define HISI_GPIO_INT_DEDGE_ST      0x0b8
0031
0032 #define HISI_GPIO_LINE_NUM_MAX  32
0033 #define HISI_GPIO_DRIVER_NAME   "gpio-hisi"
0034
0035 struct hisi_gpio {
0036     struct gpio_chip    chip;
0037     struct device       *dev;
0038     void __iomem        *reg_base;
0039     unsigned int        line_num;
0040     struct irq_chip     irq_chip;
0041     int         irq;
0042 };
0043
0044 static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip,
0045                      unsigned int off)
0046 {
0047     struct hisi_gpio *hisi_gpio =
0048             container_of(chip, struct hisi_gpio, chip);
0049     void __iomem *reg = hisi_gpio->reg_base + off;
0050
0051     return readl(reg);
0052 }
0053
0054 static inline void hisi_gpio_write_reg(struct gpio_chip *chip,
0055                        unsigned int off, u32 val)
0056 {
0057     struct hisi_gpio *hisi_gpio =
0058             container_of(chip, struct hisi_gpio, chip);
0059     void __iomem *reg = hisi_gpio->reg_base + off;
0060
0061     writel(val, reg);
0062 }
0063
0064 static void hisi_gpio_set_debounce(struct gpio_chip *chip, unsigned int off,
0065                    u32 debounce)
0066 {
0067     if (debounce)
0068         hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_SET_WX, BIT(off));
0069     else
0070         hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_CLR_WX, BIT(off));
0071 }
0072
0073 static int hisi_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
0074                 unsigned long config)
0075 {
0076     u32 config_para = pinconf_to_config_param(config);
0077     u32 config_arg;
0078
0079     switch (config_para) {
0080     case PIN_CONFIG_INPUT_DEBOUNCE:
0081         config_arg = pinconf_to_config_argument(config);
0082         hisi_gpio_set_debounce(chip, offset, config_arg);
0083         break;
0084     default:
0085         return -ENOTSUPP;
0086     }
0087
0088     return 0;
0089 }
0090
0091 static void hisi_gpio_set_ack(struct irq_data *d)
0092 {
0093     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0094
0095     hisi_gpio_write_reg(chip, HISI_GPIO_PORTA_EOI_WX, BIT(irqd_to_hwirq(d)));
0096 }
0097
0098 static void hisi_gpio_irq_set_mask(struct irq_data *d)
0099 {
0100     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0101
0102     hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d)));
0103 }
0104
0105 static void hisi_gpio_irq_clr_mask(struct irq_data *d)
0106 {
0107     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0108
0109     hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d)));
0110 }
0111
0112 static int hisi_gpio_irq_set_type(struct irq_data *d, u32 type)
0113 {
0114     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0115     unsigned int mask = BIT(irqd_to_hwirq(d));
0116
0117     switch (type) {
0118     case IRQ_TYPE_EDGE_BOTH:
0119         hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_SET, mask);
0120         break;
0121     case IRQ_TYPE_EDGE_RISING:
0122         hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
0123         hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
0124         break;
0125     case IRQ_TYPE_EDGE_FALLING:
0126         hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
0127         hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
0128         break;
0129     case IRQ_TYPE_LEVEL_HIGH:
0130         hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
0131         hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
0132         break;
0133     case IRQ_TYPE_LEVEL_LOW:
0134         hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
0135         hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
0136         break;
0137     default:
0138         return -EINVAL;
0139     }
0140
0141     /*
0142      * The dual-edge interrupt and other interrupt's registers do not
0143      * take effect at the same time. The registers of the two-edge
0144      * interrupts have higher priorities, the configuration of
0145      * the dual-edge interrupts must be disabled before the configuration
0146      * of other kind of interrupts.
0147      */
0148     if (type != IRQ_TYPE_EDGE_BOTH) {
0149         unsigned int both = hisi_gpio_read_reg(chip, HISI_GPIO_INT_DEDGE_ST);
0150
0151         if (both & mask)
0152             hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_CLR, mask);
0153     }
0154
0155     if (type & IRQ_TYPE_LEVEL_MASK)
0156         irq_set_handler_locked(d, handle_level_irq);
0157     else if (type & IRQ_TYPE_EDGE_BOTH)
0158         irq_set_handler_locked(d, handle_edge_irq);
0159
0160     return 0;
0161 }
0162
0163 static void hisi_gpio_irq_enable(struct irq_data *d)
0164 {
0165     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0166
0167     hisi_gpio_irq_clr_mask(d);
0168     hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_SET_WX, BIT(irqd_to_hwirq(d)));
0169 }
0170
0171 static void hisi_gpio_irq_disable(struct irq_data *d)
0172 {
0173     struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
0174
0175     hisi_gpio_irq_set_mask(d);
0176     hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_CLR_WX, BIT(irqd_to_hwirq(d)));
0177 }
0178
0179 static void hisi_gpio_irq_handler(struct irq_desc *desc)
0180 {
0181     struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc);
0182     unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip,
0183                            HISI_GPIO_INTSTATUS_WX);
0184     struct irq_chip *irq_c = irq_desc_get_chip(desc);
0185     int hwirq;
0186
0187     chained_irq_enter(irq_c, desc);
0188     for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
0189         generic_handle_domain_irq(hisi_gpio->chip.irq.domain,
0190                       hwirq);
0191     chained_irq_exit(irq_c, desc);
0192 }
0193
0194 static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio)
0195 {
0196     struct gpio_chip *chip = &hisi_gpio->chip;
0197     struct gpio_irq_chip *girq_chip = &chip->irq;
0198
0199     /* Set hooks for irq_chip */
0200     hisi_gpio->irq_chip.irq_ack = hisi_gpio_set_ack;
0201     hisi_gpio->irq_chip.irq_mask = hisi_gpio_irq_set_mask;
0202     hisi_gpio->irq_chip.irq_unmask = hisi_gpio_irq_clr_mask;
0203     hisi_gpio->irq_chip.irq_set_type = hisi_gpio_irq_set_type;
0204     hisi_gpio->irq_chip.irq_enable = hisi_gpio_irq_enable;
0205     hisi_gpio->irq_chip.irq_disable = hisi_gpio_irq_disable;
0206
0207     girq_chip->chip = &hisi_gpio->irq_chip;
0208     girq_chip->default_type = IRQ_TYPE_NONE;
0209     girq_chip->num_parents = 1;
0210     girq_chip->parents = &hisi_gpio->irq;
0211     girq_chip->parent_handler = hisi_gpio_irq_handler;
0212     girq_chip->parent_handler_data = hisi_gpio;
0213
0214     /* Clear Mask of GPIO controller combine IRQ */
0215     hisi_gpio_write_reg(chip, HISI_GPIO_INTCOMB_MASK_WX, 1);
0216 }
0217
0218 static const struct acpi_device_id hisi_gpio_acpi_match[] = {
0219     {"HISI0184", 0},
0220     {}
0221 };
0222 MODULE_DEVICE_TABLE(acpi, hisi_gpio_acpi_match);
0223
0224 static void hisi_gpio_get_pdata(struct device *dev,
0225                 struct hisi_gpio *hisi_gpio)
0226 {
0227     struct platform_device *pdev = to_platform_device(dev);
0228     struct fwnode_handle *fwnode;
0229     int idx = 0;
0230
0231     device_for_each_child_node(dev, fwnode)  {
0232         /* Cycle for once, no need for an array to save line_num */
0233         if (fwnode_property_read_u32(fwnode, "ngpios",
0234                          &hisi_gpio->line_num)) {
0235             dev_err(dev,
0236                 "failed to get number of lines for port%d and use default value instead\n",
0237                 idx);
0238             hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
0239         }
0240
0241         if (WARN_ON(hisi_gpio->line_num > HISI_GPIO_LINE_NUM_MAX))
0242             hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
0243
0244         hisi_gpio->irq = platform_get_irq(pdev, idx);
0245
0246         dev_info(dev,
0247              "get hisi_gpio[%d] with %d lines\n", idx,
0248              hisi_gpio->line_num);
0249
0250         idx++;
0251     }
0252 }
0253
0254 static int hisi_gpio_probe(struct platform_device *pdev)
0255 {
0256     struct device *dev = &pdev->dev;
0257     struct hisi_gpio *hisi_gpio;
0258     int port_num;
0259     int ret;
0260
0261     /*
0262      * One GPIO controller own one port currently,
0263      * if we get more from ACPI table, return error.
0264      */
0265     port_num = device_get_child_node_count(dev);
0266     if (WARN_ON(port_num != 1))
0267         return -ENODEV;
0268
0269     hisi_gpio = devm_kzalloc(dev, sizeof(*hisi_gpio), GFP_KERNEL);
0270     if (!hisi_gpio)
0271         return -ENOMEM;
0272
0273     hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
0274     if (IS_ERR(hisi_gpio->reg_base))
0275         return PTR_ERR(hisi_gpio->reg_base);
0276
0277     hisi_gpio_get_pdata(dev, hisi_gpio);
0278
0279     hisi_gpio->dev = dev;
0280
0281     ret = bgpio_init(&hisi_gpio->chip, hisi_gpio->dev, 0x4,
0282              hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX,
0283              hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX,
0284              hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX,
0285              hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX,
0286              hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX,
0287              BGPIOF_NO_SET_ON_INPUT);
0288     if (ret) {
0289         dev_err(dev, "failed to init, ret = %d\n", ret);
0290         return ret;
0291     }
0292
0293     hisi_gpio->chip.set_config = hisi_gpio_set_config;
0294     hisi_gpio->chip.ngpio = hisi_gpio->line_num;
0295     hisi_gpio->chip.bgpio_dir_unreadable = 1;
0296     hisi_gpio->chip.base = -1;
0297
0298     if (hisi_gpio->irq > 0)
0299         hisi_gpio_init_irq(hisi_gpio);
0300
0301     ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip, hisi_gpio);
0302     if (ret) {
0303         dev_err(dev, "failed to register gpiochip, ret = %d\n", ret);
0304         return ret;
0305     }
0306
0307     return 0;
0308 }
0309
0310 static struct platform_driver hisi_gpio_driver = {
0311     .driver     = {
0312         .name   = HISI_GPIO_DRIVER_NAME,
0313         .acpi_match_table = hisi_gpio_acpi_match,
0314     },
0315     .probe      = hisi_gpio_probe,
0316 };
0317
0318 module_platform_driver(hisi_gpio_driver);
0319
0320 MODULE_LICENSE("GPL");
0321 MODULE_AUTHOR("Luo Jiaxing <luojiaxing@huawei.com>");
0322 MODULE_DESCRIPTION("HiSilicon GPIO controller driver");
0323 MODULE_ALIAS("platform:" HISI_GPIO_DRIVER_NAME);