drivers/gpio/gpio-grgpio.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
0004  *
0005  * 2013 (c) Aeroflex Gaisler AB
0006  *
0007  * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
0008  * IP core library.
0009  *
0010  * Full documentation of the GRGPIO core can be found here:
0011  * http://www.gaisler.com/products/grlib/grip.pdf
0012  *
0013  * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
0014  * information on open firmware properties.
0015  *
0016  * Contributors: Andreas Larsson <andreas@gaisler.com>
0017  */
0018
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/init.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/io.h>
0024 #include <linux/of.h>
0025 #include <linux/of_platform.h>
0026 #include <linux/gpio/driver.h>
0027 #include <linux/slab.h>
0028 #include <linux/err.h>
0029 #include <linux/interrupt.h>
0030 #include <linux/irq.h>
0031 #include <linux/irqdomain.h>
0032 #include <linux/bitops.h>
0033
0034 #define GRGPIO_MAX_NGPIO 32
0035
0036 #define GRGPIO_DATA     0x00
0037 #define GRGPIO_OUTPUT       0x04
0038 #define GRGPIO_DIR      0x08
0039 #define GRGPIO_IMASK        0x0c
0040 #define GRGPIO_IPOL     0x10
0041 #define GRGPIO_IEDGE        0x14
0042 #define GRGPIO_BYPASS       0x18
0043 #define GRGPIO_IMAP_BASE    0x20
0044
0045 /* Structure for an irq of the core - called an underlying irq */
0046 struct grgpio_uirq {
0047     u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
0048     u8 uirq; /* Underlying irq of the gpio driver */
0049 };
0050
0051 /*
0052  * Structure for an irq of a gpio line handed out by this driver. The index is
0053  * used to map to the corresponding underlying irq.
0054  */
0055 struct grgpio_lirq {
0056     s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
0057     u8 irq; /* irq for the gpio line */
0058 };
0059
0060 struct grgpio_priv {
0061     struct gpio_chip gc;
0062     void __iomem *regs;
0063     struct device *dev;
0064
0065     u32 imask; /* irq mask shadow register */
0066
0067     /*
0068      * The grgpio core can have multiple "underlying" irqs. The gpio lines
0069      * can be mapped to any one or none of these underlying irqs
0070      * independently of each other. This driver sets up an irq domain and
0071      * hands out separate irqs to each gpio line
0072      */
0073     struct irq_domain *domain;
0074
0075     /*
0076      * This array contains information on each underlying irq, each
0077      * irq of the grgpio core itself.
0078      */
0079     struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
0080
0081     /*
0082      * This array contains information for each gpio line on the irqs
0083      * obtains from this driver. An index value of -1 for a certain gpio
0084      * line indicates that the line has no irq. Otherwise the index connects
0085      * the irq to the underlying irq by pointing into the uirqs array.
0086      */
0087     struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
0088 };
0089
0090 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
0091                  int val)
0092 {
0093     struct gpio_chip *gc = &priv->gc;
0094
0095     if (val)
0096         priv->imask |= BIT(offset);
0097     else
0098         priv->imask &= ~BIT(offset);
0099     gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
0100 }
0101
0102 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
0103 {
0104     struct grgpio_priv *priv = gpiochip_get_data(gc);
0105
0106     if (offset >= gc->ngpio)
0107         return -ENXIO;
0108
0109     if (priv->lirqs[offset].index < 0)
0110         return -ENXIO;
0111
0112     return irq_create_mapping(priv->domain, offset);
0113 }
0114
0115 /* -------------------- IRQ chip functions -------------------- */
0116
0117 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
0118 {
0119     struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
0120     unsigned long flags;
0121     u32 mask = BIT(d->hwirq);
0122     u32 ipol;
0123     u32 iedge;
0124     u32 pol;
0125     u32 edge;
0126
0127     switch (type) {
0128     case IRQ_TYPE_LEVEL_LOW:
0129         pol = 0;
0130         edge = 0;
0131         break;
0132     case IRQ_TYPE_LEVEL_HIGH:
0133         pol = mask;
0134         edge = 0;
0135         break;
0136     case IRQ_TYPE_EDGE_FALLING:
0137         pol = 0;
0138         edge = mask;
0139         break;
0140     case IRQ_TYPE_EDGE_RISING:
0141         pol = mask;
0142         edge = mask;
0143         break;
0144     default:
0145         return -EINVAL;
0146     }
0147
0148     raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0149
0150     ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
0151     iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
0152
0153     priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
0154     priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
0155
0156     raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0157
0158     return 0;
0159 }
0160
0161 static void grgpio_irq_mask(struct irq_data *d)
0162 {
0163     struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
0164     int offset = d->hwirq;
0165     unsigned long flags;
0166
0167     raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0168
0169     grgpio_set_imask(priv, offset, 0);
0170
0171     raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0172 }
0173
0174 static void grgpio_irq_unmask(struct irq_data *d)
0175 {
0176     struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
0177     int offset = d->hwirq;
0178     unsigned long flags;
0179
0180     raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0181
0182     grgpio_set_imask(priv, offset, 1);
0183
0184     raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0185 }
0186
0187 static struct irq_chip grgpio_irq_chip = {
0188     .name           = "grgpio",
0189     .irq_mask       = grgpio_irq_mask,
0190     .irq_unmask     = grgpio_irq_unmask,
0191     .irq_set_type       = grgpio_irq_set_type,
0192 };
0193
0194 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
0195 {
0196     struct grgpio_priv *priv = dev;
0197     int ngpio = priv->gc.ngpio;
0198     unsigned long flags;
0199     int i;
0200     int match = 0;
0201
0202     raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0203
0204     /*
0205      * For each gpio line, call its interrupt handler if it its underlying
0206      * irq matches the current irq that is handled.
0207      */
0208     for (i = 0; i < ngpio; i++) {
0209         struct grgpio_lirq *lirq = &priv->lirqs[i];
0210
0211         if (priv->imask & BIT(i) && lirq->index >= 0 &&
0212             priv->uirqs[lirq->index].uirq == irq) {
0213             generic_handle_irq(lirq->irq);
0214             match = 1;
0215         }
0216     }
0217
0218     raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0219
0220     if (!match)
0221         dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
0222
0223     return IRQ_HANDLED;
0224 }
0225
0226 /*
0227  * This function will be called as a consequence of the call to
0228  * irq_create_mapping in grgpio_to_irq
0229  */
0230 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
0231               irq_hw_number_t hwirq)
0232 {
0233     struct grgpio_priv *priv = d->host_data;
0234     struct grgpio_lirq *lirq;
0235     struct grgpio_uirq *uirq;
0236     unsigned long flags;
0237     int offset = hwirq;
0238     int ret = 0;
0239
0240     if (!priv)
0241         return -EINVAL;
0242
0243     lirq = &priv->lirqs[offset];
0244     if (lirq->index < 0)
0245         return -EINVAL;
0246
0247     dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
0248         irq, offset);
0249
0250     raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0251
0252     /* Request underlying irq if not already requested */
0253     lirq->irq = irq;
0254     uirq = &priv->uirqs[lirq->index];
0255     if (uirq->refcnt == 0) {
0256         raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0257         ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
0258                   dev_name(priv->dev), priv);
0259         if (ret) {
0260             dev_err(priv->dev,
0261                 "Could not request underlying irq %d\n",
0262                 uirq->uirq);
0263             return ret;
0264         }
0265         raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0266     }
0267     uirq->refcnt++;
0268
0269     raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0270
0271     /* Setup irq  */
0272     irq_set_chip_data(irq, priv);
0273     irq_set_chip_and_handler(irq, &grgpio_irq_chip,
0274                  handle_simple_irq);
0275     irq_set_noprobe(irq);
0276
0277     return ret;
0278 }
0279
0280 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
0281 {
0282     struct grgpio_priv *priv = d->host_data;
0283     int index;
0284     struct grgpio_lirq *lirq;
0285     struct grgpio_uirq *uirq;
0286     unsigned long flags;
0287     int ngpio = priv->gc.ngpio;
0288     int i;
0289
0290     irq_set_chip_and_handler(irq, NULL, NULL);
0291     irq_set_chip_data(irq, NULL);
0292
0293     raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
0294
0295     /* Free underlying irq if last user unmapped */
0296     index = -1;
0297     for (i = 0; i < ngpio; i++) {
0298         lirq = &priv->lirqs[i];
0299         if (lirq->irq == irq) {
0300             grgpio_set_imask(priv, i, 0);
0301             lirq->irq = 0;
0302             index = lirq->index;
0303             break;
0304         }
0305     }
0306     WARN_ON(index < 0);
0307
0308     if (index >= 0) {
0309         uirq = &priv->uirqs[lirq->index];
0310         uirq->refcnt--;
0311         if (uirq->refcnt == 0) {
0312             raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0313             free_irq(uirq->uirq, priv);
0314             return;
0315         }
0316     }
0317
0318     raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
0319 }
0320
0321 static const struct irq_domain_ops grgpio_irq_domain_ops = {
0322     .map    = grgpio_irq_map,
0323     .unmap  = grgpio_irq_unmap,
0324 };
0325
0326 /* ------------------------------------------------------------ */
0327
0328 static int grgpio_probe(struct platform_device *ofdev)
0329 {
0330     struct device_node *np = ofdev->dev.of_node;
0331     void  __iomem *regs;
0332     struct gpio_chip *gc;
0333     struct grgpio_priv *priv;
0334     int err;
0335     u32 prop;
0336     s32 *irqmap;
0337     int size;
0338     int i;
0339
0340     priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
0341     if (!priv)
0342         return -ENOMEM;
0343
0344     regs = devm_platform_ioremap_resource(ofdev, 0);
0345     if (IS_ERR(regs))
0346         return PTR_ERR(regs);
0347
0348     gc = &priv->gc;
0349     err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
0350              regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
0351              BGPIOF_BIG_ENDIAN_BYTE_ORDER);
0352     if (err) {
0353         dev_err(&ofdev->dev, "bgpio_init() failed\n");
0354         return err;
0355     }
0356
0357     priv->regs = regs;
0358     priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
0359     priv->dev = &ofdev->dev;
0360
0361     gc->owner = THIS_MODULE;
0362     gc->to_irq = grgpio_to_irq;
0363     gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
0364     gc->base = -1;
0365
0366     err = of_property_read_u32(np, "nbits", &prop);
0367     if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
0368         gc->ngpio = GRGPIO_MAX_NGPIO;
0369         dev_dbg(&ofdev->dev,
0370             "No or invalid nbits property: assume %d\n", gc->ngpio);
0371     } else {
0372         gc->ngpio = prop;
0373     }
0374
0375     /*
0376      * The irqmap contains the index values indicating which underlying irq,
0377      * if anyone, is connected to that line
0378      */
0379     irqmap = (s32 *)of_get_property(np, "irqmap", &size);
0380     if (irqmap) {
0381         if (size < gc->ngpio) {
0382             dev_err(&ofdev->dev,
0383                 "irqmap shorter than ngpio (%d < %d)\n",
0384                 size, gc->ngpio);
0385             return -EINVAL;
0386         }
0387
0388         priv->domain = irq_domain_add_linear(np, gc->ngpio,
0389                              &grgpio_irq_domain_ops,
0390                              priv);
0391         if (!priv->domain) {
0392             dev_err(&ofdev->dev, "Could not add irq domain\n");
0393             return -EINVAL;
0394         }
0395
0396         for (i = 0; i < gc->ngpio; i++) {
0397             struct grgpio_lirq *lirq;
0398             int ret;
0399
0400             lirq = &priv->lirqs[i];
0401             lirq->index = irqmap[i];
0402
0403             if (lirq->index < 0)
0404                 continue;
0405
0406             ret = platform_get_irq(ofdev, lirq->index);
0407             if (ret <= 0) {
0408                 /*
0409                  * Continue without irq functionality for that
0410                  * gpio line
0411                  */
0412                 continue;
0413             }
0414             priv->uirqs[lirq->index].uirq = ret;
0415         }
0416     }
0417
0418     platform_set_drvdata(ofdev, priv);
0419
0420     err = gpiochip_add_data(gc, priv);
0421     if (err) {
0422         dev_err(&ofdev->dev, "Could not add gpiochip\n");
0423         if (priv->domain)
0424             irq_domain_remove(priv->domain);
0425         return err;
0426     }
0427
0428     dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
0429          priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
0430
0431     return 0;
0432 }
0433
0434 static int grgpio_remove(struct platform_device *ofdev)
0435 {
0436     struct grgpio_priv *priv = platform_get_drvdata(ofdev);
0437
0438     gpiochip_remove(&priv->gc);
0439
0440     if (priv->domain)
0441         irq_domain_remove(priv->domain);
0442
0443     return 0;
0444 }
0445
0446 static const struct of_device_id grgpio_match[] = {
0447     {.name = "GAISLER_GPIO"},
0448     {.name = "01_01a"},
0449     {},
0450 };
0451
0452 MODULE_DEVICE_TABLE(of, grgpio_match);
0453
0454 static struct platform_driver grgpio_driver = {
0455     .driver = {
0456         .name = "grgpio",
0457         .of_match_table = grgpio_match,
0458     },
0459     .probe = grgpio_probe,
0460     .remove = grgpio_remove,
0461 };
0462 module_platform_driver(grgpio_driver);
0463
0464 MODULE_AUTHOR("Aeroflex Gaisler AB.");
0465 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
0466 MODULE_LICENSE("GPL");