drivers/gpio/gpio-ftgpio010.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Faraday Technolog FTGPIO010 gpiochip and interrupt routines
0004  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0005  *
0006  * Based on arch/arm/mach-gemini/gpio.c:
0007  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
0008  *
0009  * Based on plat-mxc/gpio.c:
0010  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
0011  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
0012  */
0013 #include <linux/gpio/driver.h>
0014 #include <linux/io.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/bitops.h>
0018 #include <linux/clk.h>
0019
0020 /* GPIO registers definition */
0021 #define GPIO_DATA_OUT       0x00
0022 #define GPIO_DATA_IN        0x04
0023 #define GPIO_DIR        0x08
0024 #define GPIO_BYPASS_IN      0x0C
0025 #define GPIO_DATA_SET       0x10
0026 #define GPIO_DATA_CLR       0x14
0027 #define GPIO_PULL_EN        0x18
0028 #define GPIO_PULL_TYPE      0x1C
0029 #define GPIO_INT_EN     0x20
0030 #define GPIO_INT_STAT_RAW   0x24
0031 #define GPIO_INT_STAT_MASKED    0x28
0032 #define GPIO_INT_MASK       0x2C
0033 #define GPIO_INT_CLR        0x30
0034 #define GPIO_INT_TYPE       0x34
0035 #define GPIO_INT_BOTH_EDGE  0x38
0036 #define GPIO_INT_LEVEL      0x3C
0037 #define GPIO_DEBOUNCE_EN    0x40
0038 #define GPIO_DEBOUNCE_PRESCALE  0x44
0039
0040 /**
0041  * struct ftgpio_gpio - Gemini GPIO state container
0042  * @dev: containing device for this instance
0043  * @gc: gpiochip for this instance
0044  * @base: remapped I/O-memory base
0045  * @clk: silicon clock
0046  */
0047 struct ftgpio_gpio {
0048     struct device *dev;
0049     struct gpio_chip gc;
0050     void __iomem *base;
0051     struct clk *clk;
0052 };
0053
0054 static void ftgpio_gpio_ack_irq(struct irq_data *d)
0055 {
0056     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0057     struct ftgpio_gpio *g = gpiochip_get_data(gc);
0058
0059     writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
0060 }
0061
0062 static void ftgpio_gpio_mask_irq(struct irq_data *d)
0063 {
0064     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0065     struct ftgpio_gpio *g = gpiochip_get_data(gc);
0066     u32 val;
0067
0068     val = readl(g->base + GPIO_INT_EN);
0069     val &= ~BIT(irqd_to_hwirq(d));
0070     writel(val, g->base + GPIO_INT_EN);
0071     gpiochip_disable_irq(gc, irqd_to_hwirq(d));
0072 }
0073
0074 static void ftgpio_gpio_unmask_irq(struct irq_data *d)
0075 {
0076     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0077     struct ftgpio_gpio *g = gpiochip_get_data(gc);
0078     u32 val;
0079
0080     gpiochip_enable_irq(gc, irqd_to_hwirq(d));
0081     val = readl(g->base + GPIO_INT_EN);
0082     val |= BIT(irqd_to_hwirq(d));
0083     writel(val, g->base + GPIO_INT_EN);
0084 }
0085
0086 static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
0087 {
0088     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0089     struct ftgpio_gpio *g = gpiochip_get_data(gc);
0090     u32 mask = BIT(irqd_to_hwirq(d));
0091     u32 reg_both, reg_level, reg_type;
0092
0093     reg_type = readl(g->base + GPIO_INT_TYPE);
0094     reg_level = readl(g->base + GPIO_INT_LEVEL);
0095     reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
0096
0097     switch (type) {
0098     case IRQ_TYPE_EDGE_BOTH:
0099         irq_set_handler_locked(d, handle_edge_irq);
0100         reg_type &= ~mask;
0101         reg_both |= mask;
0102         break;
0103     case IRQ_TYPE_EDGE_RISING:
0104         irq_set_handler_locked(d, handle_edge_irq);
0105         reg_type &= ~mask;
0106         reg_both &= ~mask;
0107         reg_level &= ~mask;
0108         break;
0109     case IRQ_TYPE_EDGE_FALLING:
0110         irq_set_handler_locked(d, handle_edge_irq);
0111         reg_type &= ~mask;
0112         reg_both &= ~mask;
0113         reg_level |= mask;
0114         break;
0115     case IRQ_TYPE_LEVEL_HIGH:
0116         irq_set_handler_locked(d, handle_level_irq);
0117         reg_type |= mask;
0118         reg_level &= ~mask;
0119         break;
0120     case IRQ_TYPE_LEVEL_LOW:
0121         irq_set_handler_locked(d, handle_level_irq);
0122         reg_type |= mask;
0123         reg_level |= mask;
0124         break;
0125     default:
0126         irq_set_handler_locked(d, handle_bad_irq);
0127         return -EINVAL;
0128     }
0129
0130     writel(reg_type, g->base + GPIO_INT_TYPE);
0131     writel(reg_level, g->base + GPIO_INT_LEVEL);
0132     writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
0133
0134     ftgpio_gpio_ack_irq(d);
0135
0136     return 0;
0137 }
0138
0139 static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
0140 {
0141     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0142     struct ftgpio_gpio *g = gpiochip_get_data(gc);
0143     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0144     int offset;
0145     unsigned long stat;
0146
0147     chained_irq_enter(irqchip, desc);
0148
0149     stat = readl(g->base + GPIO_INT_STAT_RAW);
0150     if (stat)
0151         for_each_set_bit(offset, &stat, gc->ngpio)
0152             generic_handle_domain_irq(gc->irq.domain, offset);
0153
0154     chained_irq_exit(irqchip, desc);
0155 }
0156
0157 static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
0158                   unsigned long config)
0159 {
0160     enum pin_config_param param = pinconf_to_config_param(config);
0161     u32 arg = pinconf_to_config_argument(config);
0162     struct ftgpio_gpio *g = gpiochip_get_data(gc);
0163     unsigned long pclk_freq;
0164     u32 deb_div;
0165     u32 val;
0166
0167     if (param != PIN_CONFIG_INPUT_DEBOUNCE)
0168         return -ENOTSUPP;
0169
0170     /*
0171      * Debounce only works if interrupts are enabled. The manual
0172      * states that if PCLK is 66 MHz, and this is set to 0x7D0, then
0173      * PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
0174      * 2000 decimal, so what they mean is simply that the PCLK is
0175      * divided by this value.
0176      *
0177      * As we get a debounce setting in microseconds, we calculate the
0178      * desired period time and see if we can get a suitable debounce
0179      * time.
0180      */
0181     pclk_freq = clk_get_rate(g->clk);
0182     deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);
0183
0184     /* This register is only 24 bits wide */
0185     if (deb_div > (1 << 24))
0186         return -ENOTSUPP;
0187
0188     dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
0189         deb_div, (pclk_freq/deb_div));
0190
0191     val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
0192     if (val == deb_div) {
0193         /*
0194          * The debounce timer happens to already be set to the
0195          * desirable value, what a coincidence! We can just enable
0196          * debounce on this GPIO line and return. This happens more
0197          * often than you think, for example when all GPIO keys
0198          * on a system are requesting the same debounce interval.
0199          */
0200         val = readl(g->base + GPIO_DEBOUNCE_EN);
0201         val |= BIT(offset);
0202         writel(val, g->base + GPIO_DEBOUNCE_EN);
0203         return 0;
0204     }
0205
0206     val = readl(g->base + GPIO_DEBOUNCE_EN);
0207     if (val) {
0208         /*
0209          * Oh no! Someone is already using the debounce with
0210          * another setting than what we need. Bummer.
0211          */
0212         return -ENOTSUPP;
0213     }
0214
0215     /* First come, first serve */
0216     writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
0217     /* Enable debounce */
0218     val |= BIT(offset);
0219     writel(val, g->base + GPIO_DEBOUNCE_EN);
0220
0221     return 0;
0222 }
0223
0224 static const struct irq_chip ftgpio_irq_chip = {
0225     .name = "FTGPIO010",
0226     .irq_ack = ftgpio_gpio_ack_irq,
0227     .irq_mask = ftgpio_gpio_mask_irq,
0228     .irq_unmask = ftgpio_gpio_unmask_irq,
0229     .irq_set_type = ftgpio_gpio_set_irq_type,
0230     .flags = IRQCHIP_IMMUTABLE,
0231      GPIOCHIP_IRQ_RESOURCE_HELPERS,
0232 };
0233
0234 static int ftgpio_gpio_probe(struct platform_device *pdev)
0235 {
0236     struct device *dev = &pdev->dev;
0237     struct ftgpio_gpio *g;
0238     struct gpio_irq_chip *girq;
0239     int irq;
0240     int ret;
0241
0242     g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
0243     if (!g)
0244         return -ENOMEM;
0245
0246     g->dev = dev;
0247
0248     g->base = devm_platform_ioremap_resource(pdev, 0);
0249     if (IS_ERR(g->base))
0250         return PTR_ERR(g->base);
0251
0252     irq = platform_get_irq(pdev, 0);
0253     if (irq <= 0)
0254         return irq ? irq : -EINVAL;
0255
0256     g->clk = devm_clk_get(dev, NULL);
0257     if (!IS_ERR(g->clk)) {
0258         ret = clk_prepare_enable(g->clk);
0259         if (ret)
0260             return ret;
0261     } else if (PTR_ERR(g->clk) == -EPROBE_DEFER) {
0262         /*
0263          * Percolate deferrals, for anything else,
0264          * just live without the clocking.
0265          */
0266         return PTR_ERR(g->clk);
0267     }
0268
0269     ret = bgpio_init(&g->gc, dev, 4,
0270              g->base + GPIO_DATA_IN,
0271              g->base + GPIO_DATA_SET,
0272              g->base + GPIO_DATA_CLR,
0273              g->base + GPIO_DIR,
0274              NULL,
0275              0);
0276     if (ret) {
0277         dev_err(dev, "unable to init generic GPIO\n");
0278         goto dis_clk;
0279     }
0280     g->gc.label = "FTGPIO010";
0281     g->gc.base = -1;
0282     g->gc.parent = dev;
0283     g->gc.owner = THIS_MODULE;
0284     /* ngpio is set by bgpio_init() */
0285
0286     /* We need a silicon clock to do debounce */
0287     if (!IS_ERR(g->clk))
0288         g->gc.set_config = ftgpio_gpio_set_config;
0289
0290     girq = &g->gc.irq;
0291     gpio_irq_chip_set_chip(girq, &ftgpio_irq_chip);
0292     girq->parent_handler = ftgpio_gpio_irq_handler;
0293     girq->num_parents = 1;
0294     girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
0295                      GFP_KERNEL);
0296     if (!girq->parents) {
0297         ret = -ENOMEM;
0298         goto dis_clk;
0299     }
0300     girq->default_type = IRQ_TYPE_NONE;
0301     girq->handler = handle_bad_irq;
0302     girq->parents[0] = irq;
0303
0304     /* Disable, unmask and clear all interrupts */
0305     writel(0x0, g->base + GPIO_INT_EN);
0306     writel(0x0, g->base + GPIO_INT_MASK);
0307     writel(~0x0, g->base + GPIO_INT_CLR);
0308
0309     /* Clear any use of debounce */
0310     writel(0x0, g->base + GPIO_DEBOUNCE_EN);
0311
0312     ret = devm_gpiochip_add_data(dev, &g->gc, g);
0313     if (ret)
0314         goto dis_clk;
0315
0316     platform_set_drvdata(pdev, g);
0317     dev_info(dev, "FTGPIO010 @%p registered\n", g->base);
0318
0319     return 0;
0320
0321 dis_clk:
0322     clk_disable_unprepare(g->clk);
0323
0324     return ret;
0325 }
0326
0327 static int ftgpio_gpio_remove(struct platform_device *pdev)
0328 {
0329     struct ftgpio_gpio *g = platform_get_drvdata(pdev);
0330
0331     clk_disable_unprepare(g->clk);
0332
0333     return 0;
0334 }
0335
0336 static const struct of_device_id ftgpio_gpio_of_match[] = {
0337     {
0338         .compatible = "cortina,gemini-gpio",
0339     },
0340     {
0341         .compatible = "moxa,moxart-gpio",
0342     },
0343     {
0344         .compatible = "faraday,ftgpio010",
0345     },
0346     {},
0347 };
0348
0349 static struct platform_driver ftgpio_gpio_driver = {
0350     .driver = {
0351         .name       = "ftgpio010-gpio",
0352         .of_match_table = of_match_ptr(ftgpio_gpio_of_match),
0353     },
0354     .probe = ftgpio_gpio_probe,
0355     .remove = ftgpio_gpio_remove,
0356 };
0357 builtin_platform_driver(ftgpio_gpio_driver);