drivers/gpio/gpio-ep93xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Generic EP93xx GPIO handling
0004  *
0005  * Copyright (c) 2008 Ryan Mallon
0006  * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
0007  *
0008  * Based on code originally from:
0009  *  linux/arch/arm/mach-ep93xx/core.c
0010  */
0011
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/io.h>
0016 #include <linux/irq.h>
0017 #include <linux/slab.h>
0018 #include <linux/gpio/driver.h>
0019 #include <linux/bitops.h>
0020
0021 #define EP93XX_GPIO_F_INT_STATUS 0x5c
0022 #define EP93XX_GPIO_A_INT_STATUS 0xa0
0023 #define EP93XX_GPIO_B_INT_STATUS 0xbc
0024
0025 /* Maximum value for gpio line identifiers */
0026 #define EP93XX_GPIO_LINE_MAX 63
0027
0028 /* Number of GPIO chips in EP93XX */
0029 #define EP93XX_GPIO_CHIP_NUM 8
0030
0031 /* Maximum value for irq capable line identifiers */
0032 #define EP93XX_GPIO_LINE_MAX_IRQ 23
0033
0034 #define EP93XX_GPIO_A_IRQ_BASE 64
0035 #define EP93XX_GPIO_B_IRQ_BASE 72
0036 /*
0037  * Static mapping of GPIO bank F IRQS:
0038  * F0..F7 (16..24) to irq 80..87.
0039  */
0040 #define EP93XX_GPIO_F_IRQ_BASE 80
0041
0042 struct ep93xx_gpio_irq_chip {
0043     struct irq_chip ic;
0044     u8 irq_offset;
0045     u8 int_unmasked;
0046     u8 int_enabled;
0047     u8 int_type1;
0048     u8 int_type2;
0049     u8 int_debounce;
0050 };
0051
0052 struct ep93xx_gpio_chip {
0053     struct gpio_chip        gc;
0054     struct ep93xx_gpio_irq_chip *eic;
0055 };
0056
0057 struct ep93xx_gpio {
0058     void __iomem        *base;
0059     struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
0060 };
0061
0062 #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
0063
0064 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
0065 {
0066     struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
0067
0068     return egc->eic;
0069 }
0070
0071 /*************************************************************************
0072  * Interrupt handling for EP93xx on-chip GPIOs
0073  *************************************************************************/
0074 #define EP93XX_INT_TYPE1_OFFSET     0x00
0075 #define EP93XX_INT_TYPE2_OFFSET     0x04
0076 #define EP93XX_INT_EOI_OFFSET       0x08
0077 #define EP93XX_INT_EN_OFFSET        0x0c
0078 #define EP93XX_INT_STATUS_OFFSET    0x10
0079 #define EP93XX_INT_RAW_STATUS_OFFSET    0x14
0080 #define EP93XX_INT_DEBOUNCE_OFFSET  0x18
0081
0082 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
0083                       struct ep93xx_gpio_irq_chip *eic)
0084 {
0085     writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
0086
0087     writeb_relaxed(eic->int_type2,
0088                epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
0089
0090     writeb_relaxed(eic->int_type1,
0091                epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
0092
0093     writeb_relaxed(eic->int_unmasked & eic->int_enabled,
0094                epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
0095 }
0096
0097 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
0098                      unsigned int offset, bool enable)
0099 {
0100     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0101     struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
0102     int port_mask = BIT(offset);
0103
0104     if (enable)
0105         eic->int_debounce |= port_mask;
0106     else
0107         eic->int_debounce &= ~port_mask;
0108
0109     writeb(eic->int_debounce,
0110            epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
0111 }
0112
0113 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
0114 {
0115     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0116     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0117     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0118     unsigned long stat;
0119     int offset;
0120
0121     chained_irq_enter(irqchip, desc);
0122
0123     /*
0124      * Dispatch the IRQs to the irqdomain of each A and B
0125      * gpiochip irqdomains depending on what has fired.
0126      * The tricky part is that the IRQ line is shared
0127      * between bank A and B and each has their own gpiochip.
0128      */
0129     stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
0130     for_each_set_bit(offset, &stat, 8)
0131         generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
0132                       offset);
0133
0134     stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
0135     for_each_set_bit(offset, &stat, 8)
0136         generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
0137                       offset);
0138
0139     chained_irq_exit(irqchip, desc);
0140 }
0141
0142 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
0143 {
0144     /*
0145      * map discontiguous hw irq range to continuous sw irq range:
0146      *
0147      *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
0148      */
0149     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0150     unsigned int irq = irq_desc_get_irq(desc);
0151     int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
0152     int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
0153
0154     chained_irq_enter(irqchip, desc);
0155     generic_handle_irq(gpio_irq);
0156     chained_irq_exit(irqchip, desc);
0157 }
0158
0159 static void ep93xx_gpio_irq_ack(struct irq_data *d)
0160 {
0161     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0162     struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
0163     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0164     int port_mask = BIT(d->irq & 7);
0165
0166     if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
0167         eic->int_type2 ^= port_mask; /* switch edge direction */
0168         ep93xx_gpio_update_int_params(epg, eic);
0169     }
0170
0171     writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
0172 }
0173
0174 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
0175 {
0176     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0177     struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
0178     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0179     int port_mask = BIT(d->irq & 7);
0180
0181     if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
0182         eic->int_type2 ^= port_mask; /* switch edge direction */
0183
0184     eic->int_unmasked &= ~port_mask;
0185     ep93xx_gpio_update_int_params(epg, eic);
0186
0187     writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
0188 }
0189
0190 static void ep93xx_gpio_irq_mask(struct irq_data *d)
0191 {
0192     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0193     struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
0194     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0195
0196     eic->int_unmasked &= ~BIT(d->irq & 7);
0197     ep93xx_gpio_update_int_params(epg, eic);
0198 }
0199
0200 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
0201 {
0202     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0203     struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
0204     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0205
0206     eic->int_unmasked |= BIT(d->irq & 7);
0207     ep93xx_gpio_update_int_params(epg, eic);
0208 }
0209
0210 /*
0211  * gpio_int_type1 controls whether the interrupt is level (0) or
0212  * edge (1) triggered, while gpio_int_type2 controls whether it
0213  * triggers on low/falling (0) or high/rising (1).
0214  */
0215 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
0216 {
0217     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0218     struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
0219     struct ep93xx_gpio *epg = gpiochip_get_data(gc);
0220     int offset = d->irq & 7;
0221     int port_mask = BIT(offset);
0222     irq_flow_handler_t handler;
0223
0224     gc->direction_input(gc, offset);
0225
0226     switch (type) {
0227     case IRQ_TYPE_EDGE_RISING:
0228         eic->int_type1 |= port_mask;
0229         eic->int_type2 |= port_mask;
0230         handler = handle_edge_irq;
0231         break;
0232     case IRQ_TYPE_EDGE_FALLING:
0233         eic->int_type1 |= port_mask;
0234         eic->int_type2 &= ~port_mask;
0235         handler = handle_edge_irq;
0236         break;
0237     case IRQ_TYPE_LEVEL_HIGH:
0238         eic->int_type1 &= ~port_mask;
0239         eic->int_type2 |= port_mask;
0240         handler = handle_level_irq;
0241         break;
0242     case IRQ_TYPE_LEVEL_LOW:
0243         eic->int_type1 &= ~port_mask;
0244         eic->int_type2 &= ~port_mask;
0245         handler = handle_level_irq;
0246         break;
0247     case IRQ_TYPE_EDGE_BOTH:
0248         eic->int_type1 |= port_mask;
0249         /* set initial polarity based on current input level */
0250         if (gc->get(gc, offset))
0251             eic->int_type2 &= ~port_mask; /* falling */
0252         else
0253             eic->int_type2 |= port_mask; /* rising */
0254         handler = handle_edge_irq;
0255         break;
0256     default:
0257         return -EINVAL;
0258     }
0259
0260     irq_set_handler_locked(d, handler);
0261
0262     eic->int_enabled |= port_mask;
0263
0264     ep93xx_gpio_update_int_params(epg, eic);
0265
0266     return 0;
0267 }
0268
0269 /*************************************************************************
0270  * gpiolib interface for EP93xx on-chip GPIOs
0271  *************************************************************************/
0272 struct ep93xx_gpio_bank {
0273     const char  *label;
0274     int     data;
0275     int     dir;
0276     int     irq;
0277     int     base;
0278     bool        has_irq;
0279     bool        has_hierarchical_irq;
0280     unsigned int    irq_base;
0281 };
0282
0283 #define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
0284     {                           \
0285         .label      = _label,           \
0286         .data       = _data,            \
0287         .dir        = _dir,             \
0288         .irq        = _irq,             \
0289         .base       = _base,            \
0290         .has_irq    = _has_irq,         \
0291         .has_hierarchical_irq = _has_hier,      \
0292         .irq_base   = _irq_base,            \
0293     }
0294
0295 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
0296     /* Bank A has 8 IRQs */
0297     EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
0298     /* Bank B has 8 IRQs */
0299     EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
0300     EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
0301     EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
0302     EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
0303     /* Bank F has 8 IRQs */
0304     EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
0305     EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
0306     EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
0307 };
0308
0309 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
0310                   unsigned long config)
0311 {
0312     u32 debounce;
0313
0314     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0315         return -ENOTSUPP;
0316
0317     debounce = pinconf_to_config_argument(config);
0318     ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
0319
0320     return 0;
0321 }
0322
0323 static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic)
0324 {
0325     ic->irq_ack = ep93xx_gpio_irq_ack;
0326     ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack;
0327     ic->irq_mask = ep93xx_gpio_irq_mask;
0328     ic->irq_unmask = ep93xx_gpio_irq_unmask;
0329     ic->irq_set_type = ep93xx_gpio_irq_type;
0330 }
0331
0332 static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
0333                 struct platform_device *pdev,
0334                 struct ep93xx_gpio *epg,
0335                 struct ep93xx_gpio_bank *bank)
0336 {
0337     void __iomem *data = epg->base + bank->data;
0338     void __iomem *dir = epg->base + bank->dir;
0339     struct gpio_chip *gc = &egc->gc;
0340     struct device *dev = &pdev->dev;
0341     struct gpio_irq_chip *girq;
0342     int err;
0343
0344     err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
0345     if (err)
0346         return err;
0347
0348     gc->label = bank->label;
0349     gc->base = bank->base;
0350
0351     girq = &gc->irq;
0352     if (bank->has_irq || bank->has_hierarchical_irq) {
0353         struct irq_chip *ic;
0354
0355         gc->set_config = ep93xx_gpio_set_config;
0356         egc->eic = devm_kcalloc(dev, 1,
0357                     sizeof(*egc->eic),
0358                     GFP_KERNEL);
0359         if (!egc->eic)
0360             return -ENOMEM;
0361         egc->eic->irq_offset = bank->irq;
0362         ic = &egc->eic->ic;
0363         ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label);
0364         if (!ic->name)
0365             return -ENOMEM;
0366         ep93xx_init_irq_chip(dev, ic);
0367         girq->chip = ic;
0368     }
0369
0370     if (bank->has_irq) {
0371         int ab_parent_irq = platform_get_irq(pdev, 0);
0372
0373         girq->parent_handler = ep93xx_gpio_ab_irq_handler;
0374         girq->num_parents = 1;
0375         girq->parents = devm_kcalloc(dev, girq->num_parents,
0376                          sizeof(*girq->parents),
0377                          GFP_KERNEL);
0378         if (!girq->parents)
0379             return -ENOMEM;
0380         girq->default_type = IRQ_TYPE_NONE;
0381         girq->handler = handle_level_irq;
0382         girq->parents[0] = ab_parent_irq;
0383         girq->first = bank->irq_base;
0384     }
0385
0386     /* Only bank F has especially funky IRQ handling */
0387     if (bank->has_hierarchical_irq) {
0388         int gpio_irq;
0389         int i;
0390
0391         /*
0392          * FIXME: convert this to use hierarchical IRQ support!
0393          * this requires fixing the root irqchip to be hierarchical.
0394          */
0395         girq->parent_handler = ep93xx_gpio_f_irq_handler;
0396         girq->num_parents = 8;
0397         girq->parents = devm_kcalloc(dev, girq->num_parents,
0398                          sizeof(*girq->parents),
0399                          GFP_KERNEL);
0400         if (!girq->parents)
0401             return -ENOMEM;
0402         /* Pick resources 1..8 for these IRQs */
0403         for (i = 0; i < girq->num_parents; i++) {
0404             girq->parents[i] = platform_get_irq(pdev, i + 1);
0405             gpio_irq = bank->irq_base + i;
0406             irq_set_chip_data(gpio_irq, &epg->gc[5]);
0407             irq_set_chip_and_handler(gpio_irq,
0408                          girq->chip,
0409                          handle_level_irq);
0410             irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
0411         }
0412         girq->default_type = IRQ_TYPE_NONE;
0413         girq->handler = handle_level_irq;
0414         girq->first = bank->irq_base;
0415     }
0416
0417     return devm_gpiochip_add_data(dev, gc, epg);
0418 }
0419
0420 static int ep93xx_gpio_probe(struct platform_device *pdev)
0421 {
0422     struct ep93xx_gpio *epg;
0423     int i;
0424
0425     epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
0426     if (!epg)
0427         return -ENOMEM;
0428
0429     epg->base = devm_platform_ioremap_resource(pdev, 0);
0430     if (IS_ERR(epg->base))
0431         return PTR_ERR(epg->base);
0432
0433     for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
0434         struct ep93xx_gpio_chip *gc = &epg->gc[i];
0435         struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
0436
0437         if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
0438             dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
0439                  bank->label);
0440     }
0441
0442     return 0;
0443 }
0444
0445 static struct platform_driver ep93xx_gpio_driver = {
0446     .driver     = {
0447         .name   = "gpio-ep93xx",
0448     },
0449     .probe      = ep93xx_gpio_probe,
0450 };
0451
0452 static int __init ep93xx_gpio_init(void)
0453 {
0454     return platform_driver_register(&ep93xx_gpio_driver);
0455 }
0456 postcore_initcall(ep93xx_gpio_init);
0457
0458 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
0459         "H Hartley Sweeten <hsweeten@visionengravers.com>");
0460 MODULE_DESCRIPTION("EP93XX GPIO driver");
0461 MODULE_LICENSE("GPL");