drivers/gpio/gpio-em.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Emma Mobile GPIO Support - GIO
0004  *
0005  *  Copyright (C) 2012 Magnus Damm
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/spinlock.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/ioport.h>
0013 #include <linux/io.h>
0014 #include <linux/irq.h>
0015 #include <linux/irqdomain.h>
0016 #include <linux/bitops.h>
0017 #include <linux/err.h>
0018 #include <linux/gpio/driver.h>
0019 #include <linux/slab.h>
0020 #include <linux/module.h>
0021 #include <linux/pinctrl/consumer.h>
0022
0023 struct em_gio_priv {
0024     void __iomem *base0;
0025     void __iomem *base1;
0026     spinlock_t sense_lock;
0027     struct platform_device *pdev;
0028     struct gpio_chip gpio_chip;
0029     struct irq_chip irq_chip;
0030     struct irq_domain *irq_domain;
0031 };
0032
0033 #define GIO_E1 0x00
0034 #define GIO_E0 0x04
0035 #define GIO_EM 0x04
0036 #define GIO_OL 0x08
0037 #define GIO_OH 0x0c
0038 #define GIO_I 0x10
0039 #define GIO_IIA 0x14
0040 #define GIO_IEN 0x18
0041 #define GIO_IDS 0x1c
0042 #define GIO_IIM 0x1c
0043 #define GIO_RAW 0x20
0044 #define GIO_MST 0x24
0045 #define GIO_IIR 0x28
0046
0047 #define GIO_IDT0 0x40
0048 #define GIO_IDT1 0x44
0049 #define GIO_IDT2 0x48
0050 #define GIO_IDT3 0x4c
0051 #define GIO_RAWBL 0x50
0052 #define GIO_RAWBH 0x54
0053 #define GIO_IRBL 0x58
0054 #define GIO_IRBH 0x5c
0055
0056 #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
0057
0058 static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
0059 {
0060     if (offs < GIO_IDT0)
0061         return ioread32(p->base0 + offs);
0062     else
0063         return ioread32(p->base1 + (offs - GIO_IDT0));
0064 }
0065
0066 static inline void em_gio_write(struct em_gio_priv *p, int offs,
0067                 unsigned long value)
0068 {
0069     if (offs < GIO_IDT0)
0070         iowrite32(value, p->base0 + offs);
0071     else
0072         iowrite32(value, p->base1 + (offs - GIO_IDT0));
0073 }
0074
0075 static void em_gio_irq_disable(struct irq_data *d)
0076 {
0077     struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
0078
0079     em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
0080 }
0081
0082 static void em_gio_irq_enable(struct irq_data *d)
0083 {
0084     struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
0085
0086     em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
0087 }
0088
0089 static int em_gio_irq_reqres(struct irq_data *d)
0090 {
0091     struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
0092     int ret;
0093
0094     ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
0095     if (ret) {
0096         dev_err(p->gpio_chip.parent,
0097             "unable to lock HW IRQ %lu for IRQ\n",
0098             irqd_to_hwirq(d));
0099         return ret;
0100     }
0101     return 0;
0102 }
0103
0104 static void em_gio_irq_relres(struct irq_data *d)
0105 {
0106     struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
0107
0108     gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
0109 }
0110
0111
0112 #define GIO_ASYNC(x) (x + 8)
0113
0114 static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
0115     [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
0116     [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
0117     [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
0118     [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
0119     [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
0120 };
0121
0122 static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
0123 {
0124     unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
0125     struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
0126     unsigned int reg, offset, shift;
0127     unsigned long flags;
0128     unsigned long tmp;
0129
0130     if (!value)
0131         return -EINVAL;
0132
0133     offset = irqd_to_hwirq(d);
0134
0135     pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
0136
0137     /* 8 x 4 bit fields in 4 IDT registers */
0138     reg = GIO_IDT(offset >> 3);
0139     shift = (offset & 0x07) << 4;
0140
0141     spin_lock_irqsave(&p->sense_lock, flags);
0142
0143     /* disable the interrupt in IIA */
0144     tmp = em_gio_read(p, GIO_IIA);
0145     tmp &= ~BIT(offset);
0146     em_gio_write(p, GIO_IIA, tmp);
0147
0148     /* change the sense setting in IDT */
0149     tmp = em_gio_read(p, reg);
0150     tmp &= ~(0xf << shift);
0151     tmp |= value << shift;
0152     em_gio_write(p, reg, tmp);
0153
0154     /* clear pending interrupts */
0155     em_gio_write(p, GIO_IIR, BIT(offset));
0156
0157     /* enable the interrupt in IIA */
0158     tmp = em_gio_read(p, GIO_IIA);
0159     tmp |= BIT(offset);
0160     em_gio_write(p, GIO_IIA, tmp);
0161
0162     spin_unlock_irqrestore(&p->sense_lock, flags);
0163
0164     return 0;
0165 }
0166
0167 static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
0168 {
0169     struct em_gio_priv *p = dev_id;
0170     unsigned long pending;
0171     unsigned int offset, irqs_handled = 0;
0172
0173     while ((pending = em_gio_read(p, GIO_MST))) {
0174         offset = __ffs(pending);
0175         em_gio_write(p, GIO_IIR, BIT(offset));
0176         generic_handle_domain_irq(p->irq_domain, offset);
0177         irqs_handled++;
0178     }
0179
0180     return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
0181 }
0182
0183 static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
0184 {
0185     return gpiochip_get_data(chip);
0186 }
0187
0188 static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
0189 {
0190     em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
0191     return 0;
0192 }
0193
0194 static int em_gio_get(struct gpio_chip *chip, unsigned offset)
0195 {
0196     return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
0197 }
0198
0199 static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
0200              unsigned shift, int value)
0201 {
0202     /* upper 16 bits contains mask and lower 16 actual value */
0203     em_gio_write(gpio_to_priv(chip), reg,
0204              (BIT(shift + 16)) | (value << shift));
0205 }
0206
0207 static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
0208 {
0209     /* output is split into two registers */
0210     if (offset < 16)
0211         __em_gio_set(chip, GIO_OL, offset, value);
0212     else
0213         __em_gio_set(chip, GIO_OH, offset - 16, value);
0214 }
0215
0216 static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
0217                    int value)
0218 {
0219     /* write GPIO value to output before selecting output mode of pin */
0220     em_gio_set(chip, offset, value);
0221     em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
0222     return 0;
0223 }
0224
0225 static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
0226 {
0227     return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
0228 }
0229
0230 static int em_gio_request(struct gpio_chip *chip, unsigned offset)
0231 {
0232     return pinctrl_gpio_request(chip->base + offset);
0233 }
0234
0235 static void em_gio_free(struct gpio_chip *chip, unsigned offset)
0236 {
0237     pinctrl_gpio_free(chip->base + offset);
0238
0239     /* Set the GPIO as an input to ensure that the next GPIO request won't
0240     * drive the GPIO pin as an output.
0241     */
0242     em_gio_direction_input(chip, offset);
0243 }
0244
0245 static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
0246                  irq_hw_number_t hwirq)
0247 {
0248     struct em_gio_priv *p = h->host_data;
0249
0250     pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
0251
0252     irq_set_chip_data(irq, h->host_data);
0253     irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
0254     return 0;
0255 }
0256
0257 static const struct irq_domain_ops em_gio_irq_domain_ops = {
0258     .map    = em_gio_irq_domain_map,
0259     .xlate  = irq_domain_xlate_twocell,
0260 };
0261
0262 static void em_gio_irq_domain_remove(void *data)
0263 {
0264     struct irq_domain *domain = data;
0265
0266     irq_domain_remove(domain);
0267 }
0268
0269 static int em_gio_probe(struct platform_device *pdev)
0270 {
0271     struct em_gio_priv *p;
0272     struct gpio_chip *gpio_chip;
0273     struct irq_chip *irq_chip;
0274     struct device *dev = &pdev->dev;
0275     const char *name = dev_name(dev);
0276     unsigned int ngpios;
0277     int irq[2], ret;
0278
0279     p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
0280     if (!p)
0281         return -ENOMEM;
0282
0283     p->pdev = pdev;
0284     platform_set_drvdata(pdev, p);
0285     spin_lock_init(&p->sense_lock);
0286
0287     irq[0] = platform_get_irq(pdev, 0);
0288     if (irq[0] < 0)
0289         return irq[0];
0290
0291     irq[1] = platform_get_irq(pdev, 1);
0292     if (irq[1] < 0)
0293         return irq[1];
0294
0295     p->base0 = devm_platform_ioremap_resource(pdev, 0);
0296     if (IS_ERR(p->base0))
0297         return PTR_ERR(p->base0);
0298
0299     p->base1 = devm_platform_ioremap_resource(pdev, 1);
0300     if (IS_ERR(p->base1))
0301         return PTR_ERR(p->base1);
0302
0303     if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
0304         dev_err(dev, "Missing ngpios OF property\n");
0305         return -EINVAL;
0306     }
0307
0308     gpio_chip = &p->gpio_chip;
0309     gpio_chip->direction_input = em_gio_direction_input;
0310     gpio_chip->get = em_gio_get;
0311     gpio_chip->direction_output = em_gio_direction_output;
0312     gpio_chip->set = em_gio_set;
0313     gpio_chip->to_irq = em_gio_to_irq;
0314     gpio_chip->request = em_gio_request;
0315     gpio_chip->free = em_gio_free;
0316     gpio_chip->label = name;
0317     gpio_chip->parent = dev;
0318     gpio_chip->owner = THIS_MODULE;
0319     gpio_chip->base = -1;
0320     gpio_chip->ngpio = ngpios;
0321
0322     irq_chip = &p->irq_chip;
0323     irq_chip->name = "gpio-em";
0324     irq_chip->irq_mask = em_gio_irq_disable;
0325     irq_chip->irq_unmask = em_gio_irq_enable;
0326     irq_chip->irq_set_type = em_gio_irq_set_type;
0327     irq_chip->irq_request_resources = em_gio_irq_reqres;
0328     irq_chip->irq_release_resources = em_gio_irq_relres;
0329     irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
0330
0331     p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
0332                           &em_gio_irq_domain_ops, p);
0333     if (!p->irq_domain) {
0334         dev_err(dev, "cannot initialize irq domain\n");
0335         return -ENXIO;
0336     }
0337
0338     ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
0339                        p->irq_domain);
0340     if (ret)
0341         return ret;
0342
0343     if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
0344         dev_err(dev, "failed to request low IRQ\n");
0345         return -ENOENT;
0346     }
0347
0348     if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
0349         dev_err(dev, "failed to request high IRQ\n");
0350         return -ENOENT;
0351     }
0352
0353     ret = devm_gpiochip_add_data(dev, gpio_chip, p);
0354     if (ret) {
0355         dev_err(dev, "failed to add GPIO controller\n");
0356         return ret;
0357     }
0358
0359     return 0;
0360 }
0361
0362 static const struct of_device_id em_gio_dt_ids[] = {
0363     { .compatible = "renesas,em-gio", },
0364     {},
0365 };
0366 MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
0367
0368 static struct platform_driver em_gio_device_driver = {
0369     .probe      = em_gio_probe,
0370     .driver     = {
0371         .name   = "em_gio",
0372         .of_match_table = em_gio_dt_ids,
0373     }
0374 };
0375
0376 static int __init em_gio_init(void)
0377 {
0378     return platform_driver_register(&em_gio_device_driver);
0379 }
0380 postcore_initcall(em_gio_init);
0381
0382 static void __exit em_gio_exit(void)
0383 {
0384     platform_driver_unregister(&em_gio_device_driver);
0385 }
0386 module_exit(em_gio_exit);
0387
0388 MODULE_AUTHOR("Magnus Damm");
0389 MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
0390 MODULE_LICENSE("GPL v2");