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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 Spreadtrum Communications Inc.
0004  * Copyright (C) 2018 Linaro Ltd.
0005  */
0006 
0007 #include <linux/bitops.h>
0008 #include <linux/gpio/driver.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/spinlock.h>
0015 
0016 /* EIC registers definition */
0017 #define SPRD_EIC_DBNC_DATA      0x0
0018 #define SPRD_EIC_DBNC_DMSK      0x4
0019 #define SPRD_EIC_DBNC_IEV       0x14
0020 #define SPRD_EIC_DBNC_IE        0x18
0021 #define SPRD_EIC_DBNC_RIS       0x1c
0022 #define SPRD_EIC_DBNC_MIS       0x20
0023 #define SPRD_EIC_DBNC_IC        0x24
0024 #define SPRD_EIC_DBNC_TRIG      0x28
0025 #define SPRD_EIC_DBNC_CTRL0     0x40
0026 
0027 #define SPRD_EIC_LATCH_INTEN        0x0
0028 #define SPRD_EIC_LATCH_INTRAW       0x4
0029 #define SPRD_EIC_LATCH_INTMSK       0x8
0030 #define SPRD_EIC_LATCH_INTCLR       0xc
0031 #define SPRD_EIC_LATCH_INTPOL       0x10
0032 #define SPRD_EIC_LATCH_INTMODE      0x14
0033 
0034 #define SPRD_EIC_ASYNC_INTIE        0x0
0035 #define SPRD_EIC_ASYNC_INTRAW       0x4
0036 #define SPRD_EIC_ASYNC_INTMSK       0x8
0037 #define SPRD_EIC_ASYNC_INTCLR       0xc
0038 #define SPRD_EIC_ASYNC_INTMODE      0x10
0039 #define SPRD_EIC_ASYNC_INTBOTH      0x14
0040 #define SPRD_EIC_ASYNC_INTPOL       0x18
0041 #define SPRD_EIC_ASYNC_DATA     0x1c
0042 
0043 #define SPRD_EIC_SYNC_INTIE     0x0
0044 #define SPRD_EIC_SYNC_INTRAW        0x4
0045 #define SPRD_EIC_SYNC_INTMSK        0x8
0046 #define SPRD_EIC_SYNC_INTCLR        0xc
0047 #define SPRD_EIC_SYNC_INTMODE       0x10
0048 #define SPRD_EIC_SYNC_INTBOTH       0x14
0049 #define SPRD_EIC_SYNC_INTPOL        0x18
0050 #define SPRD_EIC_SYNC_DATA      0x1c
0051 
0052 /*
0053  * The digital-chip EIC controller can support maximum 3 banks, and each bank
0054  * contains 8 EICs.
0055  */
0056 #define SPRD_EIC_MAX_BANK       3
0057 #define SPRD_EIC_PER_BANK_NR        8
0058 #define SPRD_EIC_DATA_MASK      GENMASK(7, 0)
0059 #define SPRD_EIC_BIT(x)         ((x) & (SPRD_EIC_PER_BANK_NR - 1))
0060 #define SPRD_EIC_DBNC_MASK      GENMASK(11, 0)
0061 
0062 /*
0063  * The Spreadtrum EIC (external interrupt controller) can be used only in
0064  * input mode to generate interrupts if detecting input signals.
0065  *
0066  * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
0067  * debounce EIC, latch EIC, async EIC and sync EIC,
0068  *
0069  * The debounce EIC is used to capture the input signals' stable status
0070  * (millisecond resolution) and a single-trigger mechanism is introduced
0071  * into this sub-module to enhance the input event detection reliability.
0072  * The debounce range is from 1ms to 4s with a step size of 1ms.
0073  *
0074  * The latch EIC is used to latch some special power down signals and
0075  * generate interrupts, since the latch EIC does not depend on the APB clock
0076  * to capture signals.
0077  *
0078  * The async EIC uses a 32k clock to capture the short signals (microsecond
0079  * resolution) to generate interrupts by level or edge trigger.
0080  *
0081  * The EIC-sync is similar with GPIO's input function, which is a synchronized
0082  * signal input register.
0083  */
0084 enum sprd_eic_type {
0085     SPRD_EIC_DEBOUNCE,
0086     SPRD_EIC_LATCH,
0087     SPRD_EIC_ASYNC,
0088     SPRD_EIC_SYNC,
0089     SPRD_EIC_MAX,
0090 };
0091 
0092 struct sprd_eic {
0093     struct gpio_chip chip;
0094     struct irq_chip intc;
0095     void __iomem *base[SPRD_EIC_MAX_BANK];
0096     enum sprd_eic_type type;
0097     spinlock_t lock;
0098     int irq;
0099 };
0100 
0101 struct sprd_eic_variant_data {
0102     enum sprd_eic_type type;
0103     u32 num_eics;
0104 };
0105 
0106 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
0107     "eic-debounce", "eic-latch", "eic-async",
0108     "eic-sync",
0109 };
0110 
0111 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
0112     .type = SPRD_EIC_DEBOUNCE,
0113     .num_eics = 8,
0114 };
0115 
0116 static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
0117     .type = SPRD_EIC_LATCH,
0118     .num_eics = 8,
0119 };
0120 
0121 static const struct sprd_eic_variant_data sc9860_eic_async_data = {
0122     .type = SPRD_EIC_ASYNC,
0123     .num_eics = 8,
0124 };
0125 
0126 static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
0127     .type = SPRD_EIC_SYNC,
0128     .num_eics = 8,
0129 };
0130 
0131 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
0132                          unsigned int bank)
0133 {
0134     if (bank >= SPRD_EIC_MAX_BANK)
0135         return NULL;
0136 
0137     return sprd_eic->base[bank];
0138 }
0139 
0140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
0141                 u16 reg, unsigned int val)
0142 {
0143     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0144     void __iomem *base =
0145         sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
0146     unsigned long flags;
0147     u32 tmp;
0148 
0149     spin_lock_irqsave(&sprd_eic->lock, flags);
0150     tmp = readl_relaxed(base + reg);
0151 
0152     if (val)
0153         tmp |= BIT(SPRD_EIC_BIT(offset));
0154     else
0155         tmp &= ~BIT(SPRD_EIC_BIT(offset));
0156 
0157     writel_relaxed(tmp, base + reg);
0158     spin_unlock_irqrestore(&sprd_eic->lock, flags);
0159 }
0160 
0161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
0162 {
0163     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0164     void __iomem *base =
0165         sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
0166 
0167     return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
0168 }
0169 
0170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
0171 {
0172     sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
0173     return 0;
0174 }
0175 
0176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
0177 {
0178     sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
0179 }
0180 
0181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
0182 {
0183     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0184 
0185     switch (sprd_eic->type) {
0186     case SPRD_EIC_DEBOUNCE:
0187         return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
0188     case SPRD_EIC_ASYNC:
0189         return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
0190     case SPRD_EIC_SYNC:
0191         return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
0192     default:
0193         return -ENOTSUPP;
0194     }
0195 }
0196 
0197 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
0198 {
0199     /* EICs are always input, nothing need to do here. */
0200     return 0;
0201 }
0202 
0203 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
0204 {
0205     /* EICs are always input, nothing need to do here. */
0206 }
0207 
0208 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
0209                  unsigned int debounce)
0210 {
0211     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0212     void __iomem *base =
0213         sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
0214     u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
0215     u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
0216 
0217     value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
0218     writel_relaxed(value, base + reg);
0219 
0220     return 0;
0221 }
0222 
0223 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
0224                    unsigned long config)
0225 {
0226     unsigned long param = pinconf_to_config_param(config);
0227     u32 arg = pinconf_to_config_argument(config);
0228 
0229     if (param == PIN_CONFIG_INPUT_DEBOUNCE)
0230         return sprd_eic_set_debounce(chip, offset, arg);
0231 
0232     return -ENOTSUPP;
0233 }
0234 
0235 static void sprd_eic_irq_mask(struct irq_data *data)
0236 {
0237     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0238     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0239     u32 offset = irqd_to_hwirq(data);
0240 
0241     switch (sprd_eic->type) {
0242     case SPRD_EIC_DEBOUNCE:
0243         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
0244         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
0245         break;
0246     case SPRD_EIC_LATCH:
0247         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
0248         break;
0249     case SPRD_EIC_ASYNC:
0250         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
0251         break;
0252     case SPRD_EIC_SYNC:
0253         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
0254         break;
0255     default:
0256         dev_err(chip->parent, "Unsupported EIC type.\n");
0257     }
0258 }
0259 
0260 static void sprd_eic_irq_unmask(struct irq_data *data)
0261 {
0262     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0263     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0264     u32 offset = irqd_to_hwirq(data);
0265 
0266     switch (sprd_eic->type) {
0267     case SPRD_EIC_DEBOUNCE:
0268         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
0269         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
0270         break;
0271     case SPRD_EIC_LATCH:
0272         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
0273         break;
0274     case SPRD_EIC_ASYNC:
0275         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
0276         break;
0277     case SPRD_EIC_SYNC:
0278         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
0279         break;
0280     default:
0281         dev_err(chip->parent, "Unsupported EIC type.\n");
0282     }
0283 }
0284 
0285 static void sprd_eic_irq_ack(struct irq_data *data)
0286 {
0287     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0288     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0289     u32 offset = irqd_to_hwirq(data);
0290 
0291     switch (sprd_eic->type) {
0292     case SPRD_EIC_DEBOUNCE:
0293         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
0294         break;
0295     case SPRD_EIC_LATCH:
0296         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
0297         break;
0298     case SPRD_EIC_ASYNC:
0299         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
0300         break;
0301     case SPRD_EIC_SYNC:
0302         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
0303         break;
0304     default:
0305         dev_err(chip->parent, "Unsupported EIC type.\n");
0306     }
0307 }
0308 
0309 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
0310 {
0311     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0312     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0313     u32 offset = irqd_to_hwirq(data);
0314     int state;
0315 
0316     switch (sprd_eic->type) {
0317     case SPRD_EIC_DEBOUNCE:
0318         switch (flow_type) {
0319         case IRQ_TYPE_LEVEL_HIGH:
0320             sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
0321             break;
0322         case IRQ_TYPE_LEVEL_LOW:
0323             sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
0324             break;
0325         case IRQ_TYPE_EDGE_RISING:
0326         case IRQ_TYPE_EDGE_FALLING:
0327         case IRQ_TYPE_EDGE_BOTH:
0328             state = sprd_eic_get(chip, offset);
0329             if (state)
0330                 sprd_eic_update(chip, offset,
0331                         SPRD_EIC_DBNC_IEV, 0);
0332             else
0333                 sprd_eic_update(chip, offset,
0334                         SPRD_EIC_DBNC_IEV, 1);
0335             break;
0336         default:
0337             return -ENOTSUPP;
0338         }
0339 
0340         irq_set_handler_locked(data, handle_level_irq);
0341         break;
0342     case SPRD_EIC_LATCH:
0343         switch (flow_type) {
0344         case IRQ_TYPE_LEVEL_HIGH:
0345             sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
0346             break;
0347         case IRQ_TYPE_LEVEL_LOW:
0348             sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
0349             break;
0350         case IRQ_TYPE_EDGE_RISING:
0351         case IRQ_TYPE_EDGE_FALLING:
0352         case IRQ_TYPE_EDGE_BOTH:
0353             state = sprd_eic_get(chip, offset);
0354             if (state)
0355                 sprd_eic_update(chip, offset,
0356                         SPRD_EIC_LATCH_INTPOL, 0);
0357             else
0358                 sprd_eic_update(chip, offset,
0359                         SPRD_EIC_LATCH_INTPOL, 1);
0360             break;
0361         default:
0362             return -ENOTSUPP;
0363         }
0364 
0365         irq_set_handler_locked(data, handle_level_irq);
0366         break;
0367     case SPRD_EIC_ASYNC:
0368         switch (flow_type) {
0369         case IRQ_TYPE_EDGE_RISING:
0370             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
0371             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
0372             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
0373             irq_set_handler_locked(data, handle_edge_irq);
0374             break;
0375         case IRQ_TYPE_EDGE_FALLING:
0376             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
0377             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
0378             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
0379             irq_set_handler_locked(data, handle_edge_irq);
0380             break;
0381         case IRQ_TYPE_EDGE_BOTH:
0382             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
0383             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
0384             irq_set_handler_locked(data, handle_edge_irq);
0385             break;
0386         case IRQ_TYPE_LEVEL_HIGH:
0387             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
0388             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
0389             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
0390             irq_set_handler_locked(data, handle_level_irq);
0391             break;
0392         case IRQ_TYPE_LEVEL_LOW:
0393             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
0394             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
0395             sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
0396             irq_set_handler_locked(data, handle_level_irq);
0397             break;
0398         default:
0399             return -ENOTSUPP;
0400         }
0401         break;
0402     case SPRD_EIC_SYNC:
0403         switch (flow_type) {
0404         case IRQ_TYPE_EDGE_RISING:
0405             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
0406             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
0407             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
0408             irq_set_handler_locked(data, handle_edge_irq);
0409             break;
0410         case IRQ_TYPE_EDGE_FALLING:
0411             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
0412             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
0413             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
0414             irq_set_handler_locked(data, handle_edge_irq);
0415             break;
0416         case IRQ_TYPE_EDGE_BOTH:
0417             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
0418             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
0419             irq_set_handler_locked(data, handle_edge_irq);
0420             break;
0421         case IRQ_TYPE_LEVEL_HIGH:
0422             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
0423             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
0424             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
0425             irq_set_handler_locked(data, handle_level_irq);
0426             break;
0427         case IRQ_TYPE_LEVEL_LOW:
0428             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
0429             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
0430             sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
0431             irq_set_handler_locked(data, handle_level_irq);
0432             break;
0433         default:
0434             return -ENOTSUPP;
0435         }
0436         break;
0437     default:
0438         dev_err(chip->parent, "Unsupported EIC type.\n");
0439         return -ENOTSUPP;
0440     }
0441 
0442     return 0;
0443 }
0444 
0445 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
0446                     unsigned int offset)
0447 {
0448     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0449     struct irq_data *data = irq_get_irq_data(irq);
0450     u32 trigger = irqd_get_trigger_type(data);
0451     int state, post_state;
0452 
0453     /*
0454      * The debounce EIC and latch EIC can only support level trigger, so we
0455      * can toggle the level trigger to emulate the edge trigger.
0456      */
0457     if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
0458          sprd_eic->type != SPRD_EIC_LATCH) ||
0459         !(trigger & IRQ_TYPE_EDGE_BOTH))
0460         return;
0461 
0462     sprd_eic_irq_mask(data);
0463     state = sprd_eic_get(chip, offset);
0464 
0465 retry:
0466     switch (sprd_eic->type) {
0467     case SPRD_EIC_DEBOUNCE:
0468         if (state)
0469             sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
0470         else
0471             sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
0472         break;
0473     case SPRD_EIC_LATCH:
0474         if (state)
0475             sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
0476         else
0477             sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
0478         break;
0479     default:
0480         sprd_eic_irq_unmask(data);
0481         return;
0482     }
0483 
0484     post_state = sprd_eic_get(chip, offset);
0485     if (state != post_state) {
0486         dev_warn(chip->parent, "EIC level was changed.\n");
0487         state = post_state;
0488         goto retry;
0489     }
0490 
0491     sprd_eic_irq_unmask(data);
0492 }
0493 
0494 static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
0495 {
0496     enum sprd_eic_type type = *(enum sprd_eic_type *)data;
0497 
0498     return !strcmp(chip->label, sprd_eic_label_name[type]);
0499 }
0500 
0501 static void sprd_eic_handle_one_type(struct gpio_chip *chip)
0502 {
0503     struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
0504     u32 bank, n, girq;
0505 
0506     for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
0507         void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
0508         unsigned long reg;
0509 
0510         switch (sprd_eic->type) {
0511         case SPRD_EIC_DEBOUNCE:
0512             reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
0513                 SPRD_EIC_DATA_MASK;
0514             break;
0515         case SPRD_EIC_LATCH:
0516             reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
0517                 SPRD_EIC_DATA_MASK;
0518             break;
0519         case SPRD_EIC_ASYNC:
0520             reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
0521                 SPRD_EIC_DATA_MASK;
0522             break;
0523         case SPRD_EIC_SYNC:
0524             reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
0525                 SPRD_EIC_DATA_MASK;
0526             break;
0527         default:
0528             dev_err(chip->parent, "Unsupported EIC type.\n");
0529             return;
0530         }
0531 
0532         for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
0533             u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
0534 
0535             girq = irq_find_mapping(chip->irq.domain, offset);
0536 
0537             generic_handle_irq(girq);
0538             sprd_eic_toggle_trigger(chip, girq, offset);
0539         }
0540     }
0541 }
0542 
0543 static void sprd_eic_irq_handler(struct irq_desc *desc)
0544 {
0545     struct irq_chip *ic = irq_desc_get_chip(desc);
0546     struct gpio_chip *chip;
0547     enum sprd_eic_type type;
0548 
0549     chained_irq_enter(ic, desc);
0550 
0551     /*
0552      * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
0553      * and sync) share one same interrupt line, we should iterate each
0554      * EIC module to check if there are EIC interrupts were triggered.
0555      */
0556     for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
0557         chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
0558         if (!chip)
0559             continue;
0560 
0561         sprd_eic_handle_one_type(chip);
0562     }
0563 
0564     chained_irq_exit(ic, desc);
0565 }
0566 
0567 static int sprd_eic_probe(struct platform_device *pdev)
0568 {
0569     const struct sprd_eic_variant_data *pdata;
0570     struct gpio_irq_chip *irq;
0571     struct sprd_eic *sprd_eic;
0572     struct resource *res;
0573     int ret, i;
0574 
0575     pdata = of_device_get_match_data(&pdev->dev);
0576     if (!pdata) {
0577         dev_err(&pdev->dev, "No matching driver data found.\n");
0578         return -EINVAL;
0579     }
0580 
0581     sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
0582     if (!sprd_eic)
0583         return -ENOMEM;
0584 
0585     spin_lock_init(&sprd_eic->lock);
0586     sprd_eic->type = pdata->type;
0587 
0588     sprd_eic->irq = platform_get_irq(pdev, 0);
0589     if (sprd_eic->irq < 0)
0590         return sprd_eic->irq;
0591 
0592     for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
0593         /*
0594          * We can have maximum 3 banks EICs, and each EIC has
0595          * its own base address. But some platform maybe only
0596          * have one bank EIC, thus base[1] and base[2] can be
0597          * optional.
0598          */
0599         res = platform_get_resource(pdev, IORESOURCE_MEM, i);
0600         if (!res)
0601             break;
0602 
0603         sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
0604         if (IS_ERR(sprd_eic->base[i]))
0605             return PTR_ERR(sprd_eic->base[i]);
0606     }
0607 
0608     sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
0609     sprd_eic->chip.ngpio = pdata->num_eics;
0610     sprd_eic->chip.base = -1;
0611     sprd_eic->chip.parent = &pdev->dev;
0612     sprd_eic->chip.direction_input = sprd_eic_direction_input;
0613     switch (sprd_eic->type) {
0614     case SPRD_EIC_DEBOUNCE:
0615         sprd_eic->chip.request = sprd_eic_request;
0616         sprd_eic->chip.free = sprd_eic_free;
0617         sprd_eic->chip.set_config = sprd_eic_set_config;
0618         sprd_eic->chip.set = sprd_eic_set;
0619         fallthrough;
0620     case SPRD_EIC_ASYNC:
0621     case SPRD_EIC_SYNC:
0622         sprd_eic->chip.get = sprd_eic_get;
0623         break;
0624     case SPRD_EIC_LATCH:
0625     default:
0626         break;
0627     }
0628 
0629     sprd_eic->intc.name = dev_name(&pdev->dev);
0630     sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
0631     sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
0632     sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
0633     sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
0634     sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
0635 
0636     irq = &sprd_eic->chip.irq;
0637     irq->chip = &sprd_eic->intc;
0638     irq->handler = handle_bad_irq;
0639     irq->default_type = IRQ_TYPE_NONE;
0640     irq->parent_handler = sprd_eic_irq_handler;
0641     irq->parent_handler_data = sprd_eic;
0642     irq->num_parents = 1;
0643     irq->parents = &sprd_eic->irq;
0644 
0645     ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
0646     if (ret < 0) {
0647         dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
0648         return ret;
0649     }
0650 
0651     platform_set_drvdata(pdev, sprd_eic);
0652     return 0;
0653 }
0654 
0655 static const struct of_device_id sprd_eic_of_match[] = {
0656     {
0657         .compatible = "sprd,sc9860-eic-debounce",
0658         .data = &sc9860_eic_dbnc_data,
0659     },
0660     {
0661         .compatible = "sprd,sc9860-eic-latch",
0662         .data = &sc9860_eic_latch_data,
0663     },
0664     {
0665         .compatible = "sprd,sc9860-eic-async",
0666         .data = &sc9860_eic_async_data,
0667     },
0668     {
0669         .compatible = "sprd,sc9860-eic-sync",
0670         .data = &sc9860_eic_sync_data,
0671     },
0672     {
0673         /* end of list */
0674     }
0675 };
0676 MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
0677 
0678 static struct platform_driver sprd_eic_driver = {
0679     .probe = sprd_eic_probe,
0680     .driver = {
0681         .name = "sprd-eic",
0682         .of_match_table = sprd_eic_of_match,
0683     },
0684 };
0685 
0686 module_platform_driver(sprd_eic_driver);
0687 
0688 MODULE_DESCRIPTION("Spreadtrum EIC driver");
0689 MODULE_LICENSE("GPL v2");
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