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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2011 Jamie Iles
0004  *
0005  * All enquiries to support@picochip.com
0006  */
0007 #include <linux/acpi.h>
0008 #include <linux/clk.h>
0009 #include <linux/err.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/io.h>
0014 #include <linux/ioport.h>
0015 #include <linux/irq.h>
0016 #include <linux/mod_devicetable.h>
0017 #include <linux/module.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/property.h>
0020 #include <linux/reset.h>
0021 #include <linux/slab.h>
0022 #include <linux/spinlock.h>
0023 
0024 #include "gpiolib.h"
0025 #include "gpiolib-acpi.h"
0026 
0027 #define GPIO_SWPORTA_DR     0x00
0028 #define GPIO_SWPORTA_DDR    0x04
0029 #define GPIO_SWPORTB_DR     0x0c
0030 #define GPIO_SWPORTB_DDR    0x10
0031 #define GPIO_SWPORTC_DR     0x18
0032 #define GPIO_SWPORTC_DDR    0x1c
0033 #define GPIO_SWPORTD_DR     0x24
0034 #define GPIO_SWPORTD_DDR    0x28
0035 #define GPIO_INTEN      0x30
0036 #define GPIO_INTMASK        0x34
0037 #define GPIO_INTTYPE_LEVEL  0x38
0038 #define GPIO_INT_POLARITY   0x3c
0039 #define GPIO_INTSTATUS      0x40
0040 #define GPIO_PORTA_DEBOUNCE 0x48
0041 #define GPIO_PORTA_EOI      0x4c
0042 #define GPIO_EXT_PORTA      0x50
0043 #define GPIO_EXT_PORTB      0x54
0044 #define GPIO_EXT_PORTC      0x58
0045 #define GPIO_EXT_PORTD      0x5c
0046 
0047 #define DWAPB_DRIVER_NAME   "gpio-dwapb"
0048 #define DWAPB_MAX_PORTS     4
0049 #define DWAPB_MAX_GPIOS     32
0050 
0051 #define GPIO_EXT_PORT_STRIDE    0x04 /* register stride 32 bits */
0052 #define GPIO_SWPORT_DR_STRIDE   0x0c /* register stride 3*32 bits */
0053 #define GPIO_SWPORT_DDR_STRIDE  0x0c /* register stride 3*32 bits */
0054 
0055 #define GPIO_REG_OFFSET_V1  0
0056 #define GPIO_REG_OFFSET_V2  1
0057 #define GPIO_REG_OFFSET_MASK    BIT(0)
0058 
0059 #define GPIO_INTMASK_V2     0x44
0060 #define GPIO_INTTYPE_LEVEL_V2   0x34
0061 #define GPIO_INT_POLARITY_V2    0x38
0062 #define GPIO_INTSTATUS_V2   0x3c
0063 #define GPIO_PORTA_EOI_V2   0x40
0064 
0065 #define DWAPB_NR_CLOCKS     2
0066 
0067 struct dwapb_gpio;
0068 
0069 struct dwapb_port_property {
0070     struct fwnode_handle *fwnode;
0071     unsigned int idx;
0072     unsigned int ngpio;
0073     unsigned int gpio_base;
0074     int irq[DWAPB_MAX_GPIOS];
0075 };
0076 
0077 struct dwapb_platform_data {
0078     struct dwapb_port_property *properties;
0079     unsigned int nports;
0080 };
0081 
0082 #ifdef CONFIG_PM_SLEEP
0083 /* Store GPIO context across system-wide suspend/resume transitions */
0084 struct dwapb_context {
0085     u32 data;
0086     u32 dir;
0087     u32 ext;
0088     u32 int_en;
0089     u32 int_mask;
0090     u32 int_type;
0091     u32 int_pol;
0092     u32 int_deb;
0093     u32 wake_en;
0094 };
0095 #endif
0096 
0097 struct dwapb_gpio_port_irqchip {
0098     unsigned int        nr_irqs;
0099     unsigned int        irq[DWAPB_MAX_GPIOS];
0100 };
0101 
0102 struct dwapb_gpio_port {
0103     struct gpio_chip    gc;
0104     struct dwapb_gpio_port_irqchip *pirq;
0105     struct dwapb_gpio   *gpio;
0106 #ifdef CONFIG_PM_SLEEP
0107     struct dwapb_context    *ctx;
0108 #endif
0109     unsigned int        idx;
0110 };
0111 #define to_dwapb_gpio(_gc) \
0112     (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
0113 
0114 struct dwapb_gpio {
0115     struct  device      *dev;
0116     void __iomem        *regs;
0117     struct dwapb_gpio_port  *ports;
0118     unsigned int        nr_ports;
0119     unsigned int        flags;
0120     struct reset_control    *rst;
0121     struct clk_bulk_data    clks[DWAPB_NR_CLOCKS];
0122 };
0123 
0124 static inline u32 gpio_reg_v2_convert(unsigned int offset)
0125 {
0126     switch (offset) {
0127     case GPIO_INTMASK:
0128         return GPIO_INTMASK_V2;
0129     case GPIO_INTTYPE_LEVEL:
0130         return GPIO_INTTYPE_LEVEL_V2;
0131     case GPIO_INT_POLARITY:
0132         return GPIO_INT_POLARITY_V2;
0133     case GPIO_INTSTATUS:
0134         return GPIO_INTSTATUS_V2;
0135     case GPIO_PORTA_EOI:
0136         return GPIO_PORTA_EOI_V2;
0137     }
0138 
0139     return offset;
0140 }
0141 
0142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
0143 {
0144     if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
0145         return gpio_reg_v2_convert(offset);
0146 
0147     return offset;
0148 }
0149 
0150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
0151 {
0152     struct gpio_chip *gc    = &gpio->ports[0].gc;
0153     void __iomem *reg_base  = gpio->regs;
0154 
0155     return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
0156 }
0157 
0158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
0159                    u32 val)
0160 {
0161     struct gpio_chip *gc    = &gpio->ports[0].gc;
0162     void __iomem *reg_base  = gpio->regs;
0163 
0164     gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
0165 }
0166 
0167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
0168 {
0169     struct dwapb_gpio_port *port;
0170     int i;
0171 
0172     for (i = 0; i < gpio->nr_ports; i++) {
0173         port = &gpio->ports[i];
0174         if (port->idx == offs / DWAPB_MAX_GPIOS)
0175             return port;
0176     }
0177 
0178     return NULL;
0179 }
0180 
0181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
0182 {
0183     struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
0184     struct gpio_chip *gc;
0185     u32 pol;
0186     int val;
0187 
0188     if (!port)
0189         return;
0190     gc = &port->gc;
0191 
0192     pol = dwapb_read(gpio, GPIO_INT_POLARITY);
0193     /* Just read the current value right out of the data register */
0194     val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
0195     if (val)
0196         pol &= ~BIT(offs);
0197     else
0198         pol |= BIT(offs);
0199 
0200     dwapb_write(gpio, GPIO_INT_POLARITY, pol);
0201 }
0202 
0203 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
0204 {
0205     struct gpio_chip *gc = &gpio->ports[0].gc;
0206     unsigned long irq_status;
0207     irq_hw_number_t hwirq;
0208 
0209     irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
0210     for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
0211         int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
0212         u32 irq_type = irq_get_trigger_type(gpio_irq);
0213 
0214         generic_handle_irq(gpio_irq);
0215 
0216         if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
0217             dwapb_toggle_trigger(gpio, hwirq);
0218     }
0219 
0220     return irq_status;
0221 }
0222 
0223 static void dwapb_irq_handler(struct irq_desc *desc)
0224 {
0225     struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
0226     struct irq_chip *chip = irq_desc_get_chip(desc);
0227 
0228     chained_irq_enter(chip, desc);
0229     dwapb_do_irq(gpio);
0230     chained_irq_exit(chip, desc);
0231 }
0232 
0233 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
0234 {
0235     return IRQ_RETVAL(dwapb_do_irq(dev_id));
0236 }
0237 
0238 static void dwapb_irq_ack(struct irq_data *d)
0239 {
0240     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0241     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0242     u32 val = BIT(irqd_to_hwirq(d));
0243     unsigned long flags;
0244 
0245     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0246     dwapb_write(gpio, GPIO_PORTA_EOI, val);
0247     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0248 }
0249 
0250 static void dwapb_irq_mask(struct irq_data *d)
0251 {
0252     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0253     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0254     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0255     unsigned long flags;
0256     u32 val;
0257 
0258     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0259     val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
0260     dwapb_write(gpio, GPIO_INTMASK, val);
0261     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0262 
0263     gpiochip_disable_irq(gc, hwirq);
0264 }
0265 
0266 static void dwapb_irq_unmask(struct irq_data *d)
0267 {
0268     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0269     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0270     irq_hw_number_t hwirq = irqd_to_hwirq(d);
0271     unsigned long flags;
0272     u32 val;
0273 
0274     gpiochip_enable_irq(gc, hwirq);
0275 
0276     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0277     val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
0278     dwapb_write(gpio, GPIO_INTMASK, val);
0279     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0280 }
0281 
0282 static void dwapb_irq_enable(struct irq_data *d)
0283 {
0284     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0285     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0286     unsigned long flags;
0287     u32 val;
0288 
0289     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0290     val = dwapb_read(gpio, GPIO_INTEN);
0291     val |= BIT(irqd_to_hwirq(d));
0292     dwapb_write(gpio, GPIO_INTEN, val);
0293     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0294 }
0295 
0296 static void dwapb_irq_disable(struct irq_data *d)
0297 {
0298     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0299     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0300     unsigned long flags;
0301     u32 val;
0302 
0303     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0304     val = dwapb_read(gpio, GPIO_INTEN);
0305     val &= ~BIT(irqd_to_hwirq(d));
0306     dwapb_write(gpio, GPIO_INTEN, val);
0307     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0308 }
0309 
0310 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
0311 {
0312     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0313     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0314     irq_hw_number_t bit = irqd_to_hwirq(d);
0315     unsigned long level, polarity, flags;
0316 
0317     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0318     level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
0319     polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
0320 
0321     switch (type) {
0322     case IRQ_TYPE_EDGE_BOTH:
0323         level |= BIT(bit);
0324         dwapb_toggle_trigger(gpio, bit);
0325         break;
0326     case IRQ_TYPE_EDGE_RISING:
0327         level |= BIT(bit);
0328         polarity |= BIT(bit);
0329         break;
0330     case IRQ_TYPE_EDGE_FALLING:
0331         level |= BIT(bit);
0332         polarity &= ~BIT(bit);
0333         break;
0334     case IRQ_TYPE_LEVEL_HIGH:
0335         level &= ~BIT(bit);
0336         polarity |= BIT(bit);
0337         break;
0338     case IRQ_TYPE_LEVEL_LOW:
0339         level &= ~BIT(bit);
0340         polarity &= ~BIT(bit);
0341         break;
0342     }
0343 
0344     if (type & IRQ_TYPE_LEVEL_MASK)
0345         irq_set_handler_locked(d, handle_level_irq);
0346     else if (type & IRQ_TYPE_EDGE_BOTH)
0347         irq_set_handler_locked(d, handle_edge_irq);
0348 
0349     dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
0350     if (type != IRQ_TYPE_EDGE_BOTH)
0351         dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
0352     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0353 
0354     return 0;
0355 }
0356 
0357 #ifdef CONFIG_PM_SLEEP
0358 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
0359 {
0360     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0361     struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
0362     struct dwapb_context *ctx = gpio->ports[0].ctx;
0363     irq_hw_number_t bit = irqd_to_hwirq(d);
0364 
0365     if (enable)
0366         ctx->wake_en |= BIT(bit);
0367     else
0368         ctx->wake_en &= ~BIT(bit);
0369 
0370     return 0;
0371 }
0372 #else
0373 #define dwapb_irq_set_wake  NULL
0374 #endif
0375 
0376 static const struct irq_chip dwapb_irq_chip = {
0377     .name       = DWAPB_DRIVER_NAME,
0378     .irq_ack    = dwapb_irq_ack,
0379     .irq_mask   = dwapb_irq_mask,
0380     .irq_unmask = dwapb_irq_unmask,
0381     .irq_set_type   = dwapb_irq_set_type,
0382     .irq_enable = dwapb_irq_enable,
0383     .irq_disable    = dwapb_irq_disable,
0384     .irq_set_wake   = dwapb_irq_set_wake,
0385     .flags      = IRQCHIP_IMMUTABLE,
0386     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0387 };
0388 
0389 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
0390                    unsigned offset, unsigned debounce)
0391 {
0392     struct dwapb_gpio_port *port = gpiochip_get_data(gc);
0393     struct dwapb_gpio *gpio = port->gpio;
0394     unsigned long flags, val_deb;
0395     unsigned long mask = BIT(offset);
0396 
0397     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0398 
0399     val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
0400     if (debounce)
0401         val_deb |= mask;
0402     else
0403         val_deb &= ~mask;
0404     dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
0405 
0406     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0407 
0408     return 0;
0409 }
0410 
0411 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
0412                  unsigned long config)
0413 {
0414     u32 debounce;
0415 
0416     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0417         return -ENOTSUPP;
0418 
0419     debounce = pinconf_to_config_argument(config);
0420     return dwapb_gpio_set_debounce(gc, offset, debounce);
0421 }
0422 
0423 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
0424                   struct dwapb_port_property *pp)
0425 {
0426     int i;
0427 
0428     /* Group all available IRQs into an array of parental IRQs. */
0429     for (i = 0; i < pp->ngpio; ++i) {
0430         if (!pp->irq[i])
0431             continue;
0432 
0433         pirq->irq[pirq->nr_irqs++] = pp->irq[i];
0434     }
0435 
0436     return pirq->nr_irqs ? 0 : -ENOENT;
0437 }
0438 
0439 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
0440                  struct dwapb_gpio_port *port,
0441                  struct dwapb_port_property *pp)
0442 {
0443     struct dwapb_gpio_port_irqchip *pirq;
0444     struct gpio_chip *gc = &port->gc;
0445     struct gpio_irq_chip *girq;
0446     int err;
0447 
0448     pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
0449     if (!pirq)
0450         return;
0451 
0452     if (dwapb_convert_irqs(pirq, pp)) {
0453         dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
0454         goto err_kfree_pirq;
0455     }
0456 
0457     girq = &gc->irq;
0458     girq->handler = handle_bad_irq;
0459     girq->default_type = IRQ_TYPE_NONE;
0460 
0461     port->pirq = pirq;
0462 
0463     /*
0464      * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
0465      * IRQ lane shared between several devices. In that case the parental
0466      * IRQ has to be handled in the shared way so to be properly delivered
0467      * to all the connected devices.
0468      */
0469     if (has_acpi_companion(gpio->dev)) {
0470         girq->num_parents = 0;
0471         girq->parents = NULL;
0472         girq->parent_handler = NULL;
0473 
0474         err = devm_request_irq(gpio->dev, pp->irq[0],
0475                        dwapb_irq_handler_mfd,
0476                        IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
0477         if (err) {
0478             dev_err(gpio->dev, "error requesting IRQ\n");
0479             goto err_kfree_pirq;
0480         }
0481     } else {
0482         girq->num_parents = pirq->nr_irqs;
0483         girq->parents = pirq->irq;
0484         girq->parent_handler_data = gpio;
0485         girq->parent_handler = dwapb_irq_handler;
0486     }
0487 
0488     gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
0489 
0490     return;
0491 
0492 err_kfree_pirq:
0493     devm_kfree(gpio->dev, pirq);
0494 }
0495 
0496 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
0497                    struct dwapb_port_property *pp,
0498                    unsigned int offs)
0499 {
0500     struct dwapb_gpio_port *port;
0501     void __iomem *dat, *set, *dirout;
0502     int err;
0503 
0504     port = &gpio->ports[offs];
0505     port->gpio = gpio;
0506     port->idx = pp->idx;
0507 
0508 #ifdef CONFIG_PM_SLEEP
0509     port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
0510     if (!port->ctx)
0511         return -ENOMEM;
0512 #endif
0513 
0514     dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
0515     set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
0516     dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
0517 
0518     /* This registers 32 GPIO lines per port */
0519     err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
0520              NULL, 0);
0521     if (err) {
0522         dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
0523             port->idx);
0524         return err;
0525     }
0526 
0527     port->gc.fwnode = pp->fwnode;
0528     port->gc.ngpio = pp->ngpio;
0529     port->gc.base = pp->gpio_base;
0530 
0531     /* Only port A support debounce */
0532     if (pp->idx == 0)
0533         port->gc.set_config = dwapb_gpio_set_config;
0534 
0535     /* Only port A can provide interrupts in all configurations of the IP */
0536     if (pp->idx == 0)
0537         dwapb_configure_irqs(gpio, port, pp);
0538 
0539     err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
0540     if (err) {
0541         dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
0542             port->idx);
0543         return err;
0544     }
0545 
0546     return 0;
0547 }
0548 
0549 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
0550               struct dwapb_port_property *pp)
0551 {
0552     int irq, j;
0553 
0554     for (j = 0; j < pp->ngpio; j++) {
0555         if (has_acpi_companion(dev))
0556             irq = platform_get_irq_optional(to_platform_device(dev), j);
0557         else
0558             irq = fwnode_irq_get(fwnode, j);
0559         if (irq > 0)
0560             pp->irq[j] = irq;
0561     }
0562 }
0563 
0564 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
0565 {
0566     struct fwnode_handle *fwnode;
0567     struct dwapb_platform_data *pdata;
0568     struct dwapb_port_property *pp;
0569     int nports;
0570     int i;
0571 
0572     nports = device_get_child_node_count(dev);
0573     if (nports == 0)
0574         return ERR_PTR(-ENODEV);
0575 
0576     pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
0577     if (!pdata)
0578         return ERR_PTR(-ENOMEM);
0579 
0580     pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
0581     if (!pdata->properties)
0582         return ERR_PTR(-ENOMEM);
0583 
0584     pdata->nports = nports;
0585 
0586     i = 0;
0587     device_for_each_child_node(dev, fwnode)  {
0588         pp = &pdata->properties[i++];
0589         pp->fwnode = fwnode;
0590 
0591         if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
0592             pp->idx >= DWAPB_MAX_PORTS) {
0593             dev_err(dev,
0594                 "missing/invalid port index for port%d\n", i);
0595             fwnode_handle_put(fwnode);
0596             return ERR_PTR(-EINVAL);
0597         }
0598 
0599         if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
0600             fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
0601             dev_info(dev,
0602                  "failed to get number of gpios for port%d\n",
0603                  i);
0604             pp->ngpio = DWAPB_MAX_GPIOS;
0605         }
0606 
0607         pp->gpio_base   = -1;
0608 
0609         /* For internal use only, new platforms mustn't exercise this */
0610         if (is_software_node(fwnode))
0611             fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
0612 
0613         /*
0614          * Only port A can provide interrupts in all configurations of
0615          * the IP.
0616          */
0617         if (pp->idx == 0)
0618             dwapb_get_irq(dev, fwnode, pp);
0619     }
0620 
0621     return pdata;
0622 }
0623 
0624 static void dwapb_assert_reset(void *data)
0625 {
0626     struct dwapb_gpio *gpio = data;
0627 
0628     reset_control_assert(gpio->rst);
0629 }
0630 
0631 static int dwapb_get_reset(struct dwapb_gpio *gpio)
0632 {
0633     int err;
0634 
0635     gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
0636     if (IS_ERR(gpio->rst))
0637         return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
0638                      "Cannot get reset descriptor\n");
0639 
0640     err = reset_control_deassert(gpio->rst);
0641     if (err) {
0642         dev_err(gpio->dev, "Cannot deassert reset lane\n");
0643         return err;
0644     }
0645 
0646     return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
0647 }
0648 
0649 static void dwapb_disable_clks(void *data)
0650 {
0651     struct dwapb_gpio *gpio = data;
0652 
0653     clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
0654 }
0655 
0656 static int dwapb_get_clks(struct dwapb_gpio *gpio)
0657 {
0658     int err;
0659 
0660     /* Optional bus and debounce clocks */
0661     gpio->clks[0].id = "bus";
0662     gpio->clks[1].id = "db";
0663     err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
0664                      gpio->clks);
0665     if (err)
0666         return dev_err_probe(gpio->dev, err,
0667                      "Cannot get APB/Debounce clocks\n");
0668 
0669     err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
0670     if (err) {
0671         dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
0672         return err;
0673     }
0674 
0675     return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
0676 }
0677 
0678 static const struct of_device_id dwapb_of_match[] = {
0679     { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
0680     { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
0681     { /* Sentinel */ }
0682 };
0683 MODULE_DEVICE_TABLE(of, dwapb_of_match);
0684 
0685 static const struct acpi_device_id dwapb_acpi_match[] = {
0686     {"HISI0181", GPIO_REG_OFFSET_V1},
0687     {"APMC0D07", GPIO_REG_OFFSET_V1},
0688     {"APMC0D81", GPIO_REG_OFFSET_V2},
0689     { }
0690 };
0691 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
0692 
0693 static int dwapb_gpio_probe(struct platform_device *pdev)
0694 {
0695     unsigned int i;
0696     struct dwapb_gpio *gpio;
0697     int err;
0698     struct dwapb_platform_data *pdata;
0699     struct device *dev = &pdev->dev;
0700 
0701     pdata = dwapb_gpio_get_pdata(dev);
0702     if (IS_ERR(pdata))
0703         return PTR_ERR(pdata);
0704 
0705     gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
0706     if (!gpio)
0707         return -ENOMEM;
0708 
0709     gpio->dev = &pdev->dev;
0710     gpio->nr_ports = pdata->nports;
0711 
0712     err = dwapb_get_reset(gpio);
0713     if (err)
0714         return err;
0715 
0716     gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
0717                    sizeof(*gpio->ports), GFP_KERNEL);
0718     if (!gpio->ports)
0719         return -ENOMEM;
0720 
0721     gpio->regs = devm_platform_ioremap_resource(pdev, 0);
0722     if (IS_ERR(gpio->regs))
0723         return PTR_ERR(gpio->regs);
0724 
0725     err = dwapb_get_clks(gpio);
0726     if (err)
0727         return err;
0728 
0729     gpio->flags = (uintptr_t)device_get_match_data(dev);
0730 
0731     for (i = 0; i < gpio->nr_ports; i++) {
0732         err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
0733         if (err)
0734             return err;
0735     }
0736 
0737     platform_set_drvdata(pdev, gpio);
0738 
0739     return 0;
0740 }
0741 
0742 #ifdef CONFIG_PM_SLEEP
0743 static int dwapb_gpio_suspend(struct device *dev)
0744 {
0745     struct dwapb_gpio *gpio = dev_get_drvdata(dev);
0746     struct gpio_chip *gc    = &gpio->ports[0].gc;
0747     unsigned long flags;
0748     int i;
0749 
0750     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0751     for (i = 0; i < gpio->nr_ports; i++) {
0752         unsigned int offset;
0753         unsigned int idx = gpio->ports[i].idx;
0754         struct dwapb_context *ctx = gpio->ports[i].ctx;
0755 
0756         offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
0757         ctx->dir = dwapb_read(gpio, offset);
0758 
0759         offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
0760         ctx->data = dwapb_read(gpio, offset);
0761 
0762         offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
0763         ctx->ext = dwapb_read(gpio, offset);
0764 
0765         /* Only port A can provide interrupts */
0766         if (idx == 0) {
0767             ctx->int_mask   = dwapb_read(gpio, GPIO_INTMASK);
0768             ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
0769             ctx->int_pol    = dwapb_read(gpio, GPIO_INT_POLARITY);
0770             ctx->int_type   = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
0771             ctx->int_deb    = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
0772 
0773             /* Mask out interrupts */
0774             dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
0775         }
0776     }
0777     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0778 
0779     clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
0780 
0781     return 0;
0782 }
0783 
0784 static int dwapb_gpio_resume(struct device *dev)
0785 {
0786     struct dwapb_gpio *gpio = dev_get_drvdata(dev);
0787     struct gpio_chip *gc    = &gpio->ports[0].gc;
0788     unsigned long flags;
0789     int i, err;
0790 
0791     err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
0792     if (err) {
0793         dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
0794         return err;
0795     }
0796 
0797     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0798     for (i = 0; i < gpio->nr_ports; i++) {
0799         unsigned int offset;
0800         unsigned int idx = gpio->ports[i].idx;
0801         struct dwapb_context *ctx = gpio->ports[i].ctx;
0802 
0803         offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
0804         dwapb_write(gpio, offset, ctx->data);
0805 
0806         offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
0807         dwapb_write(gpio, offset, ctx->dir);
0808 
0809         offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
0810         dwapb_write(gpio, offset, ctx->ext);
0811 
0812         /* Only port A can provide interrupts */
0813         if (idx == 0) {
0814             dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
0815             dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
0816             dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
0817             dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
0818             dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
0819 
0820             /* Clear out spurious interrupts */
0821             dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
0822         }
0823     }
0824     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0825 
0826     return 0;
0827 }
0828 #endif
0829 
0830 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
0831              dwapb_gpio_resume);
0832 
0833 static struct platform_driver dwapb_gpio_driver = {
0834     .driver     = {
0835         .name   = DWAPB_DRIVER_NAME,
0836         .pm = &dwapb_gpio_pm_ops,
0837         .of_match_table = dwapb_of_match,
0838         .acpi_match_table = dwapb_acpi_match,
0839     },
0840     .probe      = dwapb_gpio_probe,
0841 };
0842 
0843 module_platform_driver(dwapb_gpio_driver);
0844 
0845 MODULE_LICENSE("GPL");
0846 MODULE_AUTHOR("Jamie Iles");
0847 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
0848 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
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