drivers/gpio/gpio-dln2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the Diolan DLN-2 USB-GPIO adapter
0004  *
0005  * Copyright (c) 2014 Intel Corporation
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/slab.h>
0011 #include <linux/types.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/irq.h>
0014 #include <linux/irqchip/chained_irq.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/mfd/dln2.h>
0018
0019 #define DLN2_GPIO_ID            0x01
0020
0021 #define DLN2_GPIO_GET_PIN_COUNT     DLN2_CMD(0x01, DLN2_GPIO_ID)
0022 #define DLN2_GPIO_SET_DEBOUNCE      DLN2_CMD(0x04, DLN2_GPIO_ID)
0023 #define DLN2_GPIO_GET_DEBOUNCE      DLN2_CMD(0x05, DLN2_GPIO_ID)
0024 #define DLN2_GPIO_PORT_GET_VAL      DLN2_CMD(0x06, DLN2_GPIO_ID)
0025 #define DLN2_GPIO_PIN_GET_VAL       DLN2_CMD(0x0B, DLN2_GPIO_ID)
0026 #define DLN2_GPIO_PIN_SET_OUT_VAL   DLN2_CMD(0x0C, DLN2_GPIO_ID)
0027 #define DLN2_GPIO_PIN_GET_OUT_VAL   DLN2_CMD(0x0D, DLN2_GPIO_ID)
0028 #define DLN2_GPIO_CONDITION_MET_EV  DLN2_CMD(0x0F, DLN2_GPIO_ID)
0029 #define DLN2_GPIO_PIN_ENABLE        DLN2_CMD(0x10, DLN2_GPIO_ID)
0030 #define DLN2_GPIO_PIN_DISABLE       DLN2_CMD(0x11, DLN2_GPIO_ID)
0031 #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
0032 #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
0033 #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
0034 #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
0035
0036 #define DLN2_GPIO_EVENT_NONE        0
0037 #define DLN2_GPIO_EVENT_CHANGE      1
0038 #define DLN2_GPIO_EVENT_LVL_HIGH    2
0039 #define DLN2_GPIO_EVENT_LVL_LOW     3
0040 #define DLN2_GPIO_EVENT_CHANGE_RISING   0x11
0041 #define DLN2_GPIO_EVENT_CHANGE_FALLING  0x21
0042 #define DLN2_GPIO_EVENT_MASK        0x0F
0043
0044 #define DLN2_GPIO_MAX_PINS 32
0045
0046 struct dln2_gpio {
0047     struct platform_device *pdev;
0048     struct gpio_chip gpio;
0049
0050     /*
0051      * Cache pin direction to save us one transfer, since the hardware has
0052      * separate commands to read the in and out values.
0053      */
0054     DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
0055
0056     /* active IRQs - not synced to hardware */
0057     DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
0058     /* active IRQS - synced to hardware */
0059     DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
0060     int irq_type[DLN2_GPIO_MAX_PINS];
0061     struct mutex irq_lock;
0062 };
0063
0064 struct dln2_gpio_pin {
0065     __le16 pin;
0066 };
0067
0068 struct dln2_gpio_pin_val {
0069     __le16 pin __packed;
0070     u8 value;
0071 };
0072
0073 static int dln2_gpio_get_pin_count(struct platform_device *pdev)
0074 {
0075     int ret;
0076     __le16 count;
0077     int len = sizeof(count);
0078
0079     ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
0080     if (ret < 0)
0081         return ret;
0082     if (len < sizeof(count))
0083         return -EPROTO;
0084
0085     return le16_to_cpu(count);
0086 }
0087
0088 static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
0089 {
0090     struct dln2_gpio_pin req = {
0091         .pin = cpu_to_le16(pin),
0092     };
0093
0094     return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
0095 }
0096
0097 static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
0098 {
0099     int ret;
0100     struct dln2_gpio_pin req = {
0101         .pin = cpu_to_le16(pin),
0102     };
0103     struct dln2_gpio_pin_val rsp;
0104     int len = sizeof(rsp);
0105
0106     ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
0107     if (ret < 0)
0108         return ret;
0109     if (len < sizeof(rsp) || req.pin != rsp.pin)
0110         return -EPROTO;
0111
0112     return rsp.value;
0113 }
0114
0115 static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
0116 {
0117     int ret;
0118
0119     ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
0120     if (ret < 0)
0121         return ret;
0122     return !!ret;
0123 }
0124
0125 static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
0126 {
0127     int ret;
0128
0129     ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
0130     if (ret < 0)
0131         return ret;
0132     return !!ret;
0133 }
0134
0135 static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
0136                      unsigned int pin, int value)
0137 {
0138     struct dln2_gpio_pin_val req = {
0139         .pin = cpu_to_le16(pin),
0140         .value = value,
0141     };
0142
0143     return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
0144                 sizeof(req));
0145 }
0146
0147 #define DLN2_GPIO_DIRECTION_IN      0
0148 #define DLN2_GPIO_DIRECTION_OUT     1
0149
0150 static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
0151 {
0152     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0153     struct dln2_gpio_pin req = {
0154         .pin = cpu_to_le16(offset),
0155     };
0156     struct dln2_gpio_pin_val rsp;
0157     int len = sizeof(rsp);
0158     int ret;
0159
0160     ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
0161     if (ret < 0)
0162         return ret;
0163
0164     /* cache the pin direction */
0165     ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
0166                 &req, sizeof(req), &rsp, &len);
0167     if (ret < 0)
0168         return ret;
0169     if (len < sizeof(rsp) || req.pin != rsp.pin) {
0170         ret = -EPROTO;
0171         goto out_disable;
0172     }
0173
0174     switch (rsp.value) {
0175     case DLN2_GPIO_DIRECTION_IN:
0176         clear_bit(offset, dln2->output_enabled);
0177         return 0;
0178     case DLN2_GPIO_DIRECTION_OUT:
0179         set_bit(offset, dln2->output_enabled);
0180         return 0;
0181     default:
0182         ret = -EPROTO;
0183         goto out_disable;
0184     }
0185
0186 out_disable:
0187     dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
0188     return ret;
0189 }
0190
0191 static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
0192 {
0193     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0194
0195     dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
0196 }
0197
0198 static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
0199 {
0200     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0201
0202     if (test_bit(offset, dln2->output_enabled))
0203         return GPIO_LINE_DIRECTION_OUT;
0204
0205     return GPIO_LINE_DIRECTION_IN;
0206 }
0207
0208 static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
0209 {
0210     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0211     int dir;
0212
0213     dir = dln2_gpio_get_direction(chip, offset);
0214     if (dir < 0)
0215         return dir;
0216
0217     if (dir == GPIO_LINE_DIRECTION_IN)
0218         return dln2_gpio_pin_get_in_val(dln2, offset);
0219
0220     return dln2_gpio_pin_get_out_val(dln2, offset);
0221 }
0222
0223 static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0224 {
0225     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0226
0227     dln2_gpio_pin_set_out_val(dln2, offset, value);
0228 }
0229
0230 static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
0231                    unsigned dir)
0232 {
0233     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0234     struct dln2_gpio_pin_val req = {
0235         .pin = cpu_to_le16(offset),
0236         .value = dir,
0237     };
0238     int ret;
0239
0240     ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
0241                    &req, sizeof(req));
0242     if (ret < 0)
0243         return ret;
0244
0245     if (dir == DLN2_GPIO_DIRECTION_OUT)
0246         set_bit(offset, dln2->output_enabled);
0247     else
0248         clear_bit(offset, dln2->output_enabled);
0249
0250     return ret;
0251 }
0252
0253 static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0254 {
0255     return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
0256 }
0257
0258 static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
0259                       int value)
0260 {
0261     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0262     int ret;
0263
0264     ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
0265     if (ret < 0)
0266         return ret;
0267
0268     return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
0269 }
0270
0271 static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset,
0272                 unsigned long config)
0273 {
0274     struct dln2_gpio *dln2 = gpiochip_get_data(chip);
0275     __le32 duration;
0276
0277     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0278         return -ENOTSUPP;
0279
0280     duration = cpu_to_le32(pinconf_to_config_argument(config));
0281     return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
0282                 &duration, sizeof(duration));
0283 }
0284
0285 static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
0286                    unsigned type, unsigned period)
0287 {
0288     struct {
0289         __le16 pin;
0290         u8 type;
0291         __le16 period;
0292     } __packed req = {
0293         .pin = cpu_to_le16(pin),
0294         .type = type,
0295         .period = cpu_to_le16(period),
0296     };
0297
0298     return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
0299                 &req, sizeof(req));
0300 }
0301
0302 static void dln2_irq_unmask(struct irq_data *irqd)
0303 {
0304     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0305     struct dln2_gpio *dln2 = gpiochip_get_data(gc);
0306     int pin = irqd_to_hwirq(irqd);
0307
0308     gpiochip_enable_irq(gc, pin);
0309     set_bit(pin, dln2->unmasked_irqs);
0310 }
0311
0312 static void dln2_irq_mask(struct irq_data *irqd)
0313 {
0314     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0315     struct dln2_gpio *dln2 = gpiochip_get_data(gc);
0316     int pin = irqd_to_hwirq(irqd);
0317
0318     clear_bit(pin, dln2->unmasked_irqs);
0319     gpiochip_disable_irq(gc, pin);
0320 }
0321
0322 static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
0323 {
0324     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0325     struct dln2_gpio *dln2 = gpiochip_get_data(gc);
0326     int pin = irqd_to_hwirq(irqd);
0327
0328     switch (type) {
0329     case IRQ_TYPE_LEVEL_HIGH:
0330         dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
0331         break;
0332     case IRQ_TYPE_LEVEL_LOW:
0333         dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
0334         break;
0335     case IRQ_TYPE_EDGE_BOTH:
0336         dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
0337         break;
0338     case IRQ_TYPE_EDGE_RISING:
0339         dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
0340         break;
0341     case IRQ_TYPE_EDGE_FALLING:
0342         dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
0343         break;
0344     default:
0345         return -EINVAL;
0346     }
0347
0348     return 0;
0349 }
0350
0351 static void dln2_irq_bus_lock(struct irq_data *irqd)
0352 {
0353     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0354     struct dln2_gpio *dln2 = gpiochip_get_data(gc);
0355
0356     mutex_lock(&dln2->irq_lock);
0357 }
0358
0359 static void dln2_irq_bus_unlock(struct irq_data *irqd)
0360 {
0361     struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
0362     struct dln2_gpio *dln2 = gpiochip_get_data(gc);
0363     int pin = irqd_to_hwirq(irqd);
0364     int enabled, unmasked;
0365     unsigned type;
0366     int ret;
0367
0368     enabled = test_bit(pin, dln2->enabled_irqs);
0369     unmasked = test_bit(pin, dln2->unmasked_irqs);
0370
0371     if (enabled != unmasked) {
0372         if (unmasked) {
0373             type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
0374             set_bit(pin, dln2->enabled_irqs);
0375         } else {
0376             type = DLN2_GPIO_EVENT_NONE;
0377             clear_bit(pin, dln2->enabled_irqs);
0378         }
0379
0380         ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
0381         if (ret)
0382             dev_err(dln2->gpio.parent, "failed to set event\n");
0383     }
0384
0385     mutex_unlock(&dln2->irq_lock);
0386 }
0387
0388 static const struct irq_chip dln2_irqchip = {
0389     .name = "dln2-irq",
0390     .irq_mask = dln2_irq_mask,
0391     .irq_unmask = dln2_irq_unmask,
0392     .irq_set_type = dln2_irq_set_type,
0393     .irq_bus_lock = dln2_irq_bus_lock,
0394     .irq_bus_sync_unlock = dln2_irq_bus_unlock,
0395     .flags = IRQCHIP_IMMUTABLE,
0396     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0397 };
0398
0399 static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
0400                 const void *data, int len)
0401 {
0402     int pin, ret;
0403
0404     const struct {
0405         __le16 count;
0406         __u8 type;
0407         __le16 pin;
0408         __u8 value;
0409     } __packed *event = data;
0410     struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
0411
0412     if (len < sizeof(*event)) {
0413         dev_err(dln2->gpio.parent, "short event message\n");
0414         return;
0415     }
0416
0417     pin = le16_to_cpu(event->pin);
0418     if (pin >= dln2->gpio.ngpio) {
0419         dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin);
0420         return;
0421     }
0422
0423     switch (dln2->irq_type[pin]) {
0424     case DLN2_GPIO_EVENT_CHANGE_RISING:
0425         if (!event->value)
0426             return;
0427         break;
0428     case DLN2_GPIO_EVENT_CHANGE_FALLING:
0429         if (event->value)
0430             return;
0431         break;
0432     }
0433
0434     ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin);
0435     if (unlikely(ret))
0436         dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
0437 }
0438
0439 static int dln2_gpio_probe(struct platform_device *pdev)
0440 {
0441     struct dln2_gpio *dln2;
0442     struct device *dev = &pdev->dev;
0443     struct gpio_irq_chip *girq;
0444     int pins;
0445     int ret;
0446
0447     pins = dln2_gpio_get_pin_count(pdev);
0448     if (pins < 0) {
0449         dev_err(dev, "failed to get pin count: %d\n", pins);
0450         return pins;
0451     }
0452     if (pins > DLN2_GPIO_MAX_PINS) {
0453         pins = DLN2_GPIO_MAX_PINS;
0454         dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
0455     }
0456
0457     dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
0458     if (!dln2)
0459         return -ENOMEM;
0460
0461     mutex_init(&dln2->irq_lock);
0462
0463     dln2->pdev = pdev;
0464
0465     dln2->gpio.label = "dln2";
0466     dln2->gpio.parent = dev;
0467     dln2->gpio.owner = THIS_MODULE;
0468     dln2->gpio.base = -1;
0469     dln2->gpio.ngpio = pins;
0470     dln2->gpio.can_sleep = true;
0471     dln2->gpio.set = dln2_gpio_set;
0472     dln2->gpio.get = dln2_gpio_get;
0473     dln2->gpio.request = dln2_gpio_request;
0474     dln2->gpio.free = dln2_gpio_free;
0475     dln2->gpio.get_direction = dln2_gpio_get_direction;
0476     dln2->gpio.direction_input = dln2_gpio_direction_input;
0477     dln2->gpio.direction_output = dln2_gpio_direction_output;
0478     dln2->gpio.set_config = dln2_gpio_set_config;
0479
0480     girq = &dln2->gpio.irq;
0481     gpio_irq_chip_set_chip(girq, &dln2_irqchip);
0482     /* The event comes from the outside so no parent handler */
0483     girq->parent_handler = NULL;
0484     girq->num_parents = 0;
0485     girq->parents = NULL;
0486     girq->default_type = IRQ_TYPE_NONE;
0487     girq->handler = handle_simple_irq;
0488
0489     platform_set_drvdata(pdev, dln2);
0490
0491     ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2);
0492     if (ret < 0) {
0493         dev_err(dev, "failed to add gpio chip: %d\n", ret);
0494         return ret;
0495     }
0496
0497     ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
0498                      dln2_gpio_event);
0499     if (ret) {
0500         dev_err(dev, "failed to register event cb: %d\n", ret);
0501         return ret;
0502     }
0503
0504     return 0;
0505 }
0506
0507 static int dln2_gpio_remove(struct platform_device *pdev)
0508 {
0509     dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
0510
0511     return 0;
0512 }
0513
0514 static struct platform_driver dln2_gpio_driver = {
0515     .driver.name    = "dln2-gpio",
0516     .probe      = dln2_gpio_probe,
0517     .remove     = dln2_gpio_remove,
0518 };
0519
0520 module_platform_driver(dln2_gpio_driver);
0521
0522 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
0523 MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
0524 MODULE_LICENSE("GPL v2");
0525 MODULE_ALIAS("platform:dln2-gpio");