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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * TI DaVinci GPIO Support
0004  *
0005  * Copyright (c) 2006-2007 David Brownell
0006  * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
0007  */
0008 
0009 #include <linux/gpio/driver.h>
0010 #include <linux/errno.h>
0011 #include <linux/kernel.h>
0012 #include <linux/clk.h>
0013 #include <linux/err.h>
0014 #include <linux/io.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqdomain.h>
0017 #include <linux/module.h>
0018 #include <linux/of.h>
0019 #include <linux/of_device.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/platform_data/gpio-davinci.h>
0023 #include <linux/irqchip/chained_irq.h>
0024 #include <linux/spinlock.h>
0025 #include <linux/pm_runtime.h>
0026 
0027 #include <asm-generic/gpio.h>
0028 
0029 #define MAX_REGS_BANKS 5
0030 #define MAX_INT_PER_BANK 32
0031 
0032 struct davinci_gpio_regs {
0033     u32 dir;
0034     u32 out_data;
0035     u32 set_data;
0036     u32 clr_data;
0037     u32 in_data;
0038     u32 set_rising;
0039     u32 clr_rising;
0040     u32 set_falling;
0041     u32 clr_falling;
0042     u32 intstat;
0043 };
0044 
0045 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
0046 
0047 #define BINTEN  0x8 /* GPIO Interrupt Per-Bank Enable Register */
0048 
0049 static void __iomem *gpio_base;
0050 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
0051 
0052 struct davinci_gpio_irq_data {
0053     void __iomem            *regs;
0054     struct davinci_gpio_controller  *chip;
0055     int             bank_num;
0056 };
0057 
0058 struct davinci_gpio_controller {
0059     struct gpio_chip    chip;
0060     struct irq_domain   *irq_domain;
0061     /* Serialize access to GPIO registers */
0062     spinlock_t      lock;
0063     void __iomem        *regs[MAX_REGS_BANKS];
0064     int         gpio_unbanked;
0065     int         irqs[MAX_INT_PER_BANK];
0066     struct davinci_gpio_regs context[MAX_REGS_BANKS];
0067     u32         binten_context;
0068 };
0069 
0070 static inline u32 __gpio_mask(unsigned gpio)
0071 {
0072     return 1 << (gpio % 32);
0073 }
0074 
0075 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
0076 {
0077     struct davinci_gpio_regs __iomem *g;
0078 
0079     g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
0080 
0081     return g;
0082 }
0083 
0084 static int davinci_gpio_irq_setup(struct platform_device *pdev);
0085 
0086 /*--------------------------------------------------------------------------*/
0087 
0088 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
0089 static inline int __davinci_direction(struct gpio_chip *chip,
0090             unsigned offset, bool out, int value)
0091 {
0092     struct davinci_gpio_controller *d = gpiochip_get_data(chip);
0093     struct davinci_gpio_regs __iomem *g;
0094     unsigned long flags;
0095     u32 temp;
0096     int bank = offset / 32;
0097     u32 mask = __gpio_mask(offset);
0098 
0099     g = d->regs[bank];
0100     spin_lock_irqsave(&d->lock, flags);
0101     temp = readl_relaxed(&g->dir);
0102     if (out) {
0103         temp &= ~mask;
0104         writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
0105     } else {
0106         temp |= mask;
0107     }
0108     writel_relaxed(temp, &g->dir);
0109     spin_unlock_irqrestore(&d->lock, flags);
0110 
0111     return 0;
0112 }
0113 
0114 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
0115 {
0116     return __davinci_direction(chip, offset, false, 0);
0117 }
0118 
0119 static int
0120 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
0121 {
0122     return __davinci_direction(chip, offset, true, value);
0123 }
0124 
0125 /*
0126  * Read the pin's value (works even if it's set up as output);
0127  * returns zero/nonzero.
0128  *
0129  * Note that changes are synched to the GPIO clock, so reading values back
0130  * right after you've set them may give old values.
0131  */
0132 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
0133 {
0134     struct davinci_gpio_controller *d = gpiochip_get_data(chip);
0135     struct davinci_gpio_regs __iomem *g;
0136     int bank = offset / 32;
0137 
0138     g = d->regs[bank];
0139 
0140     return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
0141 }
0142 
0143 /*
0144  * Assuming the pin is muxed as a gpio output, set its output value.
0145  */
0146 static void
0147 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0148 {
0149     struct davinci_gpio_controller *d = gpiochip_get_data(chip);
0150     struct davinci_gpio_regs __iomem *g;
0151     int bank = offset / 32;
0152 
0153     g = d->regs[bank];
0154 
0155     writel_relaxed(__gpio_mask(offset),
0156                value ? &g->set_data : &g->clr_data);
0157 }
0158 
0159 static struct davinci_gpio_platform_data *
0160 davinci_gpio_get_pdata(struct platform_device *pdev)
0161 {
0162     struct device_node *dn = pdev->dev.of_node;
0163     struct davinci_gpio_platform_data *pdata;
0164     int ret;
0165     u32 val;
0166 
0167     if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
0168         return dev_get_platdata(&pdev->dev);
0169 
0170     pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
0171     if (!pdata)
0172         return NULL;
0173 
0174     ret = of_property_read_u32(dn, "ti,ngpio", &val);
0175     if (ret)
0176         goto of_err;
0177 
0178     pdata->ngpio = val;
0179 
0180     ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
0181     if (ret)
0182         goto of_err;
0183 
0184     pdata->gpio_unbanked = val;
0185 
0186     return pdata;
0187 
0188 of_err:
0189     dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
0190     return NULL;
0191 }
0192 
0193 static int davinci_gpio_probe(struct platform_device *pdev)
0194 {
0195     int bank, i, ret = 0;
0196     unsigned int ngpio, nbank, nirq;
0197     struct davinci_gpio_controller *chips;
0198     struct davinci_gpio_platform_data *pdata;
0199     struct device *dev = &pdev->dev;
0200 
0201     pdata = davinci_gpio_get_pdata(pdev);
0202     if (!pdata) {
0203         dev_err(dev, "No platform data found\n");
0204         return -EINVAL;
0205     }
0206 
0207     dev->platform_data = pdata;
0208 
0209     /*
0210      * The gpio banks conceptually expose a segmented bitmap,
0211      * and "ngpio" is one more than the largest zero-based
0212      * bit index that's valid.
0213      */
0214     ngpio = pdata->ngpio;
0215     if (ngpio == 0) {
0216         dev_err(dev, "How many GPIOs?\n");
0217         return -EINVAL;
0218     }
0219 
0220     if (WARN_ON(ARCH_NR_GPIOS < ngpio))
0221         ngpio = ARCH_NR_GPIOS;
0222 
0223     /*
0224      * If there are unbanked interrupts then the number of
0225      * interrupts is equal to number of gpios else all are banked so
0226      * number of interrupts is equal to number of banks(each with 16 gpios)
0227      */
0228     if (pdata->gpio_unbanked)
0229         nirq = pdata->gpio_unbanked;
0230     else
0231         nirq = DIV_ROUND_UP(ngpio, 16);
0232 
0233     chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
0234     if (!chips)
0235         return -ENOMEM;
0236 
0237     gpio_base = devm_platform_ioremap_resource(pdev, 0);
0238     if (IS_ERR(gpio_base))
0239         return PTR_ERR(gpio_base);
0240 
0241     for (i = 0; i < nirq; i++) {
0242         chips->irqs[i] = platform_get_irq(pdev, i);
0243         if (chips->irqs[i] < 0)
0244             return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
0245     }
0246 
0247     chips->chip.label = dev_name(dev);
0248 
0249     chips->chip.direction_input = davinci_direction_in;
0250     chips->chip.get = davinci_gpio_get;
0251     chips->chip.direction_output = davinci_direction_out;
0252     chips->chip.set = davinci_gpio_set;
0253 
0254     chips->chip.ngpio = ngpio;
0255     chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
0256 
0257 #ifdef CONFIG_OF_GPIO
0258     chips->chip.of_gpio_n_cells = 2;
0259     chips->chip.parent = dev;
0260     chips->chip.request = gpiochip_generic_request;
0261     chips->chip.free = gpiochip_generic_free;
0262 #endif
0263     spin_lock_init(&chips->lock);
0264 
0265     nbank = DIV_ROUND_UP(ngpio, 32);
0266     for (bank = 0; bank < nbank; bank++)
0267         chips->regs[bank] = gpio_base + offset_array[bank];
0268 
0269     ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
0270     if (ret)
0271         return ret;
0272 
0273     platform_set_drvdata(pdev, chips);
0274     ret = davinci_gpio_irq_setup(pdev);
0275     if (ret)
0276         return ret;
0277 
0278     return 0;
0279 }
0280 
0281 /*--------------------------------------------------------------------------*/
0282 /*
0283  * We expect irqs will normally be set up as input pins, but they can also be
0284  * used as output pins ... which is convenient for testing.
0285  *
0286  * NOTE:  The first few GPIOs also have direct INTC hookups in addition
0287  * to their GPIOBNK0 irq, with a bit less overhead.
0288  *
0289  * All those INTC hookups (direct, plus several IRQ banks) can also
0290  * serve as EDMA event triggers.
0291  */
0292 
0293 static void gpio_irq_disable(struct irq_data *d)
0294 {
0295     struct davinci_gpio_regs __iomem *g = irq2regs(d);
0296     uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
0297 
0298     writel_relaxed(mask, &g->clr_falling);
0299     writel_relaxed(mask, &g->clr_rising);
0300 }
0301 
0302 static void gpio_irq_enable(struct irq_data *d)
0303 {
0304     struct davinci_gpio_regs __iomem *g = irq2regs(d);
0305     uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
0306     unsigned status = irqd_get_trigger_type(d);
0307 
0308     status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
0309     if (!status)
0310         status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
0311 
0312     if (status & IRQ_TYPE_EDGE_FALLING)
0313         writel_relaxed(mask, &g->set_falling);
0314     if (status & IRQ_TYPE_EDGE_RISING)
0315         writel_relaxed(mask, &g->set_rising);
0316 }
0317 
0318 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
0319 {
0320     if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0321         return -EINVAL;
0322 
0323     return 0;
0324 }
0325 
0326 static struct irq_chip gpio_irqchip = {
0327     .name       = "GPIO",
0328     .irq_enable = gpio_irq_enable,
0329     .irq_disable    = gpio_irq_disable,
0330     .irq_set_type   = gpio_irq_type,
0331     .flags      = IRQCHIP_SET_TYPE_MASKED,
0332 };
0333 
0334 static void gpio_irq_handler(struct irq_desc *desc)
0335 {
0336     struct davinci_gpio_regs __iomem *g;
0337     u32 mask = 0xffff;
0338     int bank_num;
0339     struct davinci_gpio_controller *d;
0340     struct davinci_gpio_irq_data *irqdata;
0341 
0342     irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
0343     bank_num = irqdata->bank_num;
0344     g = irqdata->regs;
0345     d = irqdata->chip;
0346 
0347     /* we only care about one bank */
0348     if ((bank_num % 2) == 1)
0349         mask <<= 16;
0350 
0351     /* temporarily mask (level sensitive) parent IRQ */
0352     chained_irq_enter(irq_desc_get_chip(desc), desc);
0353     while (1) {
0354         u32     status;
0355         int     bit;
0356         irq_hw_number_t hw_irq;
0357 
0358         /* ack any irqs */
0359         status = readl_relaxed(&g->intstat) & mask;
0360         if (!status)
0361             break;
0362         writel_relaxed(status, &g->intstat);
0363 
0364         /* now demux them to the right lowlevel handler */
0365 
0366         while (status) {
0367             bit = __ffs(status);
0368             status &= ~BIT(bit);
0369             /* Max number of gpios per controller is 144 so
0370              * hw_irq will be in [0..143]
0371              */
0372             hw_irq = (bank_num / 2) * 32 + bit;
0373 
0374             generic_handle_domain_irq(d->irq_domain, hw_irq);
0375         }
0376     }
0377     chained_irq_exit(irq_desc_get_chip(desc), desc);
0378     /* now it may re-trigger */
0379 }
0380 
0381 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
0382 {
0383     struct davinci_gpio_controller *d = gpiochip_get_data(chip);
0384 
0385     if (d->irq_domain)
0386         return irq_create_mapping(d->irq_domain, offset);
0387     else
0388         return -ENXIO;
0389 }
0390 
0391 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
0392 {
0393     struct davinci_gpio_controller *d = gpiochip_get_data(chip);
0394 
0395     /*
0396      * NOTE:  we assume for now that only irqs in the first gpio_chip
0397      * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
0398      */
0399     if (offset < d->gpio_unbanked)
0400         return d->irqs[offset];
0401     else
0402         return -ENODEV;
0403 }
0404 
0405 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
0406 {
0407     struct davinci_gpio_controller *d;
0408     struct davinci_gpio_regs __iomem *g;
0409     u32 mask, i;
0410 
0411     d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
0412     g = (struct davinci_gpio_regs __iomem *)d->regs[0];
0413     for (i = 0; i < MAX_INT_PER_BANK; i++)
0414         if (data->irq == d->irqs[i])
0415             break;
0416 
0417     if (i == MAX_INT_PER_BANK)
0418         return -EINVAL;
0419 
0420     mask = __gpio_mask(i);
0421 
0422     if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
0423         return -EINVAL;
0424 
0425     writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
0426              ? &g->set_falling : &g->clr_falling);
0427     writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
0428              ? &g->set_rising : &g->clr_rising);
0429 
0430     return 0;
0431 }
0432 
0433 static int
0434 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
0435              irq_hw_number_t hw)
0436 {
0437     struct davinci_gpio_controller *chips =
0438                 (struct davinci_gpio_controller *)d->host_data;
0439     struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
0440 
0441     irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
0442                 "davinci_gpio");
0443     irq_set_irq_type(irq, IRQ_TYPE_NONE);
0444     irq_set_chip_data(irq, (__force void *)g);
0445     irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
0446 
0447     return 0;
0448 }
0449 
0450 static const struct irq_domain_ops davinci_gpio_irq_ops = {
0451     .map = davinci_gpio_irq_map,
0452     .xlate = irq_domain_xlate_onetwocell,
0453 };
0454 
0455 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
0456 {
0457     static struct irq_chip_type gpio_unbanked;
0458 
0459     gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
0460 
0461     return &gpio_unbanked.chip;
0462 };
0463 
0464 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
0465 {
0466     static struct irq_chip gpio_unbanked;
0467 
0468     gpio_unbanked = *irq_get_chip(irq);
0469     return &gpio_unbanked;
0470 };
0471 
0472 static const struct of_device_id davinci_gpio_ids[];
0473 
0474 /*
0475  * NOTE:  for suspend/resume, probably best to make a platform_device with
0476  * suspend_late/resume_resume calls hooking into results of the set_wake()
0477  * calls ... so if no gpios are wakeup events the clock can be disabled,
0478  * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
0479  * (dm6446) can be set appropriately for GPIOV33 pins.
0480  */
0481 
0482 static int davinci_gpio_irq_setup(struct platform_device *pdev)
0483 {
0484     unsigned    gpio, bank;
0485     int     irq;
0486     int     ret;
0487     struct clk  *clk;
0488     u32     binten = 0;
0489     unsigned    ngpio;
0490     struct device *dev = &pdev->dev;
0491     struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
0492     struct davinci_gpio_platform_data *pdata = dev->platform_data;
0493     struct davinci_gpio_regs __iomem *g;
0494     struct irq_domain   *irq_domain = NULL;
0495     const struct of_device_id *match;
0496     struct irq_chip *irq_chip;
0497     struct davinci_gpio_irq_data *irqdata;
0498     gpio_get_irq_chip_cb_t gpio_get_irq_chip;
0499 
0500     /*
0501      * Use davinci_gpio_get_irq_chip by default to handle non DT cases
0502      */
0503     gpio_get_irq_chip = davinci_gpio_get_irq_chip;
0504     match = of_match_device(of_match_ptr(davinci_gpio_ids),
0505                 dev);
0506     if (match)
0507         gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
0508 
0509     ngpio = pdata->ngpio;
0510 
0511     clk = devm_clk_get(dev, "gpio");
0512     if (IS_ERR(clk)) {
0513         dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
0514         return PTR_ERR(clk);
0515     }
0516 
0517     ret = clk_prepare_enable(clk);
0518     if (ret)
0519         return ret;
0520 
0521     if (!pdata->gpio_unbanked) {
0522         irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
0523         if (irq < 0) {
0524             dev_err(dev, "Couldn't allocate IRQ numbers\n");
0525             clk_disable_unprepare(clk);
0526             return irq;
0527         }
0528 
0529         irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
0530                             &davinci_gpio_irq_ops,
0531                             chips);
0532         if (!irq_domain) {
0533             dev_err(dev, "Couldn't register an IRQ domain\n");
0534             clk_disable_unprepare(clk);
0535             return -ENODEV;
0536         }
0537     }
0538 
0539     /*
0540      * Arrange gpio_to_irq() support, handling either direct IRQs or
0541      * banked IRQs.  Having GPIOs in the first GPIO bank use direct
0542      * IRQs, while the others use banked IRQs, would need some setup
0543      * tweaks to recognize hardware which can do that.
0544      */
0545     chips->chip.to_irq = gpio_to_irq_banked;
0546     chips->irq_domain = irq_domain;
0547 
0548     /*
0549      * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
0550      * controller only handling trigger modes.  We currently assume no
0551      * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
0552      */
0553     if (pdata->gpio_unbanked) {
0554         /* pass "bank 0" GPIO IRQs to AINTC */
0555         chips->chip.to_irq = gpio_to_irq_unbanked;
0556         chips->gpio_unbanked = pdata->gpio_unbanked;
0557         binten = GENMASK(pdata->gpio_unbanked / 16, 0);
0558 
0559         /* AINTC handles mask/unmask; GPIO handles triggering */
0560         irq = chips->irqs[0];
0561         irq_chip = gpio_get_irq_chip(irq);
0562         irq_chip->name = "GPIO-AINTC";
0563         irq_chip->irq_set_type = gpio_irq_type_unbanked;
0564 
0565         /* default trigger: both edges */
0566         g = chips->regs[0];
0567         writel_relaxed(~0, &g->set_falling);
0568         writel_relaxed(~0, &g->set_rising);
0569 
0570         /* set the direct IRQs up to use that irqchip */
0571         for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
0572             irq_set_chip(chips->irqs[gpio], irq_chip);
0573             irq_set_handler_data(chips->irqs[gpio], chips);
0574             irq_set_status_flags(chips->irqs[gpio],
0575                          IRQ_TYPE_EDGE_BOTH);
0576         }
0577 
0578         goto done;
0579     }
0580 
0581     /*
0582      * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
0583      * then chain through our own handler.
0584      */
0585     for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
0586         /* disabled by default, enabled only as needed
0587          * There are register sets for 32 GPIOs. 2 banks of 16
0588          * GPIOs are covered by each set of registers hence divide by 2
0589          */
0590         g = chips->regs[bank / 2];
0591         writel_relaxed(~0, &g->clr_falling);
0592         writel_relaxed(~0, &g->clr_rising);
0593 
0594         /*
0595          * Each chip handles 32 gpios, and each irq bank consists of 16
0596          * gpio irqs. Pass the irq bank's corresponding controller to
0597          * the chained irq handler.
0598          */
0599         irqdata = devm_kzalloc(&pdev->dev,
0600                        sizeof(struct
0601                           davinci_gpio_irq_data),
0602                           GFP_KERNEL);
0603         if (!irqdata) {
0604             clk_disable_unprepare(clk);
0605             return -ENOMEM;
0606         }
0607 
0608         irqdata->regs = g;
0609         irqdata->bank_num = bank;
0610         irqdata->chip = chips;
0611 
0612         irq_set_chained_handler_and_data(chips->irqs[bank],
0613                          gpio_irq_handler, irqdata);
0614 
0615         binten |= BIT(bank);
0616     }
0617 
0618 done:
0619     /*
0620      * BINTEN -- per-bank interrupt enable. genirq would also let these
0621      * bits be set/cleared dynamically.
0622      */
0623     writel_relaxed(binten, gpio_base + BINTEN);
0624 
0625     return 0;
0626 }
0627 
0628 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
0629                       u32 nbank)
0630 {
0631     struct davinci_gpio_regs __iomem *g;
0632     struct davinci_gpio_regs *context;
0633     u32 bank;
0634     void __iomem *base;
0635 
0636     base = chips->regs[0] - offset_array[0];
0637     chips->binten_context = readl_relaxed(base + BINTEN);
0638 
0639     for (bank = 0; bank < nbank; bank++) {
0640         g = chips->regs[bank];
0641         context = &chips->context[bank];
0642         context->dir = readl_relaxed(&g->dir);
0643         context->set_data = readl_relaxed(&g->set_data);
0644         context->set_rising = readl_relaxed(&g->set_rising);
0645         context->set_falling = readl_relaxed(&g->set_falling);
0646     }
0647 
0648     /* Clear Bank interrupt enable bit */
0649     writel_relaxed(0, base + BINTEN);
0650 
0651     /* Clear all interrupt status registers */
0652     writel_relaxed(GENMASK(31, 0), &g->intstat);
0653 }
0654 
0655 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
0656                      u32 nbank)
0657 {
0658     struct davinci_gpio_regs __iomem *g;
0659     struct davinci_gpio_regs *context;
0660     u32 bank;
0661     void __iomem *base;
0662 
0663     base = chips->regs[0] - offset_array[0];
0664 
0665     if (readl_relaxed(base + BINTEN) != chips->binten_context)
0666         writel_relaxed(chips->binten_context, base + BINTEN);
0667 
0668     for (bank = 0; bank < nbank; bank++) {
0669         g = chips->regs[bank];
0670         context = &chips->context[bank];
0671         if (readl_relaxed(&g->dir) != context->dir)
0672             writel_relaxed(context->dir, &g->dir);
0673         if (readl_relaxed(&g->set_data) != context->set_data)
0674             writel_relaxed(context->set_data, &g->set_data);
0675         if (readl_relaxed(&g->set_rising) != context->set_rising)
0676             writel_relaxed(context->set_rising, &g->set_rising);
0677         if (readl_relaxed(&g->set_falling) != context->set_falling)
0678             writel_relaxed(context->set_falling, &g->set_falling);
0679     }
0680 }
0681 
0682 static int davinci_gpio_suspend(struct device *dev)
0683 {
0684     struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
0685     struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
0686     u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
0687 
0688     davinci_gpio_save_context(chips, nbank);
0689 
0690     return 0;
0691 }
0692 
0693 static int davinci_gpio_resume(struct device *dev)
0694 {
0695     struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
0696     struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
0697     u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
0698 
0699     davinci_gpio_restore_context(chips, nbank);
0700 
0701     return 0;
0702 }
0703 
0704 DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
0705              davinci_gpio_resume);
0706 
0707 static const struct of_device_id davinci_gpio_ids[] = {
0708     { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
0709     { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
0710     { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
0711     { /* sentinel */ },
0712 };
0713 MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
0714 
0715 static struct platform_driver davinci_gpio_driver = {
0716     .probe      = davinci_gpio_probe,
0717     .driver     = {
0718         .name       = "davinci_gpio",
0719         .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
0720         .of_match_table = of_match_ptr(davinci_gpio_ids),
0721     },
0722 };
0723 
0724 /**
0725  * GPIO driver registration needs to be done before machine_init functions
0726  * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
0727  */
0728 static int __init davinci_gpio_drv_reg(void)
0729 {
0730     return platform_driver_register(&davinci_gpio_driver);
0731 }
0732 postcore_initcall(davinci_gpio_drv_reg);
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