drivers/gpio/gpio-crystalcove.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel Crystal Cove GPIO Driver
0004  *
0005  * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
0006  *
0007  * Author: Yang, Bin <bin.yang@intel.com>
0008  */
0009
0010 #include <linux/bitops.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/mfd/intel_soc_pmic.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/seq_file.h>
0018 #include <linux/types.h>
0019
0020 #define CRYSTALCOVE_GPIO_NUM    16
0021 #define CRYSTALCOVE_VGPIO_NUM   95
0022
0023 #define UPDATE_IRQ_TYPE     BIT(0)
0024 #define UPDATE_IRQ_MASK     BIT(1)
0025
0026 #define GPIO0IRQ        0x0b
0027 #define GPIO1IRQ        0x0c
0028 #define MGPIO0IRQS0     0x19
0029 #define MGPIO1IRQS0     0x1a
0030 #define MGPIO0IRQSX     0x1b
0031 #define MGPIO1IRQSX     0x1c
0032 #define GPIO0P0CTLO     0x2b
0033 #define GPIO0P0CTLI     0x33
0034 #define GPIO1P0CTLO     0x3b
0035 #define GPIO1P0CTLI     0x43
0036 #define GPIOPANELCTL        0x52
0037
0038 #define CTLI_INTCNT_DIS     (0)
0039 #define CTLI_INTCNT_NE      (1 << 1)
0040 #define CTLI_INTCNT_PE      (2 << 1)
0041 #define CTLI_INTCNT_BE      (3 << 1)
0042
0043 #define CTLO_DIR_IN     (0)
0044 #define CTLO_DIR_OUT        (1 << 5)
0045
0046 #define CTLO_DRV_CMOS       (0)
0047 #define CTLO_DRV_OD     (1 << 4)
0048
0049 #define CTLO_DRV_REN        (1 << 3)
0050
0051 #define CTLO_RVAL_2KDW      (0)
0052 #define CTLO_RVAL_2KUP      (1 << 1)
0053 #define CTLO_RVAL_50KDW     (2 << 1)
0054 #define CTLO_RVAL_50KUP     (3 << 1)
0055
0056 #define CTLO_INPUT_SET  (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
0057 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
0058
0059 enum ctrl_register {
0060     CTRL_IN,
0061     CTRL_OUT,
0062 };
0063
0064 /**
0065  * struct crystalcove_gpio - Crystal Cove GPIO controller
0066  * @buslock: for bus lock/sync and unlock.
0067  * @chip: the abstract gpio_chip structure.
0068  * @regmap: the regmap from the parent device.
0069  * @update: pending IRQ setting update, to be written to the chip upon unlock.
0070  * @intcnt_value: the Interrupt Detect value to be written.
0071  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
0072  */
0073 struct crystalcove_gpio {
0074     struct mutex buslock; /* irq_bus_lock */
0075     struct gpio_chip chip;
0076     struct regmap *regmap;
0077     int update;
0078     int intcnt_value;
0079     bool set_irq_mask;
0080 };
0081
0082 static inline int to_reg(int gpio, enum ctrl_register reg_type)
0083 {
0084     int reg;
0085
0086     if (gpio >= CRYSTALCOVE_GPIO_NUM) {
0087         /*
0088          * Virtual GPIO called from ACPI, for now we only support
0089          * the panel ctl.
0090          */
0091         switch (gpio) {
0092         case 0x5e:
0093             return GPIOPANELCTL;
0094         default:
0095             return -EOPNOTSUPP;
0096         }
0097     }
0098
0099     if (reg_type == CTRL_IN) {
0100         if (gpio < 8)
0101             reg = GPIO0P0CTLI;
0102         else
0103             reg = GPIO1P0CTLI;
0104     } else {
0105         if (gpio < 8)
0106             reg = GPIO0P0CTLO;
0107         else
0108             reg = GPIO1P0CTLO;
0109     }
0110
0111     return reg + gpio % 8;
0112 }
0113
0114 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
0115 {
0116     u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
0117     int mask = BIT(gpio % 8);
0118
0119     if (cg->set_irq_mask)
0120         regmap_update_bits(cg->regmap, mirqs0, mask, mask);
0121     else
0122         regmap_update_bits(cg->regmap, mirqs0, mask, 0);
0123 }
0124
0125 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
0126 {
0127     int reg = to_reg(gpio, CTRL_IN);
0128
0129     regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
0130 }
0131
0132 static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
0133 {
0134     struct crystalcove_gpio *cg = gpiochip_get_data(chip);
0135     int reg = to_reg(gpio, CTRL_OUT);
0136
0137     if (reg < 0)
0138         return 0;
0139
0140     return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
0141 }
0142
0143 static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
0144 {
0145     struct crystalcove_gpio *cg = gpiochip_get_data(chip);
0146     int reg = to_reg(gpio, CTRL_OUT);
0147
0148     if (reg < 0)
0149         return 0;
0150
0151     return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
0152 }
0153
0154 static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
0155 {
0156     struct crystalcove_gpio *cg = gpiochip_get_data(chip);
0157     unsigned int val;
0158     int ret, reg = to_reg(gpio, CTRL_IN);
0159
0160     if (reg < 0)
0161         return 0;
0162
0163     ret = regmap_read(cg->regmap, reg, &val);
0164     if (ret)
0165         return ret;
0166
0167     return val & 0x1;
0168 }
0169
0170 static void crystalcove_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
0171 {
0172     struct crystalcove_gpio *cg = gpiochip_get_data(chip);
0173     int reg = to_reg(gpio, CTRL_OUT);
0174
0175     if (reg < 0)
0176         return;
0177
0178     if (value)
0179         regmap_update_bits(cg->regmap, reg, 1, 1);
0180     else
0181         regmap_update_bits(cg->regmap, reg, 1, 0);
0182 }
0183
0184 static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
0185 {
0186     struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
0187     irq_hw_number_t hwirq = irqd_to_hwirq(data);
0188
0189     if (hwirq >= CRYSTALCOVE_GPIO_NUM)
0190         return 0;
0191
0192     switch (type) {
0193     case IRQ_TYPE_NONE:
0194         cg->intcnt_value = CTLI_INTCNT_DIS;
0195         break;
0196     case IRQ_TYPE_EDGE_BOTH:
0197         cg->intcnt_value = CTLI_INTCNT_BE;
0198         break;
0199     case IRQ_TYPE_EDGE_RISING:
0200         cg->intcnt_value = CTLI_INTCNT_PE;
0201         break;
0202     case IRQ_TYPE_EDGE_FALLING:
0203         cg->intcnt_value = CTLI_INTCNT_NE;
0204         break;
0205     default:
0206         return -EINVAL;
0207     }
0208
0209     cg->update |= UPDATE_IRQ_TYPE;
0210
0211     return 0;
0212 }
0213
0214 static void crystalcove_bus_lock(struct irq_data *data)
0215 {
0216     struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
0217
0218     mutex_lock(&cg->buslock);
0219 }
0220
0221 static void crystalcove_bus_sync_unlock(struct irq_data *data)
0222 {
0223     struct crystalcove_gpio *cg = gpiochip_get_data(irq_data_get_irq_chip_data(data));
0224     irq_hw_number_t hwirq = irqd_to_hwirq(data);
0225
0226     if (cg->update & UPDATE_IRQ_TYPE)
0227         crystalcove_update_irq_ctrl(cg, hwirq);
0228     if (cg->update & UPDATE_IRQ_MASK)
0229         crystalcove_update_irq_mask(cg, hwirq);
0230     cg->update = 0;
0231
0232     mutex_unlock(&cg->buslock);
0233 }
0234
0235 static void crystalcove_irq_unmask(struct irq_data *data)
0236 {
0237     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0238     struct crystalcove_gpio *cg = gpiochip_get_data(gc);
0239     irq_hw_number_t hwirq = irqd_to_hwirq(data);
0240
0241     if (hwirq >= CRYSTALCOVE_GPIO_NUM)
0242         return;
0243
0244     gpiochip_enable_irq(gc, hwirq);
0245
0246     cg->set_irq_mask = false;
0247     cg->update |= UPDATE_IRQ_MASK;
0248 }
0249
0250 static void crystalcove_irq_mask(struct irq_data *data)
0251 {
0252     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0253     struct crystalcove_gpio *cg = gpiochip_get_data(gc);
0254     irq_hw_number_t hwirq = irqd_to_hwirq(data);
0255
0256     if (hwirq >= CRYSTALCOVE_GPIO_NUM)
0257         return;
0258
0259     cg->set_irq_mask = true;
0260     cg->update |= UPDATE_IRQ_MASK;
0261
0262     gpiochip_disable_irq(gc, hwirq);
0263 }
0264
0265 static const struct irq_chip crystalcove_irqchip = {
0266     .name           = "Crystal Cove",
0267     .irq_mask       = crystalcove_irq_mask,
0268     .irq_unmask     = crystalcove_irq_unmask,
0269     .irq_set_type       = crystalcove_irq_type,
0270     .irq_bus_lock       = crystalcove_bus_lock,
0271     .irq_bus_sync_unlock    = crystalcove_bus_sync_unlock,
0272     .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
0273     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0274 };
0275
0276 static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
0277 {
0278     struct crystalcove_gpio *cg = data;
0279     unsigned long pending;
0280     unsigned int p0, p1;
0281     int gpio;
0282     unsigned int virq;
0283
0284     if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
0285         regmap_read(cg->regmap, GPIO1IRQ, &p1))
0286         return IRQ_NONE;
0287
0288     regmap_write(cg->regmap, GPIO0IRQ, p0);
0289     regmap_write(cg->regmap, GPIO1IRQ, p1);
0290
0291     pending = p0 | p1 << 8;
0292
0293     for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
0294         virq = irq_find_mapping(cg->chip.irq.domain, gpio);
0295         handle_nested_irq(virq);
0296     }
0297
0298     return IRQ_HANDLED;
0299 }
0300
0301 static void crystalcove_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0302 {
0303     struct crystalcove_gpio *cg = gpiochip_get_data(chip);
0304     int gpio, offset;
0305     unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
0306
0307     for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
0308         regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
0309         regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
0310         regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
0311                 &mirqs0);
0312         regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
0313                 &mirqsx);
0314         regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
0315                 &irq);
0316
0317         offset = gpio % 8;
0318         seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
0319                gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
0320                ctli & 0x1 ? "hi" : "lo",
0321                ctli & CTLI_INTCNT_NE ? "fall" : "    ",
0322                ctli & CTLI_INTCNT_PE ? "rise" : "    ",
0323                ctlo,
0324                mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
0325                mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
0326                irq & BIT(offset) ? "pending" : "       ");
0327     }
0328 }
0329
0330 static int crystalcove_gpio_probe(struct platform_device *pdev)
0331 {
0332     int irq = platform_get_irq(pdev, 0);
0333     struct crystalcove_gpio *cg;
0334     int retval;
0335     struct device *dev = pdev->dev.parent;
0336     struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
0337     struct gpio_irq_chip *girq;
0338
0339     if (irq < 0)
0340         return irq;
0341
0342     cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
0343     if (!cg)
0344         return -ENOMEM;
0345
0346     mutex_init(&cg->buslock);
0347     cg->chip.label = KBUILD_MODNAME;
0348     cg->chip.direction_input = crystalcove_gpio_dir_in;
0349     cg->chip.direction_output = crystalcove_gpio_dir_out;
0350     cg->chip.get = crystalcove_gpio_get;
0351     cg->chip.set = crystalcove_gpio_set;
0352     cg->chip.base = -1;
0353     cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
0354     cg->chip.can_sleep = true;
0355     cg->chip.parent = dev;
0356     cg->chip.dbg_show = crystalcove_gpio_dbg_show;
0357     cg->regmap = pmic->regmap;
0358
0359     girq = &cg->chip.irq;
0360     gpio_irq_chip_set_chip(girq, &crystalcove_irqchip);
0361     /* This will let us handle the parent IRQ in the driver */
0362     girq->parent_handler = NULL;
0363     girq->num_parents = 0;
0364     girq->parents = NULL;
0365     girq->default_type = IRQ_TYPE_NONE;
0366     girq->handler = handle_simple_irq;
0367     girq->threaded = true;
0368
0369     retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
0370                        crystalcove_gpio_irq_handler,
0371                        IRQF_ONESHOT, KBUILD_MODNAME, cg);
0372     if (retval) {
0373         dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
0374         return retval;
0375     }
0376
0377     retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
0378     if (retval)
0379         return retval;
0380
0381     /* Distuingish IRQ domain from others sharing (MFD) the same fwnode */
0382     irq_domain_update_bus_token(cg->chip.irq.domain, DOMAIN_BUS_WIRED);
0383
0384     return 0;
0385 }
0386
0387 static struct platform_driver crystalcove_gpio_driver = {
0388     .probe = crystalcove_gpio_probe,
0389     .driver = {
0390         .name = "crystal_cove_gpio",
0391     },
0392 };
0393 module_platform_driver(crystalcove_gpio_driver);
0394
0395 MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
0396 MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
0397 MODULE_LICENSE("GPL v2");