Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2015-2017 Broadcom
0003 
0004 #include <linux/bitops.h>
0005 #include <linux/gpio/driver.h>
0006 #include <linux/of_device.h>
0007 #include <linux/of_irq.h>
0008 #include <linux/module.h>
0009 #include <linux/irqdomain.h>
0010 #include <linux/irqchip/chained_irq.h>
0011 #include <linux/interrupt.h>
0012 
0013 enum gio_reg_index {
0014     GIO_REG_ODEN = 0,
0015     GIO_REG_DATA,
0016     GIO_REG_IODIR,
0017     GIO_REG_EC,
0018     GIO_REG_EI,
0019     GIO_REG_MASK,
0020     GIO_REG_LEVEL,
0021     GIO_REG_STAT,
0022     NUMBER_OF_GIO_REGISTERS
0023 };
0024 
0025 #define GIO_BANK_SIZE           (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
0026 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
0027 #define GIO_ODEN(bank)          GIO_BANK_OFF(bank, GIO_REG_ODEN)
0028 #define GIO_DATA(bank)          GIO_BANK_OFF(bank, GIO_REG_DATA)
0029 #define GIO_IODIR(bank)         GIO_BANK_OFF(bank, GIO_REG_IODIR)
0030 #define GIO_EC(bank)            GIO_BANK_OFF(bank, GIO_REG_EC)
0031 #define GIO_EI(bank)            GIO_BANK_OFF(bank, GIO_REG_EI)
0032 #define GIO_MASK(bank)          GIO_BANK_OFF(bank, GIO_REG_MASK)
0033 #define GIO_LEVEL(bank)         GIO_BANK_OFF(bank, GIO_REG_LEVEL)
0034 #define GIO_STAT(bank)          GIO_BANK_OFF(bank, GIO_REG_STAT)
0035 
0036 struct brcmstb_gpio_bank {
0037     struct list_head node;
0038     int id;
0039     struct gpio_chip gc;
0040     struct brcmstb_gpio_priv *parent_priv;
0041     u32 width;
0042     u32 wake_active;
0043     u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
0044 };
0045 
0046 struct brcmstb_gpio_priv {
0047     struct list_head bank_list;
0048     void __iomem *reg_base;
0049     struct platform_device *pdev;
0050     struct irq_domain *irq_domain;
0051     struct irq_chip irq_chip;
0052     int parent_irq;
0053     int gpio_base;
0054     int num_gpios;
0055     int parent_wake_irq;
0056 };
0057 
0058 #define MAX_GPIO_PER_BANK       32
0059 #define GPIO_BANK(gpio)         ((gpio) >> 5)
0060 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
0061 #define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))
0062 
0063 static inline struct brcmstb_gpio_priv *
0064 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
0065 {
0066     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0067     return bank->parent_priv;
0068 }
0069 
0070 static unsigned long
0071 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
0072 {
0073     void __iomem *reg_base = bank->parent_priv->reg_base;
0074 
0075     return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
0076            bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
0077 }
0078 
0079 static unsigned long
0080 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
0081 {
0082     unsigned long status;
0083     unsigned long flags;
0084 
0085     raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
0086     status = __brcmstb_gpio_get_active_irqs(bank);
0087     raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
0088 
0089     return status;
0090 }
0091 
0092 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
0093                     struct brcmstb_gpio_bank *bank)
0094 {
0095     return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
0096 }
0097 
0098 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
0099         unsigned int hwirq, bool enable)
0100 {
0101     struct gpio_chip *gc = &bank->gc;
0102     struct brcmstb_gpio_priv *priv = bank->parent_priv;
0103     u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
0104     u32 imask;
0105     unsigned long flags;
0106 
0107     raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
0108     imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
0109     if (enable)
0110         imask |= mask;
0111     else
0112         imask &= ~mask;
0113     gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
0114     raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
0115 }
0116 
0117 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
0118 {
0119     struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
0120     /* gc_offset is relative to this gpio_chip; want real offset */
0121     int hwirq = offset + (gc->base - priv->gpio_base);
0122 
0123     if (hwirq >= priv->num_gpios)
0124         return -ENXIO;
0125     return irq_create_mapping(priv->irq_domain, hwirq);
0126 }
0127 
0128 /* -------------------- IRQ chip functions -------------------- */
0129 
0130 static void brcmstb_gpio_irq_mask(struct irq_data *d)
0131 {
0132     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0133     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0134 
0135     brcmstb_gpio_set_imask(bank, d->hwirq, false);
0136 }
0137 
0138 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
0139 {
0140     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0141     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0142 
0143     brcmstb_gpio_set_imask(bank, d->hwirq, true);
0144 }
0145 
0146 static void brcmstb_gpio_irq_ack(struct irq_data *d)
0147 {
0148     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0149     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0150     struct brcmstb_gpio_priv *priv = bank->parent_priv;
0151     u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
0152 
0153     gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
0154 }
0155 
0156 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0157 {
0158     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0159     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0160     struct brcmstb_gpio_priv *priv = bank->parent_priv;
0161     u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
0162     u32 edge_insensitive, iedge_insensitive;
0163     u32 edge_config, iedge_config;
0164     u32 level, ilevel;
0165     unsigned long flags;
0166 
0167     switch (type) {
0168     case IRQ_TYPE_LEVEL_LOW:
0169         level = mask;
0170         edge_config = 0;
0171         edge_insensitive = 0;
0172         break;
0173     case IRQ_TYPE_LEVEL_HIGH:
0174         level = mask;
0175         edge_config = mask;
0176         edge_insensitive = 0;
0177         break;
0178     case IRQ_TYPE_EDGE_FALLING:
0179         level = 0;
0180         edge_config = 0;
0181         edge_insensitive = 0;
0182         break;
0183     case IRQ_TYPE_EDGE_RISING:
0184         level = 0;
0185         edge_config = mask;
0186         edge_insensitive = 0;
0187         break;
0188     case IRQ_TYPE_EDGE_BOTH:
0189         level = 0;
0190         edge_config = 0;  /* don't care, but want known value */
0191         edge_insensitive = mask;
0192         break;
0193     default:
0194         return -EINVAL;
0195     }
0196 
0197     raw_spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
0198 
0199     iedge_config = bank->gc.read_reg(priv->reg_base +
0200             GIO_EC(bank->id)) & ~mask;
0201     iedge_insensitive = bank->gc.read_reg(priv->reg_base +
0202             GIO_EI(bank->id)) & ~mask;
0203     ilevel = bank->gc.read_reg(priv->reg_base +
0204             GIO_LEVEL(bank->id)) & ~mask;
0205 
0206     bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
0207             iedge_config | edge_config);
0208     bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
0209             iedge_insensitive | edge_insensitive);
0210     bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
0211             ilevel | level);
0212 
0213     raw_spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
0214     return 0;
0215 }
0216 
0217 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
0218         unsigned int enable)
0219 {
0220     int ret = 0;
0221 
0222     if (enable)
0223         ret = enable_irq_wake(priv->parent_wake_irq);
0224     else
0225         ret = disable_irq_wake(priv->parent_wake_irq);
0226     if (ret)
0227         dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
0228                 enable ? "enable" : "disable");
0229     return ret;
0230 }
0231 
0232 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
0233 {
0234     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0235     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0236     struct brcmstb_gpio_priv *priv = bank->parent_priv;
0237     u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
0238 
0239     /*
0240      * Do not do anything specific for now, suspend/resume callbacks will
0241      * configure the interrupt mask appropriately
0242      */
0243     if (enable)
0244         bank->wake_active |= mask;
0245     else
0246         bank->wake_active &= ~mask;
0247 
0248     return brcmstb_gpio_priv_set_wake(priv, enable);
0249 }
0250 
0251 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
0252 {
0253     struct brcmstb_gpio_priv *priv = data;
0254 
0255     if (!priv || irq != priv->parent_wake_irq)
0256         return IRQ_NONE;
0257 
0258     /* Nothing to do */
0259     return IRQ_HANDLED;
0260 }
0261 
0262 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
0263 {
0264     struct brcmstb_gpio_priv *priv = bank->parent_priv;
0265     struct irq_domain *domain = priv->irq_domain;
0266     int hwbase = bank->gc.base - priv->gpio_base;
0267     unsigned long status;
0268 
0269     while ((status = brcmstb_gpio_get_active_irqs(bank))) {
0270         unsigned int offset;
0271 
0272         for_each_set_bit(offset, &status, 32) {
0273             if (offset >= bank->width)
0274                 dev_warn(&priv->pdev->dev,
0275                      "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
0276                      bank->id, offset);
0277             generic_handle_domain_irq(domain, hwbase + offset);
0278         }
0279     }
0280 }
0281 
0282 /* Each UPG GIO block has one IRQ for all banks */
0283 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
0284 {
0285     struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
0286     struct irq_chip *chip = irq_desc_get_chip(desc);
0287     struct brcmstb_gpio_bank *bank;
0288 
0289     /* Interrupts weren't properly cleared during probe */
0290     BUG_ON(!priv || !chip);
0291 
0292     chained_irq_enter(chip, desc);
0293     list_for_each_entry(bank, &priv->bank_list, node)
0294         brcmstb_gpio_irq_bank_handler(bank);
0295     chained_irq_exit(chip, desc);
0296 }
0297 
0298 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
0299         struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
0300 {
0301     struct brcmstb_gpio_bank *bank;
0302     int i = 0;
0303 
0304     /* banks are in descending order */
0305     list_for_each_entry_reverse(bank, &priv->bank_list, node) {
0306         i += bank->gc.ngpio;
0307         if (hwirq < i)
0308             return bank;
0309     }
0310     return NULL;
0311 }
0312 
0313 /*
0314  * This lock class tells lockdep that GPIO irqs are in a different
0315  * category than their parents, so it won't report false recursion.
0316  */
0317 static struct lock_class_key brcmstb_gpio_irq_lock_class;
0318 static struct lock_class_key brcmstb_gpio_irq_request_class;
0319 
0320 
0321 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
0322         irq_hw_number_t hwirq)
0323 {
0324     struct brcmstb_gpio_priv *priv = d->host_data;
0325     struct brcmstb_gpio_bank *bank =
0326         brcmstb_gpio_hwirq_to_bank(priv, hwirq);
0327     struct platform_device *pdev = priv->pdev;
0328     int ret;
0329 
0330     if (!bank)
0331         return -EINVAL;
0332 
0333     dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
0334         irq, (int)hwirq, bank->id);
0335     ret = irq_set_chip_data(irq, &bank->gc);
0336     if (ret < 0)
0337         return ret;
0338     irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
0339                   &brcmstb_gpio_irq_request_class);
0340     irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
0341     irq_set_noprobe(irq);
0342     return 0;
0343 }
0344 
0345 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
0346 {
0347     irq_set_chip_and_handler(irq, NULL, NULL);
0348     irq_set_chip_data(irq, NULL);
0349 }
0350 
0351 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
0352     .map = brcmstb_gpio_irq_map,
0353     .unmap = brcmstb_gpio_irq_unmap,
0354     .xlate = irq_domain_xlate_twocell,
0355 };
0356 
0357 /* Make sure that the number of banks matches up between properties */
0358 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
0359         struct device_node *np, struct resource *res)
0360 {
0361     int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
0362     int num_banks =
0363         of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
0364 
0365     if (res_num_banks != num_banks) {
0366         dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
0367                 res_num_banks, num_banks);
0368         return -EINVAL;
0369     } else {
0370         return 0;
0371     }
0372 }
0373 
0374 static int brcmstb_gpio_remove(struct platform_device *pdev)
0375 {
0376     struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
0377     struct brcmstb_gpio_bank *bank;
0378     int offset, virq;
0379 
0380     if (priv->parent_irq > 0)
0381         irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
0382 
0383     /* Remove all IRQ mappings and delete the domain */
0384     if (priv->irq_domain) {
0385         for (offset = 0; offset < priv->num_gpios; offset++) {
0386             virq = irq_find_mapping(priv->irq_domain, offset);
0387             irq_dispose_mapping(virq);
0388         }
0389         irq_domain_remove(priv->irq_domain);
0390     }
0391 
0392     /*
0393      * You can lose return values below, but we report all errors, and it's
0394      * more important to actually perform all of the steps.
0395      */
0396     list_for_each_entry(bank, &priv->bank_list, node)
0397         gpiochip_remove(&bank->gc);
0398 
0399     return 0;
0400 }
0401 
0402 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
0403         const struct of_phandle_args *gpiospec, u32 *flags)
0404 {
0405     struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
0406     struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
0407     int offset;
0408 
0409     if (gc->of_gpio_n_cells != 2) {
0410         WARN_ON(1);
0411         return -EINVAL;
0412     }
0413 
0414     if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
0415         return -EINVAL;
0416 
0417     offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
0418     if (offset >= gc->ngpio || offset < 0)
0419         return -EINVAL;
0420 
0421     if (unlikely(offset >= bank->width)) {
0422         dev_warn_ratelimited(&priv->pdev->dev,
0423             "Received request for invalid GPIO offset %d\n",
0424             gpiospec->args[0]);
0425     }
0426 
0427     if (flags)
0428         *flags = gpiospec->args[1];
0429 
0430     return offset;
0431 }
0432 
0433 /* priv->parent_irq and priv->num_gpios must be set before calling */
0434 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
0435         struct brcmstb_gpio_priv *priv)
0436 {
0437     struct device *dev = &pdev->dev;
0438     struct device_node *np = dev->of_node;
0439     int err;
0440 
0441     priv->irq_domain =
0442         irq_domain_add_linear(np, priv->num_gpios,
0443                       &brcmstb_gpio_irq_domain_ops,
0444                       priv);
0445     if (!priv->irq_domain) {
0446         dev_err(dev, "Couldn't allocate IRQ domain\n");
0447         return -ENXIO;
0448     }
0449 
0450     if (of_property_read_bool(np, "wakeup-source")) {
0451         priv->parent_wake_irq = platform_get_irq(pdev, 1);
0452         if (priv->parent_wake_irq < 0) {
0453             priv->parent_wake_irq = 0;
0454             dev_warn(dev,
0455                 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
0456         } else {
0457             /*
0458              * Set wakeup capability so we can process boot-time
0459              * "wakeups" (e.g., from S5 cold boot)
0460              */
0461             device_set_wakeup_capable(dev, true);
0462             device_wakeup_enable(dev);
0463             err = devm_request_irq(dev, priv->parent_wake_irq,
0464                            brcmstb_gpio_wake_irq_handler,
0465                            IRQF_SHARED,
0466                            "brcmstb-gpio-wake", priv);
0467 
0468             if (err < 0) {
0469                 dev_err(dev, "Couldn't request wake IRQ");
0470                 goto out_free_domain;
0471             }
0472         }
0473     }
0474 
0475     priv->irq_chip.name = dev_name(dev);
0476     priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
0477     priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
0478     priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
0479     priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
0480     priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
0481 
0482     if (priv->parent_wake_irq)
0483         priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
0484 
0485     irq_set_chained_handler_and_data(priv->parent_irq,
0486                      brcmstb_gpio_irq_handler, priv);
0487     irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
0488 
0489     return 0;
0490 
0491 out_free_domain:
0492     irq_domain_remove(priv->irq_domain);
0493 
0494     return err;
0495 }
0496 
0497 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
0498                    struct brcmstb_gpio_bank *bank)
0499 {
0500     struct gpio_chip *gc = &bank->gc;
0501     unsigned int i;
0502 
0503     for (i = 0; i < GIO_REG_STAT; i++)
0504         bank->saved_regs[i] = gc->read_reg(priv->reg_base +
0505                            GIO_BANK_OFF(bank->id, i));
0506 }
0507 
0508 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
0509 {
0510     struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
0511     struct brcmstb_gpio_bank *bank;
0512     struct gpio_chip *gc;
0513     u32 imask;
0514 
0515     /* disable non-wake interrupt */
0516     if (priv->parent_irq >= 0)
0517         disable_irq(priv->parent_irq);
0518 
0519     list_for_each_entry(bank, &priv->bank_list, node) {
0520         gc = &bank->gc;
0521 
0522         if (save)
0523             brcmstb_gpio_bank_save(priv, bank);
0524 
0525         /* Unmask GPIOs which have been flagged as wake-up sources */
0526         if (priv->parent_wake_irq)
0527             imask = bank->wake_active;
0528         else
0529             imask = 0;
0530         gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
0531                    imask);
0532     }
0533 }
0534 
0535 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
0536 {
0537     /* Enable GPIO for S5 cold boot */
0538     brcmstb_gpio_quiesce(&pdev->dev, false);
0539 }
0540 
0541 #ifdef CONFIG_PM_SLEEP
0542 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
0543                       struct brcmstb_gpio_bank *bank)
0544 {
0545     struct gpio_chip *gc = &bank->gc;
0546     unsigned int i;
0547 
0548     for (i = 0; i < GIO_REG_STAT; i++)
0549         gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
0550                   bank->saved_regs[i]);
0551 }
0552 
0553 static int brcmstb_gpio_suspend(struct device *dev)
0554 {
0555     brcmstb_gpio_quiesce(dev, true);
0556     return 0;
0557 }
0558 
0559 static int brcmstb_gpio_resume(struct device *dev)
0560 {
0561     struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
0562     struct brcmstb_gpio_bank *bank;
0563     bool need_wakeup_event = false;
0564 
0565     list_for_each_entry(bank, &priv->bank_list, node) {
0566         need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
0567         brcmstb_gpio_bank_restore(priv, bank);
0568     }
0569 
0570     if (priv->parent_wake_irq && need_wakeup_event)
0571         pm_wakeup_event(dev, 0);
0572 
0573     /* enable non-wake interrupt */
0574     if (priv->parent_irq >= 0)
0575         enable_irq(priv->parent_irq);
0576 
0577     return 0;
0578 }
0579 
0580 #else
0581 #define brcmstb_gpio_suspend    NULL
0582 #define brcmstb_gpio_resume NULL
0583 #endif /* CONFIG_PM_SLEEP */
0584 
0585 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
0586     .suspend_noirq  = brcmstb_gpio_suspend,
0587     .resume_noirq = brcmstb_gpio_resume,
0588 };
0589 
0590 static int brcmstb_gpio_probe(struct platform_device *pdev)
0591 {
0592     struct device *dev = &pdev->dev;
0593     struct device_node *np = dev->of_node;
0594     void __iomem *reg_base;
0595     struct brcmstb_gpio_priv *priv;
0596     struct resource *res;
0597     struct property *prop;
0598     const __be32 *p;
0599     u32 bank_width;
0600     int num_banks = 0;
0601     int err;
0602     static int gpio_base;
0603     unsigned long flags = 0;
0604     bool need_wakeup_event = false;
0605 
0606     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0607     if (!priv)
0608         return -ENOMEM;
0609     platform_set_drvdata(pdev, priv);
0610     INIT_LIST_HEAD(&priv->bank_list);
0611 
0612     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0613     reg_base = devm_ioremap_resource(dev, res);
0614     if (IS_ERR(reg_base))
0615         return PTR_ERR(reg_base);
0616 
0617     priv->gpio_base = gpio_base;
0618     priv->reg_base = reg_base;
0619     priv->pdev = pdev;
0620 
0621     if (of_property_read_bool(np, "interrupt-controller")) {
0622         priv->parent_irq = platform_get_irq(pdev, 0);
0623         if (priv->parent_irq <= 0)
0624             return -ENOENT;
0625     } else {
0626         priv->parent_irq = -ENOENT;
0627     }
0628 
0629     if (brcmstb_gpio_sanity_check_banks(dev, np, res))
0630         return -EINVAL;
0631 
0632     /*
0633      * MIPS endianness is configured by boot strap, which also reverses all
0634      * bus endianness (i.e., big-endian CPU + big endian bus ==> native
0635      * endian I/O).
0636      *
0637      * Other architectures (e.g., ARM) either do not support big endian, or
0638      * else leave I/O in little endian mode.
0639      */
0640 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
0641     flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
0642 #endif
0643 
0644     of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
0645             bank_width) {
0646         struct brcmstb_gpio_bank *bank;
0647         struct gpio_chip *gc;
0648 
0649         /*
0650          * If bank_width is 0, then there is an empty bank in the
0651          * register block. Special handling for this case.
0652          */
0653         if (bank_width == 0) {
0654             dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
0655                 num_banks);
0656             num_banks++;
0657             gpio_base += MAX_GPIO_PER_BANK;
0658             continue;
0659         }
0660 
0661         bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
0662         if (!bank) {
0663             err = -ENOMEM;
0664             goto fail;
0665         }
0666 
0667         bank->parent_priv = priv;
0668         bank->id = num_banks;
0669         if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
0670             dev_err(dev, "Invalid bank width %d\n", bank_width);
0671             err = -EINVAL;
0672             goto fail;
0673         } else {
0674             bank->width = bank_width;
0675         }
0676 
0677         /*
0678          * Regs are 4 bytes wide, have data reg, no set/clear regs,
0679          * and direction bits have 0 = output and 1 = input
0680          */
0681         gc = &bank->gc;
0682         err = bgpio_init(gc, dev, 4,
0683                 reg_base + GIO_DATA(bank->id),
0684                 NULL, NULL, NULL,
0685                 reg_base + GIO_IODIR(bank->id), flags);
0686         if (err) {
0687             dev_err(dev, "bgpio_init() failed\n");
0688             goto fail;
0689         }
0690 
0691         gc->owner = THIS_MODULE;
0692         gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
0693         if (!gc->label) {
0694             err = -ENOMEM;
0695             goto fail;
0696         }
0697         gc->base = gpio_base;
0698         gc->of_gpio_n_cells = 2;
0699         gc->of_xlate = brcmstb_gpio_of_xlate;
0700         /* not all ngpio lines are valid, will use bank width later */
0701         gc->ngpio = MAX_GPIO_PER_BANK;
0702         gc->offset = bank->id * MAX_GPIO_PER_BANK;
0703         if (priv->parent_irq > 0)
0704             gc->to_irq = brcmstb_gpio_to_irq;
0705 
0706         /*
0707          * Mask all interrupts by default, since wakeup interrupts may
0708          * be retained from S5 cold boot
0709          */
0710         need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
0711         gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
0712 
0713         err = gpiochip_add_data(gc, bank);
0714         if (err) {
0715             dev_err(dev, "Could not add gpiochip for bank %d\n",
0716                     bank->id);
0717             goto fail;
0718         }
0719         gpio_base += gc->ngpio;
0720 
0721         dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
0722             gc->base, gc->ngpio, bank->width);
0723 
0724         /* Everything looks good, so add bank to list */
0725         list_add(&bank->node, &priv->bank_list);
0726 
0727         num_banks++;
0728     }
0729 
0730     priv->num_gpios = gpio_base - priv->gpio_base;
0731     if (priv->parent_irq > 0) {
0732         err = brcmstb_gpio_irq_setup(pdev, priv);
0733         if (err)
0734             goto fail;
0735     }
0736 
0737     if (priv->parent_wake_irq && need_wakeup_event)
0738         pm_wakeup_event(dev, 0);
0739 
0740     return 0;
0741 
0742 fail:
0743     (void) brcmstb_gpio_remove(pdev);
0744     return err;
0745 }
0746 
0747 static const struct of_device_id brcmstb_gpio_of_match[] = {
0748     { .compatible = "brcm,brcmstb-gpio" },
0749     {},
0750 };
0751 
0752 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
0753 
0754 static struct platform_driver brcmstb_gpio_driver = {
0755     .driver = {
0756         .name = "brcmstb-gpio",
0757         .of_match_table = brcmstb_gpio_of_match,
0758         .pm = &brcmstb_gpio_pm_ops,
0759     },
0760     .probe = brcmstb_gpio_probe,
0761     .remove = brcmstb_gpio_remove,
0762     .shutdown = brcmstb_gpio_shutdown,
0763 };
0764 module_platform_driver(brcmstb_gpio_driver);
0765 
0766 MODULE_AUTHOR("Gregory Fong");
0767 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
0768 MODULE_LICENSE("GPL v2");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!