drivers/gpio/gpio-bcm-kona.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Broadcom Kona GPIO Driver
0004  *
0005  * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
0006  * Copyright (C) 2012-2014 Broadcom Corporation
0007  */
0008
0009 #include <linux/bitops.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/gpio/driver.h>
0013 #include <linux/of_device.h>
0014 #include <linux/init.h>
0015 #include <linux/irqdomain.h>
0016 #include <linux/irqchip/chained_irq.h>
0017
0018 #define BCM_GPIO_PASSWD             0x00a5a501
0019 #define GPIO_PER_BANK               32
0020 #define GPIO_MAX_BANK_NUM           8
0021
0022 #define GPIO_BANK(gpio)             ((gpio) >> 5)
0023 #define GPIO_BIT(gpio)              ((gpio) & (GPIO_PER_BANK - 1))
0024
0025 /* There is a GPIO control register for each GPIO */
0026 #define GPIO_CONTROL(gpio)          (0x00000100 + ((gpio) << 2))
0027
0028 /* The remaining registers are per GPIO bank */
0029 #define GPIO_OUT_STATUS(bank)           (0x00000000 + ((bank) << 2))
0030 #define GPIO_IN_STATUS(bank)            (0x00000020 + ((bank) << 2))
0031 #define GPIO_OUT_SET(bank)          (0x00000040 + ((bank) << 2))
0032 #define GPIO_OUT_CLEAR(bank)            (0x00000060 + ((bank) << 2))
0033 #define GPIO_INT_STATUS(bank)           (0x00000080 + ((bank) << 2))
0034 #define GPIO_INT_MASK(bank)         (0x000000a0 + ((bank) << 2))
0035 #define GPIO_INT_MSKCLR(bank)           (0x000000c0 + ((bank) << 2))
0036 #define GPIO_PWD_STATUS(bank)           (0x00000500 + ((bank) << 2))
0037
0038 #define GPIO_GPPWR_OFFSET           0x00000520
0039
0040 #define GPIO_GPCTR0_DBR_SHIFT           5
0041 #define GPIO_GPCTR0_DBR_MASK            0x000001e0
0042
0043 #define GPIO_GPCTR0_ITR_SHIFT           3
0044 #define GPIO_GPCTR0_ITR_MASK            0x00000018
0045 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE     0x00000001
0046 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE    0x00000002
0047 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE       0x00000003
0048
0049 #define GPIO_GPCTR0_IOTR_MASK           0x00000001
0050 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT     0x00000000
0051 #define GPIO_GPCTR0_IOTR_CMD_INPUT      0x00000001
0052
0053 #define GPIO_GPCTR0_DB_ENABLE_MASK      0x00000100
0054
0055 #define LOCK_CODE               0xffffffff
0056 #define UNLOCK_CODE             0x00000000
0057
0058 struct bcm_kona_gpio {
0059     void __iomem *reg_base;
0060     int num_bank;
0061     raw_spinlock_t lock;
0062     struct gpio_chip gpio_chip;
0063     struct irq_domain *irq_domain;
0064     struct bcm_kona_gpio_bank *banks;
0065     struct platform_device *pdev;
0066 };
0067
0068 struct bcm_kona_gpio_bank {
0069     int id;
0070     int irq;
0071     /* Used in the interrupt handler */
0072     struct bcm_kona_gpio *kona_gpio;
0073 };
0074
0075 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
0076                         int bank_id, u32 lockcode)
0077 {
0078     writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
0079     writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
0080 }
0081
0082 static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
0083                     unsigned gpio)
0084 {
0085     u32 val;
0086     unsigned long flags;
0087     int bank_id = GPIO_BANK(gpio);
0088
0089     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0090
0091     val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
0092     val |= BIT(gpio);
0093     bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
0094
0095     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0096 }
0097
0098 static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
0099                     unsigned gpio)
0100 {
0101     u32 val;
0102     unsigned long flags;
0103     int bank_id = GPIO_BANK(gpio);
0104
0105     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0106
0107     val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
0108     val &= ~BIT(gpio);
0109     bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
0110
0111     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0112 }
0113
0114 static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
0115 {
0116     struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
0117     void __iomem *reg_base = kona_gpio->reg_base;
0118     u32 val;
0119
0120     val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
0121     return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
0122 }
0123
0124 static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
0125 {
0126     struct bcm_kona_gpio *kona_gpio;
0127     void __iomem *reg_base;
0128     int bank_id = GPIO_BANK(gpio);
0129     int bit = GPIO_BIT(gpio);
0130     u32 val, reg_offset;
0131     unsigned long flags;
0132
0133     kona_gpio = gpiochip_get_data(chip);
0134     reg_base = kona_gpio->reg_base;
0135     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0136
0137     /* this function only applies to output pin */
0138     if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
0139         goto out;
0140
0141     reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
0142
0143     val = readl(reg_base + reg_offset);
0144     val |= BIT(bit);
0145     writel(val, reg_base + reg_offset);
0146
0147 out:
0148     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0149 }
0150
0151 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
0152 {
0153     struct bcm_kona_gpio *kona_gpio;
0154     void __iomem *reg_base;
0155     int bank_id = GPIO_BANK(gpio);
0156     int bit = GPIO_BIT(gpio);
0157     u32 val, reg_offset;
0158     unsigned long flags;
0159
0160     kona_gpio = gpiochip_get_data(chip);
0161     reg_base = kona_gpio->reg_base;
0162     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0163
0164     if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
0165         reg_offset = GPIO_IN_STATUS(bank_id);
0166     else
0167         reg_offset = GPIO_OUT_STATUS(bank_id);
0168
0169     /* read the GPIO bank status */
0170     val = readl(reg_base + reg_offset);
0171
0172     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0173
0174     /* return the specified bit status */
0175     return !!(val & BIT(bit));
0176 }
0177
0178 static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
0179 {
0180     struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
0181
0182     bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
0183     return 0;
0184 }
0185
0186 static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
0187 {
0188     struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
0189
0190     bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
0191 }
0192
0193 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
0194 {
0195     struct bcm_kona_gpio *kona_gpio;
0196     void __iomem *reg_base;
0197     u32 val;
0198     unsigned long flags;
0199
0200     kona_gpio = gpiochip_get_data(chip);
0201     reg_base = kona_gpio->reg_base;
0202     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0203
0204     val = readl(reg_base + GPIO_CONTROL(gpio));
0205     val &= ~GPIO_GPCTR0_IOTR_MASK;
0206     val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
0207     writel(val, reg_base + GPIO_CONTROL(gpio));
0208
0209     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0210
0211     return 0;
0212 }
0213
0214 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
0215                       unsigned gpio, int value)
0216 {
0217     struct bcm_kona_gpio *kona_gpio;
0218     void __iomem *reg_base;
0219     int bank_id = GPIO_BANK(gpio);
0220     int bit = GPIO_BIT(gpio);
0221     u32 val, reg_offset;
0222     unsigned long flags;
0223
0224     kona_gpio = gpiochip_get_data(chip);
0225     reg_base = kona_gpio->reg_base;
0226     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0227
0228     val = readl(reg_base + GPIO_CONTROL(gpio));
0229     val &= ~GPIO_GPCTR0_IOTR_MASK;
0230     val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
0231     writel(val, reg_base + GPIO_CONTROL(gpio));
0232     reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
0233
0234     val = readl(reg_base + reg_offset);
0235     val |= BIT(bit);
0236     writel(val, reg_base + reg_offset);
0237
0238     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0239
0240     return 0;
0241 }
0242
0243 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
0244 {
0245     struct bcm_kona_gpio *kona_gpio;
0246
0247     kona_gpio = gpiochip_get_data(chip);
0248     if (gpio >= kona_gpio->gpio_chip.ngpio)
0249         return -ENXIO;
0250     return irq_create_mapping(kona_gpio->irq_domain, gpio);
0251 }
0252
0253 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
0254                       unsigned debounce)
0255 {
0256     struct bcm_kona_gpio *kona_gpio;
0257     void __iomem *reg_base;
0258     u32 val, res;
0259     unsigned long flags;
0260
0261     kona_gpio = gpiochip_get_data(chip);
0262     reg_base = kona_gpio->reg_base;
0263     /* debounce must be 1-128ms (or 0) */
0264     if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
0265         dev_err(chip->parent, "Debounce value %u not in range\n",
0266             debounce);
0267         return -EINVAL;
0268     }
0269
0270     /* calculate debounce bit value */
0271     if (debounce != 0) {
0272         /* Convert to ms */
0273         debounce /= 1000;
0274         /* find the MSB */
0275         res = fls(debounce) - 1;
0276         /* Check if MSB-1 is set (round up or down) */
0277         if (res > 0 && (debounce & BIT(res - 1)))
0278             res++;
0279     }
0280
0281     /* spin lock for read-modify-write of the GPIO register */
0282     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0283
0284     val = readl(reg_base + GPIO_CONTROL(gpio));
0285     val &= ~GPIO_GPCTR0_DBR_MASK;
0286
0287     if (debounce == 0) {
0288         /* disable debounce */
0289         val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
0290     } else {
0291         val |= GPIO_GPCTR0_DB_ENABLE_MASK |
0292             (res << GPIO_GPCTR0_DBR_SHIFT);
0293     }
0294
0295     writel(val, reg_base + GPIO_CONTROL(gpio));
0296
0297     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0298
0299     return 0;
0300 }
0301
0302 static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
0303                     unsigned long config)
0304 {
0305     u32 debounce;
0306
0307     if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
0308         return -ENOTSUPP;
0309
0310     debounce = pinconf_to_config_argument(config);
0311     return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
0312 }
0313
0314 static const struct gpio_chip template_chip = {
0315     .label = "bcm-kona-gpio",
0316     .owner = THIS_MODULE,
0317     .request = bcm_kona_gpio_request,
0318     .free = bcm_kona_gpio_free,
0319     .get_direction = bcm_kona_gpio_get_dir,
0320     .direction_input = bcm_kona_gpio_direction_input,
0321     .get = bcm_kona_gpio_get,
0322     .direction_output = bcm_kona_gpio_direction_output,
0323     .set = bcm_kona_gpio_set,
0324     .set_config = bcm_kona_gpio_set_config,
0325     .to_irq = bcm_kona_gpio_to_irq,
0326     .base = 0,
0327 };
0328
0329 static void bcm_kona_gpio_irq_ack(struct irq_data *d)
0330 {
0331     struct bcm_kona_gpio *kona_gpio;
0332     void __iomem *reg_base;
0333     unsigned gpio = d->hwirq;
0334     int bank_id = GPIO_BANK(gpio);
0335     int bit = GPIO_BIT(gpio);
0336     u32 val;
0337     unsigned long flags;
0338
0339     kona_gpio = irq_data_get_irq_chip_data(d);
0340     reg_base = kona_gpio->reg_base;
0341     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0342
0343     val = readl(reg_base + GPIO_INT_STATUS(bank_id));
0344     val |= BIT(bit);
0345     writel(val, reg_base + GPIO_INT_STATUS(bank_id));
0346
0347     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0348 }
0349
0350 static void bcm_kona_gpio_irq_mask(struct irq_data *d)
0351 {
0352     struct bcm_kona_gpio *kona_gpio;
0353     void __iomem *reg_base;
0354     unsigned gpio = d->hwirq;
0355     int bank_id = GPIO_BANK(gpio);
0356     int bit = GPIO_BIT(gpio);
0357     u32 val;
0358     unsigned long flags;
0359
0360     kona_gpio = irq_data_get_irq_chip_data(d);
0361     reg_base = kona_gpio->reg_base;
0362     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0363
0364     val = readl(reg_base + GPIO_INT_MASK(bank_id));
0365     val |= BIT(bit);
0366     writel(val, reg_base + GPIO_INT_MASK(bank_id));
0367     gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
0368
0369     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0370 }
0371
0372 static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
0373 {
0374     struct bcm_kona_gpio *kona_gpio;
0375     void __iomem *reg_base;
0376     unsigned gpio = d->hwirq;
0377     int bank_id = GPIO_BANK(gpio);
0378     int bit = GPIO_BIT(gpio);
0379     u32 val;
0380     unsigned long flags;
0381
0382     kona_gpio = irq_data_get_irq_chip_data(d);
0383     reg_base = kona_gpio->reg_base;
0384     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0385
0386     val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
0387     val |= BIT(bit);
0388     writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
0389     gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
0390
0391     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0392 }
0393
0394 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
0395 {
0396     struct bcm_kona_gpio *kona_gpio;
0397     void __iomem *reg_base;
0398     unsigned gpio = d->hwirq;
0399     u32 lvl_type;
0400     u32 val;
0401     unsigned long flags;
0402
0403     kona_gpio = irq_data_get_irq_chip_data(d);
0404     reg_base = kona_gpio->reg_base;
0405     switch (type & IRQ_TYPE_SENSE_MASK) {
0406     case IRQ_TYPE_EDGE_RISING:
0407         lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
0408         break;
0409
0410     case IRQ_TYPE_EDGE_FALLING:
0411         lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
0412         break;
0413
0414     case IRQ_TYPE_EDGE_BOTH:
0415         lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
0416         break;
0417
0418     case IRQ_TYPE_LEVEL_HIGH:
0419     case IRQ_TYPE_LEVEL_LOW:
0420         /* BCM GPIO doesn't support level triggering */
0421     default:
0422         dev_err(kona_gpio->gpio_chip.parent,
0423             "Invalid BCM GPIO irq type 0x%x\n", type);
0424         return -EINVAL;
0425     }
0426
0427     raw_spin_lock_irqsave(&kona_gpio->lock, flags);
0428
0429     val = readl(reg_base + GPIO_CONTROL(gpio));
0430     val &= ~GPIO_GPCTR0_ITR_MASK;
0431     val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
0432     writel(val, reg_base + GPIO_CONTROL(gpio));
0433
0434     raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
0435
0436     return 0;
0437 }
0438
0439 static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
0440 {
0441     void __iomem *reg_base;
0442     int bit, bank_id;
0443     unsigned long sta;
0444     struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
0445     struct irq_chip *chip = irq_desc_get_chip(desc);
0446
0447     chained_irq_enter(chip, desc);
0448
0449     /*
0450      * For bank interrupts, we can't use chip_data to store the kona_gpio
0451      * pointer, since GIC needs it for its own purposes. Therefore, we get
0452      * our pointer from the bank structure.
0453      */
0454     reg_base = bank->kona_gpio->reg_base;
0455     bank_id = bank->id;
0456
0457     while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
0458             (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
0459         for_each_set_bit(bit, &sta, 32) {
0460             int hwirq = GPIO_PER_BANK * bank_id + bit;
0461             /*
0462              * Clear interrupt before handler is called so we don't
0463              * miss any interrupt occurred during executing them.
0464              */
0465             writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
0466                    BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
0467             /* Invoke interrupt handler */
0468             generic_handle_domain_irq(bank->kona_gpio->irq_domain,
0469                           hwirq);
0470         }
0471     }
0472
0473     chained_irq_exit(chip, desc);
0474 }
0475
0476 static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
0477 {
0478     struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
0479
0480     return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
0481 }
0482
0483 static void bcm_kona_gpio_irq_relres(struct irq_data *d)
0484 {
0485     struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
0486
0487     gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
0488 }
0489
0490 static struct irq_chip bcm_gpio_irq_chip = {
0491     .name = "bcm-kona-gpio",
0492     .irq_ack = bcm_kona_gpio_irq_ack,
0493     .irq_mask = bcm_kona_gpio_irq_mask,
0494     .irq_unmask = bcm_kona_gpio_irq_unmask,
0495     .irq_set_type = bcm_kona_gpio_irq_set_type,
0496     .irq_request_resources = bcm_kona_gpio_irq_reqres,
0497     .irq_release_resources = bcm_kona_gpio_irq_relres,
0498 };
0499
0500 static struct of_device_id const bcm_kona_gpio_of_match[] = {
0501     { .compatible = "brcm,kona-gpio" },
0502     {}
0503 };
0504
0505 /*
0506  * This lock class tells lockdep that GPIO irqs are in a different
0507  * category than their parents, so it won't report false recursion.
0508  */
0509 static struct lock_class_key gpio_lock_class;
0510 static struct lock_class_key gpio_request_class;
0511
0512 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
0513                  irq_hw_number_t hwirq)
0514 {
0515     int ret;
0516
0517     ret = irq_set_chip_data(irq, d->host_data);
0518     if (ret < 0)
0519         return ret;
0520     irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
0521     irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
0522     irq_set_noprobe(irq);
0523
0524     return 0;
0525 }
0526
0527 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
0528 {
0529     irq_set_chip_and_handler(irq, NULL, NULL);
0530     irq_set_chip_data(irq, NULL);
0531 }
0532
0533 static const struct irq_domain_ops bcm_kona_irq_ops = {
0534     .map = bcm_kona_gpio_irq_map,
0535     .unmap = bcm_kona_gpio_irq_unmap,
0536     .xlate = irq_domain_xlate_twocell,
0537 };
0538
0539 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
0540 {
0541     void __iomem *reg_base;
0542     int i;
0543
0544     reg_base = kona_gpio->reg_base;
0545     /* disable interrupts and clear status */
0546     for (i = 0; i < kona_gpio->num_bank; i++) {
0547         /* Unlock the entire bank first */
0548         bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
0549         writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
0550         writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
0551         /* Now re-lock the bank */
0552         bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
0553     }
0554 }
0555
0556 static int bcm_kona_gpio_probe(struct platform_device *pdev)
0557 {
0558     struct device *dev = &pdev->dev;
0559     const struct of_device_id *match;
0560     struct bcm_kona_gpio_bank *bank;
0561     struct bcm_kona_gpio *kona_gpio;
0562     struct gpio_chip *chip;
0563     int ret;
0564     int i;
0565
0566     match = of_match_device(bcm_kona_gpio_of_match, dev);
0567     if (!match) {
0568         dev_err(dev, "Failed to find gpio controller\n");
0569         return -ENODEV;
0570     }
0571
0572     kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
0573     if (!kona_gpio)
0574         return -ENOMEM;
0575
0576     kona_gpio->gpio_chip = template_chip;
0577     chip = &kona_gpio->gpio_chip;
0578     ret = platform_irq_count(pdev);
0579     if (!ret) {
0580         dev_err(dev, "Couldn't determine # GPIO banks\n");
0581         return -ENOENT;
0582     } else if (ret < 0) {
0583         return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
0584     }
0585     kona_gpio->num_bank = ret;
0586
0587     if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
0588         dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
0589             GPIO_MAX_BANK_NUM);
0590         return -ENXIO;
0591     }
0592     kona_gpio->banks = devm_kcalloc(dev,
0593                     kona_gpio->num_bank,
0594                     sizeof(*kona_gpio->banks),
0595                     GFP_KERNEL);
0596     if (!kona_gpio->banks)
0597         return -ENOMEM;
0598
0599     kona_gpio->pdev = pdev;
0600     platform_set_drvdata(pdev, kona_gpio);
0601     chip->parent = dev;
0602     chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
0603
0604     kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
0605                               chip->ngpio,
0606                               &bcm_kona_irq_ops,
0607                               kona_gpio);
0608     if (!kona_gpio->irq_domain) {
0609         dev_err(dev, "Couldn't allocate IRQ domain\n");
0610         return -ENXIO;
0611     }
0612
0613     kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
0614     if (IS_ERR(kona_gpio->reg_base)) {
0615         ret = PTR_ERR(kona_gpio->reg_base);
0616         goto err_irq_domain;
0617     }
0618
0619     for (i = 0; i < kona_gpio->num_bank; i++) {
0620         bank = &kona_gpio->banks[i];
0621         bank->id = i;
0622         bank->irq = platform_get_irq(pdev, i);
0623         bank->kona_gpio = kona_gpio;
0624         if (bank->irq < 0) {
0625             dev_err(dev, "Couldn't get IRQ for bank %d", i);
0626             ret = -ENOENT;
0627             goto err_irq_domain;
0628         }
0629     }
0630
0631     dev_info(&pdev->dev, "Setting up Kona GPIO\n");
0632
0633     bcm_kona_gpio_reset(kona_gpio);
0634
0635     ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
0636     if (ret < 0) {
0637         dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
0638         goto err_irq_domain;
0639     }
0640     for (i = 0; i < kona_gpio->num_bank; i++) {
0641         bank = &kona_gpio->banks[i];
0642         irq_set_chained_handler_and_data(bank->irq,
0643                          bcm_kona_gpio_irq_handler,
0644                          bank);
0645     }
0646
0647     raw_spin_lock_init(&kona_gpio->lock);
0648
0649     return 0;
0650
0651 err_irq_domain:
0652     irq_domain_remove(kona_gpio->irq_domain);
0653
0654     return ret;
0655 }
0656
0657 static struct platform_driver bcm_kona_gpio_driver = {
0658     .driver = {
0659             .name = "bcm-kona-gpio",
0660             .of_match_table = bcm_kona_gpio_of_match,
0661     },
0662     .probe = bcm_kona_gpio_probe,
0663 };
0664 builtin_platform_driver(bcm_kona_gpio_driver);