drivers/gpio/gpio-ath79.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Atheros AR71XX/AR724X/AR913X GPIO API support
0004  *
0005  *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
0006  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
0007  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
0008  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
0009  */
0010
0011 #include <linux/gpio/driver.h>
0012 #include <linux/platform_data/gpio-ath79.h>
0013 #include <linux/of_device.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/module.h>
0016 #include <linux/irq.h>
0017
0018 #define AR71XX_GPIO_REG_OE      0x00
0019 #define AR71XX_GPIO_REG_IN      0x04
0020 #define AR71XX_GPIO_REG_SET     0x0c
0021 #define AR71XX_GPIO_REG_CLEAR       0x10
0022
0023 #define AR71XX_GPIO_REG_INT_ENABLE  0x14
0024 #define AR71XX_GPIO_REG_INT_TYPE    0x18
0025 #define AR71XX_GPIO_REG_INT_POLARITY    0x1c
0026 #define AR71XX_GPIO_REG_INT_PENDING 0x20
0027 #define AR71XX_GPIO_REG_INT_MASK    0x24
0028
0029 struct ath79_gpio_ctrl {
0030     struct gpio_chip gc;
0031     void __iomem *base;
0032     raw_spinlock_t lock;
0033     unsigned long both_edges;
0034 };
0035
0036 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
0037 {
0038     struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
0039
0040     return container_of(gc, struct ath79_gpio_ctrl, gc);
0041 }
0042
0043 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
0044 {
0045     return readl(ctrl->base + reg);
0046 }
0047
0048 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
0049             unsigned reg, u32 val)
0050 {
0051     writel(val, ctrl->base + reg);
0052 }
0053
0054 static bool ath79_gpio_update_bits(
0055     struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
0056 {
0057     u32 old_val, new_val;
0058
0059     old_val = ath79_gpio_read(ctrl, reg);
0060     new_val = (old_val & ~mask) | (bits & mask);
0061
0062     if (new_val != old_val)
0063         ath79_gpio_write(ctrl, reg, new_val);
0064
0065     return new_val != old_val;
0066 }
0067
0068 static void ath79_gpio_irq_unmask(struct irq_data *data)
0069 {
0070     struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
0071     u32 mask = BIT(irqd_to_hwirq(data));
0072     unsigned long flags;
0073
0074     raw_spin_lock_irqsave(&ctrl->lock, flags);
0075     ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
0076     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0077 }
0078
0079 static void ath79_gpio_irq_mask(struct irq_data *data)
0080 {
0081     struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
0082     u32 mask = BIT(irqd_to_hwirq(data));
0083     unsigned long flags;
0084
0085     raw_spin_lock_irqsave(&ctrl->lock, flags);
0086     ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
0087     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0088 }
0089
0090 static void ath79_gpio_irq_enable(struct irq_data *data)
0091 {
0092     struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
0093     u32 mask = BIT(irqd_to_hwirq(data));
0094     unsigned long flags;
0095
0096     raw_spin_lock_irqsave(&ctrl->lock, flags);
0097     ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
0098     ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
0099     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0100 }
0101
0102 static void ath79_gpio_irq_disable(struct irq_data *data)
0103 {
0104     struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
0105     u32 mask = BIT(irqd_to_hwirq(data));
0106     unsigned long flags;
0107
0108     raw_spin_lock_irqsave(&ctrl->lock, flags);
0109     ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
0110     ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
0111     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0112 }
0113
0114 static int ath79_gpio_irq_set_type(struct irq_data *data,
0115                 unsigned int flow_type)
0116 {
0117     struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
0118     u32 mask = BIT(irqd_to_hwirq(data));
0119     u32 type = 0, polarity = 0;
0120     unsigned long flags;
0121     bool disabled;
0122
0123     switch (flow_type) {
0124     case IRQ_TYPE_EDGE_RISING:
0125         polarity |= mask;
0126         fallthrough;
0127     case IRQ_TYPE_EDGE_FALLING:
0128     case IRQ_TYPE_EDGE_BOTH:
0129         break;
0130
0131     case IRQ_TYPE_LEVEL_HIGH:
0132         polarity |= mask;
0133         fallthrough;
0134     case IRQ_TYPE_LEVEL_LOW:
0135         type |= mask;
0136         break;
0137
0138     default:
0139         return -EINVAL;
0140     }
0141
0142     raw_spin_lock_irqsave(&ctrl->lock, flags);
0143
0144     if (flow_type == IRQ_TYPE_EDGE_BOTH) {
0145         ctrl->both_edges |= mask;
0146         polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
0147     } else {
0148         ctrl->both_edges &= ~mask;
0149     }
0150
0151     /* As the IRQ configuration can't be loaded atomically we
0152      * have to disable the interrupt while the configuration state
0153      * is invalid.
0154      */
0155     disabled = ath79_gpio_update_bits(
0156         ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
0157
0158     ath79_gpio_update_bits(
0159         ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
0160     ath79_gpio_update_bits(
0161         ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
0162
0163     if (disabled)
0164         ath79_gpio_update_bits(
0165             ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
0166
0167     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0168
0169     return 0;
0170 }
0171
0172 static struct irq_chip ath79_gpio_irqchip = {
0173     .name = "gpio-ath79",
0174     .irq_enable = ath79_gpio_irq_enable,
0175     .irq_disable = ath79_gpio_irq_disable,
0176     .irq_mask = ath79_gpio_irq_mask,
0177     .irq_unmask = ath79_gpio_irq_unmask,
0178     .irq_set_type = ath79_gpio_irq_set_type,
0179 };
0180
0181 static void ath79_gpio_irq_handler(struct irq_desc *desc)
0182 {
0183     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0184     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0185     struct ath79_gpio_ctrl *ctrl =
0186         container_of(gc, struct ath79_gpio_ctrl, gc);
0187     unsigned long flags, pending;
0188     u32 both_edges, state;
0189     int irq;
0190
0191     chained_irq_enter(irqchip, desc);
0192
0193     raw_spin_lock_irqsave(&ctrl->lock, flags);
0194
0195     pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
0196
0197     /* Update the polarity of the both edges irqs */
0198     both_edges = ctrl->both_edges & pending;
0199     if (both_edges) {
0200         state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
0201         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
0202                 both_edges, ~state);
0203     }
0204
0205     raw_spin_unlock_irqrestore(&ctrl->lock, flags);
0206
0207     for_each_set_bit(irq, &pending, gc->ngpio)
0208         generic_handle_domain_irq(gc->irq.domain, irq);
0209
0210     chained_irq_exit(irqchip, desc);
0211 }
0212
0213 static const struct of_device_id ath79_gpio_of_match[] = {
0214     { .compatible = "qca,ar7100-gpio" },
0215     { .compatible = "qca,ar9340-gpio" },
0216     {},
0217 };
0218 MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
0219
0220 static int ath79_gpio_probe(struct platform_device *pdev)
0221 {
0222     struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
0223     struct device *dev = &pdev->dev;
0224     struct device_node *np = dev->of_node;
0225     struct ath79_gpio_ctrl *ctrl;
0226     struct gpio_irq_chip *girq;
0227     u32 ath79_gpio_count;
0228     bool oe_inverted;
0229     int err;
0230
0231     ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
0232     if (!ctrl)
0233         return -ENOMEM;
0234
0235     if (np) {
0236         err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
0237         if (err) {
0238             dev_err(dev, "ngpios property is not valid\n");
0239             return err;
0240         }
0241         oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
0242     } else if (pdata) {
0243         ath79_gpio_count = pdata->ngpios;
0244         oe_inverted = pdata->oe_inverted;
0245     } else {
0246         dev_err(dev, "No DT node or platform data found\n");
0247         return -EINVAL;
0248     }
0249
0250     if (ath79_gpio_count >= 32) {
0251         dev_err(dev, "ngpios must be less than 32\n");
0252         return -EINVAL;
0253     }
0254
0255     ctrl->base = devm_platform_ioremap_resource(pdev, 0);
0256     if (IS_ERR(ctrl->base))
0257         return PTR_ERR(ctrl->base);
0258
0259     raw_spin_lock_init(&ctrl->lock);
0260     err = bgpio_init(&ctrl->gc, dev, 4,
0261             ctrl->base + AR71XX_GPIO_REG_IN,
0262             ctrl->base + AR71XX_GPIO_REG_SET,
0263             ctrl->base + AR71XX_GPIO_REG_CLEAR,
0264             oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
0265             oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
0266             0);
0267     if (err) {
0268         dev_err(dev, "bgpio_init failed\n");
0269         return err;
0270     }
0271     /* Use base 0 to stay compatible with legacy platforms */
0272     ctrl->gc.base = 0;
0273
0274     /* Optional interrupt setup */
0275     if (!np || of_property_read_bool(np, "interrupt-controller")) {
0276         girq = &ctrl->gc.irq;
0277         girq->chip = &ath79_gpio_irqchip;
0278         girq->parent_handler = ath79_gpio_irq_handler;
0279         girq->num_parents = 1;
0280         girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
0281                          GFP_KERNEL);
0282         if (!girq->parents)
0283             return -ENOMEM;
0284         girq->parents[0] = platform_get_irq(pdev, 0);
0285         girq->default_type = IRQ_TYPE_NONE;
0286         girq->handler = handle_simple_irq;
0287     }
0288
0289     return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
0290 }
0291
0292 static struct platform_driver ath79_gpio_driver = {
0293     .driver = {
0294         .name = "ath79-gpio",
0295         .of_match_table = ath79_gpio_of_match,
0296     },
0297     .probe = ath79_gpio_probe,
0298 };
0299
0300 module_platform_driver(ath79_gpio_driver);
0301
0302 MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
0303 MODULE_LICENSE("GPL v2");