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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2015 IBM Corp.
0004  *
0005  * Joel Stanley <joel@jms.id.au>
0006  */
0007 
0008 #include <asm/div64.h>
0009 #include <linux/clk.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/gpio/aspeed.h>
0012 #include <linux/hashtable.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/pinctrl/consumer.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/string.h>
0021 
0022 /*
0023  * These two headers aren't meant to be used by GPIO drivers. We need
0024  * them in order to access gpio_chip_hwgpio() which we need to implement
0025  * the aspeed specific API which allows the coprocessor to request
0026  * access to some GPIOs and to arbitrate between coprocessor and ARM.
0027  */
0028 #include <linux/gpio/consumer.h>
0029 #include "gpiolib.h"
0030 
0031 struct aspeed_bank_props {
0032     unsigned int bank;
0033     u32 input;
0034     u32 output;
0035 };
0036 
0037 struct aspeed_gpio_config {
0038     unsigned int nr_gpios;
0039     const struct aspeed_bank_props *props;
0040 };
0041 
0042 /*
0043  * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled
0044  * @timer_users: Tracks the number of users for each timer
0045  *
0046  * The @timer_users has four elements but the first element is unused. This is
0047  * to simplify accounting and indexing, as a zero value in @offset_timer
0048  * represents disabled debouncing for the GPIO. Any other value for an element
0049  * of @offset_timer is used as an index into @timer_users. This behaviour of
0050  * the zero value aligns with the behaviour of zero built from the timer
0051  * configuration registers (i.e. debouncing is disabled).
0052  */
0053 struct aspeed_gpio {
0054     struct gpio_chip chip;
0055     struct irq_chip irqc;
0056     raw_spinlock_t lock;
0057     void __iomem *base;
0058     int irq;
0059     const struct aspeed_gpio_config *config;
0060 
0061     u8 *offset_timer;
0062     unsigned int timer_users[4];
0063     struct clk *clk;
0064 
0065     u32 *dcache;
0066     u8 *cf_copro_bankmap;
0067 };
0068 
0069 struct aspeed_gpio_bank {
0070     uint16_t    val_regs;   /* +0: Rd: read input value, Wr: set write latch
0071                      * +4: Rd/Wr: Direction (0=in, 1=out)
0072                      */
0073     uint16_t    rdata_reg;  /*     Rd: read write latch, Wr: <none>  */
0074     uint16_t    irq_regs;
0075     uint16_t    debounce_regs;
0076     uint16_t    tolerance_regs;
0077     uint16_t    cmdsrc_regs;
0078     const char  names[4][3];
0079 };
0080 
0081 /*
0082  * Note: The "value" register returns the input value sampled on the
0083  *       line even when the GPIO is configured as an output. Since
0084  *       that input goes through synchronizers, writing, then reading
0085  *       back may not return the written value right away.
0086  *
0087  *       The "rdata" register returns the content of the write latch
0088  *       and thus can be used to read back what was last written
0089  *       reliably.
0090  */
0091 
0092 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
0093 
0094 static const struct aspeed_gpio_copro_ops *copro_ops;
0095 static void *copro_data;
0096 
0097 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = {
0098     {
0099         .val_regs = 0x0000,
0100         .rdata_reg = 0x00c0,
0101         .irq_regs = 0x0008,
0102         .debounce_regs = 0x0040,
0103         .tolerance_regs = 0x001c,
0104         .cmdsrc_regs = 0x0060,
0105         .names = { "A", "B", "C", "D" },
0106     },
0107     {
0108         .val_regs = 0x0020,
0109         .rdata_reg = 0x00c4,
0110         .irq_regs = 0x0028,
0111         .debounce_regs = 0x0048,
0112         .tolerance_regs = 0x003c,
0113         .cmdsrc_regs = 0x0068,
0114         .names = { "E", "F", "G", "H" },
0115     },
0116     {
0117         .val_regs = 0x0070,
0118         .rdata_reg = 0x00c8,
0119         .irq_regs = 0x0098,
0120         .debounce_regs = 0x00b0,
0121         .tolerance_regs = 0x00ac,
0122         .cmdsrc_regs = 0x0090,
0123         .names = { "I", "J", "K", "L" },
0124     },
0125     {
0126         .val_regs = 0x0078,
0127         .rdata_reg = 0x00cc,
0128         .irq_regs = 0x00e8,
0129         .debounce_regs = 0x0100,
0130         .tolerance_regs = 0x00fc,
0131         .cmdsrc_regs = 0x00e0,
0132         .names = { "M", "N", "O", "P" },
0133     },
0134     {
0135         .val_regs = 0x0080,
0136         .rdata_reg = 0x00d0,
0137         .irq_regs = 0x0118,
0138         .debounce_regs = 0x0130,
0139         .tolerance_regs = 0x012c,
0140         .cmdsrc_regs = 0x0110,
0141         .names = { "Q", "R", "S", "T" },
0142     },
0143     {
0144         .val_regs = 0x0088,
0145         .rdata_reg = 0x00d4,
0146         .irq_regs = 0x0148,
0147         .debounce_regs = 0x0160,
0148         .tolerance_regs = 0x015c,
0149         .cmdsrc_regs = 0x0140,
0150         .names = { "U", "V", "W", "X" },
0151     },
0152     {
0153         .val_regs = 0x01E0,
0154         .rdata_reg = 0x00d8,
0155         .irq_regs = 0x0178,
0156         .debounce_regs = 0x0190,
0157         .tolerance_regs = 0x018c,
0158         .cmdsrc_regs = 0x0170,
0159         .names = { "Y", "Z", "AA", "AB" },
0160     },
0161     {
0162         .val_regs = 0x01e8,
0163         .rdata_reg = 0x00dc,
0164         .irq_regs = 0x01a8,
0165         .debounce_regs = 0x01c0,
0166         .tolerance_regs = 0x01bc,
0167         .cmdsrc_regs = 0x01a0,
0168         .names = { "AC", "", "", "" },
0169     },
0170 };
0171 
0172 enum aspeed_gpio_reg {
0173     reg_val,
0174     reg_rdata,
0175     reg_dir,
0176     reg_irq_enable,
0177     reg_irq_type0,
0178     reg_irq_type1,
0179     reg_irq_type2,
0180     reg_irq_status,
0181     reg_debounce_sel1,
0182     reg_debounce_sel2,
0183     reg_tolerance,
0184     reg_cmdsrc0,
0185     reg_cmdsrc1,
0186 };
0187 
0188 #define GPIO_VAL_VALUE  0x00
0189 #define GPIO_VAL_DIR    0x04
0190 
0191 #define GPIO_IRQ_ENABLE 0x00
0192 #define GPIO_IRQ_TYPE0  0x04
0193 #define GPIO_IRQ_TYPE1  0x08
0194 #define GPIO_IRQ_TYPE2  0x0c
0195 #define GPIO_IRQ_STATUS 0x10
0196 
0197 #define GPIO_DEBOUNCE_SEL1 0x00
0198 #define GPIO_DEBOUNCE_SEL2 0x04
0199 
0200 #define GPIO_CMDSRC_0   0x00
0201 #define GPIO_CMDSRC_1   0x04
0202 #define  GPIO_CMDSRC_ARM        0
0203 #define  GPIO_CMDSRC_LPC        1
0204 #define  GPIO_CMDSRC_COLDFIRE       2
0205 #define  GPIO_CMDSRC_RESERVED       3
0206 
0207 /* This will be resolved at compile time */
0208 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio,
0209                      const struct aspeed_gpio_bank *bank,
0210                      const enum aspeed_gpio_reg reg)
0211 {
0212     switch (reg) {
0213     case reg_val:
0214         return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
0215     case reg_rdata:
0216         return gpio->base + bank->rdata_reg;
0217     case reg_dir:
0218         return gpio->base + bank->val_regs + GPIO_VAL_DIR;
0219     case reg_irq_enable:
0220         return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
0221     case reg_irq_type0:
0222         return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
0223     case reg_irq_type1:
0224         return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
0225     case reg_irq_type2:
0226         return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
0227     case reg_irq_status:
0228         return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
0229     case reg_debounce_sel1:
0230         return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1;
0231     case reg_debounce_sel2:
0232         return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2;
0233     case reg_tolerance:
0234         return gpio->base + bank->tolerance_regs;
0235     case reg_cmdsrc0:
0236         return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0;
0237     case reg_cmdsrc1:
0238         return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1;
0239     }
0240     BUG();
0241 }
0242 
0243 #define GPIO_BANK(x)    ((x) >> 5)
0244 #define GPIO_OFFSET(x)  ((x) & 0x1f)
0245 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
0246 
0247 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o))
0248 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1)
0249 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0)
0250 
0251 static const struct aspeed_gpio_bank *to_bank(unsigned int offset)
0252 {
0253     unsigned int bank = GPIO_BANK(offset);
0254 
0255     WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks));
0256     return &aspeed_gpio_banks[bank];
0257 }
0258 
0259 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props)
0260 {
0261     return !(props->input || props->output);
0262 }
0263 
0264 static inline const struct aspeed_bank_props *find_bank_props(
0265         struct aspeed_gpio *gpio, unsigned int offset)
0266 {
0267     const struct aspeed_bank_props *props = gpio->config->props;
0268 
0269     while (!is_bank_props_sentinel(props)) {
0270         if (props->bank == GPIO_BANK(offset))
0271             return props;
0272         props++;
0273     }
0274 
0275     return NULL;
0276 }
0277 
0278 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset)
0279 {
0280     const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
0281     const struct aspeed_gpio_bank *bank = to_bank(offset);
0282     unsigned int group = GPIO_OFFSET(offset) / 8;
0283 
0284     return bank->names[group][0] != '\0' &&
0285         (!props || ((props->input | props->output) & GPIO_BIT(offset)));
0286 }
0287 
0288 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset)
0289 {
0290     const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
0291 
0292     return !props || (props->input & GPIO_BIT(offset));
0293 }
0294 
0295 #define have_irq(g, o) have_input((g), (o))
0296 #define have_debounce(g, o) have_input((g), (o))
0297 
0298 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset)
0299 {
0300     const struct aspeed_bank_props *props = find_bank_props(gpio, offset);
0301 
0302     return !props || (props->output & GPIO_BIT(offset));
0303 }
0304 
0305 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio,
0306                       const struct aspeed_gpio_bank *bank,
0307                       int bindex, int cmdsrc)
0308 {
0309     void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0);
0310     void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1);
0311     u32 bit, reg;
0312 
0313     /*
0314      * Each register controls 4 banks, so take the bottom 2
0315      * bits of the bank index, and use them to select the
0316      * right control bit (0, 8, 16 or 24).
0317      */
0318     bit = BIT((bindex & 3) << 3);
0319 
0320     /* Source 1 first to avoid illegal 11 combination */
0321     reg = ioread32(c1);
0322     if (cmdsrc & 2)
0323         reg |= bit;
0324     else
0325         reg &= ~bit;
0326     iowrite32(reg, c1);
0327 
0328     /* Then Source 0 */
0329     reg = ioread32(c0);
0330     if (cmdsrc & 1)
0331         reg |= bit;
0332     else
0333         reg &= ~bit;
0334     iowrite32(reg, c0);
0335 }
0336 
0337 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio,
0338                       unsigned int offset)
0339 {
0340     const struct aspeed_gpio_bank *bank = to_bank(offset);
0341 
0342     if (!copro_ops || !gpio->cf_copro_bankmap)
0343         return false;
0344     if (!gpio->cf_copro_bankmap[offset >> 3])
0345         return false;
0346     if (!copro_ops->request_access)
0347         return false;
0348 
0349     /* Pause the coprocessor */
0350     copro_ops->request_access(copro_data);
0351 
0352     /* Change command source back to ARM */
0353     aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM);
0354 
0355     /* Update cache */
0356     gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata));
0357 
0358     return true;
0359 }
0360 
0361 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio,
0362                       unsigned int offset)
0363 {
0364     const struct aspeed_gpio_bank *bank = to_bank(offset);
0365 
0366     if (!copro_ops || !gpio->cf_copro_bankmap)
0367         return;
0368     if (!gpio->cf_copro_bankmap[offset >> 3])
0369         return;
0370     if (!copro_ops->release_access)
0371         return;
0372 
0373     /* Change command source back to ColdFire */
0374     aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3,
0375                       GPIO_CMDSRC_COLDFIRE);
0376 
0377     /* Restart the coprocessor */
0378     copro_ops->release_access(copro_data);
0379 }
0380 
0381 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset)
0382 {
0383     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0384     const struct aspeed_gpio_bank *bank = to_bank(offset);
0385 
0386     return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset));
0387 }
0388 
0389 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
0390                   int val)
0391 {
0392     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0393     const struct aspeed_gpio_bank *bank = to_bank(offset);
0394     void __iomem *addr;
0395     u32 reg;
0396 
0397     addr = bank_reg(gpio, bank, reg_val);
0398     reg = gpio->dcache[GPIO_BANK(offset)];
0399 
0400     if (val)
0401         reg |= GPIO_BIT(offset);
0402     else
0403         reg &= ~GPIO_BIT(offset);
0404     gpio->dcache[GPIO_BANK(offset)] = reg;
0405 
0406     iowrite32(reg, addr);
0407 }
0408 
0409 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
0410                 int val)
0411 {
0412     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0413     unsigned long flags;
0414     bool copro;
0415 
0416     raw_spin_lock_irqsave(&gpio->lock, flags);
0417     copro = aspeed_gpio_copro_request(gpio, offset);
0418 
0419     __aspeed_gpio_set(gc, offset, val);
0420 
0421     if (copro)
0422         aspeed_gpio_copro_release(gpio, offset);
0423     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0424 }
0425 
0426 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset)
0427 {
0428     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0429     const struct aspeed_gpio_bank *bank = to_bank(offset);
0430     void __iomem *addr = bank_reg(gpio, bank, reg_dir);
0431     unsigned long flags;
0432     bool copro;
0433     u32 reg;
0434 
0435     if (!have_input(gpio, offset))
0436         return -ENOTSUPP;
0437 
0438     raw_spin_lock_irqsave(&gpio->lock, flags);
0439 
0440     reg = ioread32(addr);
0441     reg &= ~GPIO_BIT(offset);
0442 
0443     copro = aspeed_gpio_copro_request(gpio, offset);
0444     iowrite32(reg, addr);
0445     if (copro)
0446         aspeed_gpio_copro_release(gpio, offset);
0447 
0448     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0449 
0450     return 0;
0451 }
0452 
0453 static int aspeed_gpio_dir_out(struct gpio_chip *gc,
0454                    unsigned int offset, int val)
0455 {
0456     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0457     const struct aspeed_gpio_bank *bank = to_bank(offset);
0458     void __iomem *addr = bank_reg(gpio, bank, reg_dir);
0459     unsigned long flags;
0460     bool copro;
0461     u32 reg;
0462 
0463     if (!have_output(gpio, offset))
0464         return -ENOTSUPP;
0465 
0466     raw_spin_lock_irqsave(&gpio->lock, flags);
0467 
0468     reg = ioread32(addr);
0469     reg |= GPIO_BIT(offset);
0470 
0471     copro = aspeed_gpio_copro_request(gpio, offset);
0472     __aspeed_gpio_set(gc, offset, val);
0473     iowrite32(reg, addr);
0474 
0475     if (copro)
0476         aspeed_gpio_copro_release(gpio, offset);
0477     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0478 
0479     return 0;
0480 }
0481 
0482 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
0483 {
0484     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0485     const struct aspeed_gpio_bank *bank = to_bank(offset);
0486     unsigned long flags;
0487     u32 val;
0488 
0489     if (!have_input(gpio, offset))
0490         return GPIO_LINE_DIRECTION_OUT;
0491 
0492     if (!have_output(gpio, offset))
0493         return GPIO_LINE_DIRECTION_IN;
0494 
0495     raw_spin_lock_irqsave(&gpio->lock, flags);
0496 
0497     val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset);
0498 
0499     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0500 
0501     return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
0502 }
0503 
0504 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d,
0505                        struct aspeed_gpio **gpio,
0506                        const struct aspeed_gpio_bank **bank,
0507                        u32 *bit, int *offset)
0508 {
0509     struct aspeed_gpio *internal;
0510 
0511     *offset = irqd_to_hwirq(d);
0512 
0513     internal = irq_data_get_irq_chip_data(d);
0514 
0515     /* This might be a bit of a questionable place to check */
0516     if (!have_irq(internal, *offset))
0517         return -ENOTSUPP;
0518 
0519     *gpio = internal;
0520     *bank = to_bank(*offset);
0521     *bit = GPIO_BIT(*offset);
0522 
0523     return 0;
0524 }
0525 
0526 static void aspeed_gpio_irq_ack(struct irq_data *d)
0527 {
0528     const struct aspeed_gpio_bank *bank;
0529     struct aspeed_gpio *gpio;
0530     unsigned long flags;
0531     void __iomem *status_addr;
0532     int rc, offset;
0533     bool copro;
0534     u32 bit;
0535 
0536     rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
0537     if (rc)
0538         return;
0539 
0540     status_addr = bank_reg(gpio, bank, reg_irq_status);
0541 
0542     raw_spin_lock_irqsave(&gpio->lock, flags);
0543     copro = aspeed_gpio_copro_request(gpio, offset);
0544 
0545     iowrite32(bit, status_addr);
0546 
0547     if (copro)
0548         aspeed_gpio_copro_release(gpio, offset);
0549     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0550 }
0551 
0552 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set)
0553 {
0554     const struct aspeed_gpio_bank *bank;
0555     struct aspeed_gpio *gpio;
0556     unsigned long flags;
0557     u32 reg, bit;
0558     void __iomem *addr;
0559     int rc, offset;
0560     bool copro;
0561 
0562     rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
0563     if (rc)
0564         return;
0565 
0566     addr = bank_reg(gpio, bank, reg_irq_enable);
0567 
0568     raw_spin_lock_irqsave(&gpio->lock, flags);
0569     copro = aspeed_gpio_copro_request(gpio, offset);
0570 
0571     reg = ioread32(addr);
0572     if (set)
0573         reg |= bit;
0574     else
0575         reg &= ~bit;
0576     iowrite32(reg, addr);
0577 
0578     if (copro)
0579         aspeed_gpio_copro_release(gpio, offset);
0580     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0581 }
0582 
0583 static void aspeed_gpio_irq_mask(struct irq_data *d)
0584 {
0585     aspeed_gpio_irq_set_mask(d, false);
0586 }
0587 
0588 static void aspeed_gpio_irq_unmask(struct irq_data *d)
0589 {
0590     aspeed_gpio_irq_set_mask(d, true);
0591 }
0592 
0593 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type)
0594 {
0595     u32 type0 = 0;
0596     u32 type1 = 0;
0597     u32 type2 = 0;
0598     u32 bit, reg;
0599     const struct aspeed_gpio_bank *bank;
0600     irq_flow_handler_t handler;
0601     struct aspeed_gpio *gpio;
0602     unsigned long flags;
0603     void __iomem *addr;
0604     int rc, offset;
0605     bool copro;
0606 
0607     rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset);
0608     if (rc)
0609         return -EINVAL;
0610 
0611     switch (type & IRQ_TYPE_SENSE_MASK) {
0612     case IRQ_TYPE_EDGE_BOTH:
0613         type2 |= bit;
0614         fallthrough;
0615     case IRQ_TYPE_EDGE_RISING:
0616         type0 |= bit;
0617         fallthrough;
0618     case IRQ_TYPE_EDGE_FALLING:
0619         handler = handle_edge_irq;
0620         break;
0621     case IRQ_TYPE_LEVEL_HIGH:
0622         type0 |= bit;
0623         fallthrough;
0624     case IRQ_TYPE_LEVEL_LOW:
0625         type1 |= bit;
0626         handler = handle_level_irq;
0627         break;
0628     default:
0629         return -EINVAL;
0630     }
0631 
0632     raw_spin_lock_irqsave(&gpio->lock, flags);
0633     copro = aspeed_gpio_copro_request(gpio, offset);
0634 
0635     addr = bank_reg(gpio, bank, reg_irq_type0);
0636     reg = ioread32(addr);
0637     reg = (reg & ~bit) | type0;
0638     iowrite32(reg, addr);
0639 
0640     addr = bank_reg(gpio, bank, reg_irq_type1);
0641     reg = ioread32(addr);
0642     reg = (reg & ~bit) | type1;
0643     iowrite32(reg, addr);
0644 
0645     addr = bank_reg(gpio, bank, reg_irq_type2);
0646     reg = ioread32(addr);
0647     reg = (reg & ~bit) | type2;
0648     iowrite32(reg, addr);
0649 
0650     if (copro)
0651         aspeed_gpio_copro_release(gpio, offset);
0652     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0653 
0654     irq_set_handler_locked(d, handler);
0655 
0656     return 0;
0657 }
0658 
0659 static void aspeed_gpio_irq_handler(struct irq_desc *desc)
0660 {
0661     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0662     struct irq_chip *ic = irq_desc_get_chip(desc);
0663     struct aspeed_gpio *data = gpiochip_get_data(gc);
0664     unsigned int i, p, banks;
0665     unsigned long reg;
0666     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0667 
0668     chained_irq_enter(ic, desc);
0669 
0670     banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
0671     for (i = 0; i < banks; i++) {
0672         const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
0673 
0674         reg = ioread32(bank_reg(data, bank, reg_irq_status));
0675 
0676         for_each_set_bit(p, &reg, 32)
0677             generic_handle_domain_irq(gc->irq.domain, i * 32 + p);
0678     }
0679 
0680     chained_irq_exit(ic, desc);
0681 }
0682 
0683 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
0684                        unsigned long *valid_mask,
0685                        unsigned int ngpios)
0686 {
0687     struct aspeed_gpio *gpio = gpiochip_get_data(gc);
0688     const struct aspeed_bank_props *props = gpio->config->props;
0689 
0690     while (!is_bank_props_sentinel(props)) {
0691         unsigned int offset;
0692         const unsigned long int input = props->input;
0693 
0694         /* Pretty crummy approach, but similar to GPIO core */
0695         for_each_clear_bit(offset, &input, 32) {
0696             unsigned int i = props->bank * 32 + offset;
0697 
0698             if (i >= gpio->chip.ngpio)
0699                 break;
0700 
0701             clear_bit(i, valid_mask);
0702         }
0703 
0704         props++;
0705     }
0706 }
0707 
0708 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip,
0709                     unsigned int offset, bool enable)
0710 {
0711     struct aspeed_gpio *gpio = gpiochip_get_data(chip);
0712     unsigned long flags;
0713     void __iomem *treg;
0714     bool copro;
0715     u32 val;
0716 
0717     treg = bank_reg(gpio, to_bank(offset), reg_tolerance);
0718 
0719     raw_spin_lock_irqsave(&gpio->lock, flags);
0720     copro = aspeed_gpio_copro_request(gpio, offset);
0721 
0722     val = readl(treg);
0723 
0724     if (enable)
0725         val |= GPIO_BIT(offset);
0726     else
0727         val &= ~GPIO_BIT(offset);
0728 
0729     writel(val, treg);
0730 
0731     if (copro)
0732         aspeed_gpio_copro_release(gpio, offset);
0733     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0734 
0735     return 0;
0736 }
0737 
0738 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
0739 {
0740     if (!have_gpio(gpiochip_get_data(chip), offset))
0741         return -ENODEV;
0742 
0743     return pinctrl_gpio_request(chip->base + offset);
0744 }
0745 
0746 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
0747 {
0748     pinctrl_gpio_free(chip->base + offset);
0749 }
0750 
0751 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs,
0752         u32 *cycles)
0753 {
0754     u64 rate;
0755     u64 n;
0756     u32 r;
0757 
0758     rate = clk_get_rate(gpio->clk);
0759     if (!rate)
0760         return -ENOTSUPP;
0761 
0762     n = rate * usecs;
0763     r = do_div(n, 1000000);
0764 
0765     if (n >= U32_MAX)
0766         return -ERANGE;
0767 
0768     /* At least as long as the requested time */
0769     *cycles = n + (!!r);
0770 
0771     return 0;
0772 }
0773 
0774 /* Call under gpio->lock */
0775 static int register_allocated_timer(struct aspeed_gpio *gpio,
0776         unsigned int offset, unsigned int timer)
0777 {
0778     if (WARN(gpio->offset_timer[offset] != 0,
0779                 "Offset %d already allocated timer %d\n",
0780                 offset, gpio->offset_timer[offset]))
0781         return -EINVAL;
0782 
0783     if (WARN(gpio->timer_users[timer] == UINT_MAX,
0784                 "Timer user count would overflow\n"))
0785         return -EPERM;
0786 
0787     gpio->offset_timer[offset] = timer;
0788     gpio->timer_users[timer]++;
0789 
0790     return 0;
0791 }
0792 
0793 /* Call under gpio->lock */
0794 static int unregister_allocated_timer(struct aspeed_gpio *gpio,
0795         unsigned int offset)
0796 {
0797     if (WARN(gpio->offset_timer[offset] == 0,
0798                 "No timer allocated to offset %d\n", offset))
0799         return -EINVAL;
0800 
0801     if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0,
0802                 "No users recorded for timer %d\n",
0803                 gpio->offset_timer[offset]))
0804         return -EINVAL;
0805 
0806     gpio->timer_users[gpio->offset_timer[offset]]--;
0807     gpio->offset_timer[offset] = 0;
0808 
0809     return 0;
0810 }
0811 
0812 /* Call under gpio->lock */
0813 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio,
0814         unsigned int offset)
0815 {
0816     return gpio->offset_timer[offset] > 0;
0817 }
0818 
0819 /* Call under gpio->lock */
0820 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset,
0821         unsigned int timer)
0822 {
0823     const struct aspeed_gpio_bank *bank = to_bank(offset);
0824     const u32 mask = GPIO_BIT(offset);
0825     void __iomem *addr;
0826     u32 val;
0827 
0828     /* Note: Debounce timer isn't under control of the command
0829      * source registers, so no need to sync with the coprocessor
0830      */
0831     addr = bank_reg(gpio, bank, reg_debounce_sel1);
0832     val = ioread32(addr);
0833     iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr);
0834 
0835     addr = bank_reg(gpio, bank, reg_debounce_sel2);
0836     val = ioread32(addr);
0837     iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr);
0838 }
0839 
0840 static int enable_debounce(struct gpio_chip *chip, unsigned int offset,
0841                     unsigned long usecs)
0842 {
0843     struct aspeed_gpio *gpio = gpiochip_get_data(chip);
0844     u32 requested_cycles;
0845     unsigned long flags;
0846     int rc;
0847     int i;
0848 
0849     if (!gpio->clk)
0850         return -EINVAL;
0851 
0852     rc = usecs_to_cycles(gpio, usecs, &requested_cycles);
0853     if (rc < 0) {
0854         dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n",
0855                 usecs, clk_get_rate(gpio->clk), rc);
0856         return rc;
0857     }
0858 
0859     raw_spin_lock_irqsave(&gpio->lock, flags);
0860 
0861     if (timer_allocation_registered(gpio, offset)) {
0862         rc = unregister_allocated_timer(gpio, offset);
0863         if (rc < 0)
0864             goto out;
0865     }
0866 
0867     /* Try to find a timer already configured for the debounce period */
0868     for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) {
0869         u32 cycles;
0870 
0871         cycles = ioread32(gpio->base + debounce_timers[i]);
0872         if (requested_cycles == cycles)
0873             break;
0874     }
0875 
0876     if (i == ARRAY_SIZE(debounce_timers)) {
0877         int j;
0878 
0879         /*
0880          * As there are no timers configured for the requested debounce
0881          * period, find an unused timer instead
0882          */
0883         for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) {
0884             if (gpio->timer_users[j] == 0)
0885                 break;
0886         }
0887 
0888         if (j == ARRAY_SIZE(gpio->timer_users)) {
0889             dev_warn(chip->parent,
0890                     "Debounce timers exhausted, cannot debounce for period %luus\n",
0891                     usecs);
0892 
0893             rc = -EPERM;
0894 
0895             /*
0896              * We already adjusted the accounting to remove @offset
0897              * as a user of its previous timer, so also configure
0898              * the hardware so @offset has timers disabled for
0899              * consistency.
0900              */
0901             configure_timer(gpio, offset, 0);
0902             goto out;
0903         }
0904 
0905         i = j;
0906 
0907         iowrite32(requested_cycles, gpio->base + debounce_timers[i]);
0908     }
0909 
0910     if (WARN(i == 0, "Cannot register index of disabled timer\n")) {
0911         rc = -EINVAL;
0912         goto out;
0913     }
0914 
0915     register_allocated_timer(gpio, offset, i);
0916     configure_timer(gpio, offset, i);
0917 
0918 out:
0919     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0920 
0921     return rc;
0922 }
0923 
0924 static int disable_debounce(struct gpio_chip *chip, unsigned int offset)
0925 {
0926     struct aspeed_gpio *gpio = gpiochip_get_data(chip);
0927     unsigned long flags;
0928     int rc;
0929 
0930     raw_spin_lock_irqsave(&gpio->lock, flags);
0931 
0932     rc = unregister_allocated_timer(gpio, offset);
0933     if (!rc)
0934         configure_timer(gpio, offset, 0);
0935 
0936     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0937 
0938     return rc;
0939 }
0940 
0941 static int set_debounce(struct gpio_chip *chip, unsigned int offset,
0942                     unsigned long usecs)
0943 {
0944     struct aspeed_gpio *gpio = gpiochip_get_data(chip);
0945 
0946     if (!have_debounce(gpio, offset))
0947         return -ENOTSUPP;
0948 
0949     if (usecs)
0950         return enable_debounce(chip, offset, usecs);
0951 
0952     return disable_debounce(chip, offset);
0953 }
0954 
0955 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
0956                   unsigned long config)
0957 {
0958     unsigned long param = pinconf_to_config_param(config);
0959     u32 arg = pinconf_to_config_argument(config);
0960 
0961     if (param == PIN_CONFIG_INPUT_DEBOUNCE)
0962         return set_debounce(chip, offset, arg);
0963     else if (param == PIN_CONFIG_BIAS_DISABLE ||
0964             param == PIN_CONFIG_BIAS_PULL_DOWN ||
0965             param == PIN_CONFIG_DRIVE_STRENGTH)
0966         return pinctrl_gpio_set_config(offset, config);
0967     else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
0968             param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
0969         /* Return -ENOTSUPP to trigger emulation, as per datasheet */
0970         return -ENOTSUPP;
0971     else if (param == PIN_CONFIG_PERSIST_STATE)
0972         return aspeed_gpio_reset_tolerance(chip, offset, arg);
0973 
0974     return -ENOTSUPP;
0975 }
0976 
0977 /**
0978  * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
0979  *                             the coprocessor for shared GPIO banks
0980  * @ops: The callbacks
0981  * @data: Pointer passed back to the callbacks
0982  */
0983 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data)
0984 {
0985     copro_data = data;
0986     copro_ops = ops;
0987 
0988     return 0;
0989 }
0990 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops);
0991 
0992 /**
0993  * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
0994  *                               bank gets marked and any access from the ARM will
0995  *                               result in handshaking via callbacks.
0996  * @desc: The GPIO to be marked
0997  * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
0998  * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
0999  * @bit: If non-NULL, returns the bit number of the GPIO in the registers
1000  */
1001 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc,
1002                 u16 *vreg_offset, u16 *dreg_offset, u8 *bit)
1003 {
1004     struct gpio_chip *chip = gpiod_to_chip(desc);
1005     struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1006     int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1007     const struct aspeed_gpio_bank *bank = to_bank(offset);
1008     unsigned long flags;
1009 
1010     if (!gpio->cf_copro_bankmap)
1011         gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL);
1012     if (!gpio->cf_copro_bankmap)
1013         return -ENOMEM;
1014     if (offset < 0 || offset > gpio->chip.ngpio)
1015         return -EINVAL;
1016     bindex = offset >> 3;
1017 
1018     raw_spin_lock_irqsave(&gpio->lock, flags);
1019 
1020     /* Sanity check, this shouldn't happen */
1021     if (gpio->cf_copro_bankmap[bindex] == 0xff) {
1022         rc = -EIO;
1023         goto bail;
1024     }
1025     gpio->cf_copro_bankmap[bindex]++;
1026 
1027     /* Switch command source */
1028     if (gpio->cf_copro_bankmap[bindex] == 1)
1029         aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1030                           GPIO_CMDSRC_COLDFIRE);
1031 
1032     if (vreg_offset)
1033         *vreg_offset = bank->val_regs;
1034     if (dreg_offset)
1035         *dreg_offset = bank->rdata_reg;
1036     if (bit)
1037         *bit = GPIO_OFFSET(offset);
1038  bail:
1039     raw_spin_unlock_irqrestore(&gpio->lock, flags);
1040     return rc;
1041 }
1042 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio);
1043 
1044 /**
1045  * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1046  * @desc: The GPIO to be marked
1047  */
1048 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc)
1049 {
1050     struct gpio_chip *chip = gpiod_to_chip(desc);
1051     struct aspeed_gpio *gpio = gpiochip_get_data(chip);
1052     int rc = 0, bindex, offset = gpio_chip_hwgpio(desc);
1053     const struct aspeed_gpio_bank *bank = to_bank(offset);
1054     unsigned long flags;
1055 
1056     if (!gpio->cf_copro_bankmap)
1057         return -ENXIO;
1058 
1059     if (offset < 0 || offset > gpio->chip.ngpio)
1060         return -EINVAL;
1061     bindex = offset >> 3;
1062 
1063     raw_spin_lock_irqsave(&gpio->lock, flags);
1064 
1065     /* Sanity check, this shouldn't happen */
1066     if (gpio->cf_copro_bankmap[bindex] == 0) {
1067         rc = -EIO;
1068         goto bail;
1069     }
1070     gpio->cf_copro_bankmap[bindex]--;
1071 
1072     /* Switch command source */
1073     if (gpio->cf_copro_bankmap[bindex] == 0)
1074         aspeed_gpio_change_cmd_source(gpio, bank, bindex,
1075                           GPIO_CMDSRC_ARM);
1076  bail:
1077     raw_spin_unlock_irqrestore(&gpio->lock, flags);
1078     return rc;
1079 }
1080 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio);
1081 
1082 /*
1083  * Any banks not specified in a struct aspeed_bank_props array are assumed to
1084  * have the properties:
1085  *
1086  *     { .input = 0xffffffff, .output = 0xffffffff }
1087  */
1088 
1089 static const struct aspeed_bank_props ast2400_bank_props[] = {
1090     /*     input      output   */
1091     { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1092     { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1093     { },
1094 };
1095 
1096 static const struct aspeed_gpio_config ast2400_config =
1097     /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1098     { .nr_gpios = 220, .props = ast2400_bank_props, };
1099 
1100 static const struct aspeed_bank_props ast2500_bank_props[] = {
1101     /*     input      output   */
1102     { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1103     { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1104     { 7, 0x000000ff, 0x000000ff }, /* AC */
1105     { },
1106 };
1107 
1108 static const struct aspeed_gpio_config ast2500_config =
1109     /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1110     { .nr_gpios = 232, .props = ast2500_bank_props, };
1111 
1112 static const struct aspeed_bank_props ast2600_bank_props[] = {
1113     /*     input      output   */
1114     {4, 0xffffffff,  0x00ffffff}, /* Q/R/S/T */
1115     {5, 0xffffffff,  0xffffff00}, /* U/V/W/X */
1116     {6, 0x0000ffff,  0x0000ffff}, /* Y/Z */
1117     { },
1118 };
1119 
1120 static const struct aspeed_gpio_config ast2600_config =
1121     /*
1122      * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs.
1123      * We expect ngpio being set in the device tree and this is a fallback
1124      * option.
1125      */
1126     { .nr_gpios = 208, .props = ast2600_bank_props, };
1127 
1128 static const struct of_device_id aspeed_gpio_of_table[] = {
1129     { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1130     { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1131     { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1132     {}
1133 };
1134 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
1135 
1136 static int __init aspeed_gpio_probe(struct platform_device *pdev)
1137 {
1138     const struct of_device_id *gpio_id;
1139     struct aspeed_gpio *gpio;
1140     int rc, i, banks, err;
1141     u32 ngpio;
1142 
1143     gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
1144     if (!gpio)
1145         return -ENOMEM;
1146 
1147     gpio->base = devm_platform_ioremap_resource(pdev, 0);
1148     if (IS_ERR(gpio->base))
1149         return PTR_ERR(gpio->base);
1150 
1151     raw_spin_lock_init(&gpio->lock);
1152 
1153     gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
1154     if (!gpio_id)
1155         return -EINVAL;
1156 
1157     gpio->clk = of_clk_get(pdev->dev.of_node, 0);
1158     if (IS_ERR(gpio->clk)) {
1159         dev_warn(&pdev->dev,
1160                 "Failed to get clock from devicetree, debouncing disabled\n");
1161         gpio->clk = NULL;
1162     }
1163 
1164     gpio->config = gpio_id->data;
1165 
1166     gpio->chip.parent = &pdev->dev;
1167     err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio);
1168     gpio->chip.ngpio = (u16) ngpio;
1169     if (err)
1170         gpio->chip.ngpio = gpio->config->nr_gpios;
1171     gpio->chip.direction_input = aspeed_gpio_dir_in;
1172     gpio->chip.direction_output = aspeed_gpio_dir_out;
1173     gpio->chip.get_direction = aspeed_gpio_get_direction;
1174     gpio->chip.request = aspeed_gpio_request;
1175     gpio->chip.free = aspeed_gpio_free;
1176     gpio->chip.get = aspeed_gpio_get;
1177     gpio->chip.set = aspeed_gpio_set;
1178     gpio->chip.set_config = aspeed_gpio_set_config;
1179     gpio->chip.label = dev_name(&pdev->dev);
1180     gpio->chip.base = -1;
1181 
1182     /* Allocate a cache of the output registers */
1183     banks = DIV_ROUND_UP(gpio->chip.ngpio, 32);
1184     gpio->dcache = devm_kcalloc(&pdev->dev,
1185                     banks, sizeof(u32), GFP_KERNEL);
1186     if (!gpio->dcache)
1187         return -ENOMEM;
1188 
1189     /*
1190      * Populate it with initial values read from the HW and switch
1191      * all command sources to the ARM by default
1192      */
1193     for (i = 0; i < banks; i++) {
1194         const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i];
1195         void __iomem *addr = bank_reg(gpio, bank, reg_rdata);
1196         gpio->dcache[i] = ioread32(addr);
1197         aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM);
1198         aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM);
1199         aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM);
1200         aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM);
1201     }
1202 
1203     /* Optionally set up an irqchip if there is an IRQ */
1204     rc = platform_get_irq(pdev, 0);
1205     if (rc > 0) {
1206         struct gpio_irq_chip *girq;
1207 
1208         gpio->irq = rc;
1209         girq = &gpio->chip.irq;
1210         girq->chip = &gpio->irqc;
1211         girq->chip->name = dev_name(&pdev->dev);
1212         girq->chip->irq_ack = aspeed_gpio_irq_ack;
1213         girq->chip->irq_mask = aspeed_gpio_irq_mask;
1214         girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
1215         girq->chip->irq_set_type = aspeed_gpio_set_type;
1216         girq->parent_handler = aspeed_gpio_irq_handler;
1217         girq->num_parents = 1;
1218         girq->parents = devm_kcalloc(&pdev->dev, 1,
1219                          sizeof(*girq->parents),
1220                          GFP_KERNEL);
1221         if (!girq->parents)
1222             return -ENOMEM;
1223         girq->parents[0] = gpio->irq;
1224         girq->default_type = IRQ_TYPE_NONE;
1225         girq->handler = handle_bad_irq;
1226         girq->init_valid_mask = aspeed_init_irq_valid_mask;
1227     }
1228 
1229     gpio->offset_timer =
1230         devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL);
1231     if (!gpio->offset_timer)
1232         return -ENOMEM;
1233 
1234     rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
1235     if (rc < 0)
1236         return rc;
1237 
1238     return 0;
1239 }
1240 
1241 static struct platform_driver aspeed_gpio_driver = {
1242     .driver = {
1243         .name = KBUILD_MODNAME,
1244         .of_match_table = aspeed_gpio_of_table,
1245     },
1246 };
1247 
1248 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe);
1249 
1250 MODULE_DESCRIPTION("Aspeed GPIO Driver");
1251 MODULE_LICENSE("GPL");
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