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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2019 American Megatrends International LLC.
0004  *
0005  * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/hashtable.h>
0012 #include <linux/init.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/spinlock.h>
0018 #include <linux/string.h>
0019 
0020 #define ASPEED_SGPIO_CTRL       0x54
0021 
0022 #define ASPEED_SGPIO_CLK_DIV_MASK   GENMASK(31, 16)
0023 #define ASPEED_SGPIO_ENABLE     BIT(0)
0024 #define ASPEED_SGPIO_PINS_SHIFT     6
0025 
0026 struct aspeed_sgpio_pdata {
0027     const u32 pin_mask;
0028 };
0029 
0030 struct aspeed_sgpio {
0031     struct gpio_chip chip;
0032     struct irq_chip intc;
0033     struct clk *pclk;
0034     raw_spinlock_t lock;
0035     void __iomem *base;
0036     int irq;
0037 };
0038 
0039 struct aspeed_sgpio_bank {
0040     u16    val_regs;
0041     u16    rdata_reg;
0042     u16    irq_regs;
0043     u16    tolerance_regs;
0044     const char  names[4][3];
0045 };
0046 
0047 /*
0048  * Note: The "value" register returns the input value when the GPIO is
0049  *   configured as an input.
0050  *
0051  *   The "rdata" register returns the output value when the GPIO is
0052  *   configured as an output.
0053  */
0054 static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
0055     {
0056         .val_regs = 0x0000,
0057         .rdata_reg = 0x0070,
0058         .irq_regs = 0x0004,
0059         .tolerance_regs = 0x0018,
0060         .names = { "A", "B", "C", "D" },
0061     },
0062     {
0063         .val_regs = 0x001C,
0064         .rdata_reg = 0x0074,
0065         .irq_regs = 0x0020,
0066         .tolerance_regs = 0x0034,
0067         .names = { "E", "F", "G", "H" },
0068     },
0069     {
0070         .val_regs = 0x0038,
0071         .rdata_reg = 0x0078,
0072         .irq_regs = 0x003C,
0073         .tolerance_regs = 0x0050,
0074         .names = { "I", "J", "K", "L" },
0075     },
0076     {
0077         .val_regs = 0x0090,
0078         .rdata_reg = 0x007C,
0079         .irq_regs = 0x0094,
0080         .tolerance_regs = 0x00A8,
0081         .names = { "M", "N", "O", "P" },
0082     },
0083 };
0084 
0085 enum aspeed_sgpio_reg {
0086     reg_val,
0087     reg_rdata,
0088     reg_irq_enable,
0089     reg_irq_type0,
0090     reg_irq_type1,
0091     reg_irq_type2,
0092     reg_irq_status,
0093     reg_tolerance,
0094 };
0095 
0096 #define GPIO_VAL_VALUE      0x00
0097 #define GPIO_IRQ_ENABLE     0x00
0098 #define GPIO_IRQ_TYPE0      0x04
0099 #define GPIO_IRQ_TYPE1      0x08
0100 #define GPIO_IRQ_TYPE2      0x0C
0101 #define GPIO_IRQ_STATUS     0x10
0102 
0103 static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
0104                      const struct aspeed_sgpio_bank *bank,
0105                      const enum aspeed_sgpio_reg reg)
0106 {
0107     switch (reg) {
0108     case reg_val:
0109         return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
0110     case reg_rdata:
0111         return gpio->base + bank->rdata_reg;
0112     case reg_irq_enable:
0113         return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
0114     case reg_irq_type0:
0115         return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
0116     case reg_irq_type1:
0117         return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
0118     case reg_irq_type2:
0119         return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
0120     case reg_irq_status:
0121         return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
0122     case reg_tolerance:
0123         return gpio->base + bank->tolerance_regs;
0124     default:
0125         /* acturally if code runs to here, it's an error case */
0126         BUG();
0127     }
0128 }
0129 
0130 #define GPIO_BANK(x)    ((x) >> 6)
0131 #define GPIO_OFFSET(x)  ((x) & GENMASK(5, 0))
0132 #define GPIO_BIT(x)     BIT(GPIO_OFFSET(x) >> 1)
0133 
0134 static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
0135 {
0136     unsigned int bank;
0137 
0138     bank = GPIO_BANK(offset);
0139 
0140     WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
0141     return &aspeed_sgpio_banks[bank];
0142 }
0143 
0144 static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
0145         unsigned long *valid_mask, unsigned int ngpios)
0146 {
0147     bitmap_set(valid_mask, 0, ngpios);
0148     return 0;
0149 }
0150 
0151 static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
0152         unsigned long *valid_mask, unsigned int ngpios)
0153 {
0154     unsigned int i;
0155 
0156     /* input GPIOs are even bits */
0157     for (i = 0; i < ngpios; i++) {
0158         if (i % 2)
0159             clear_bit(i, valid_mask);
0160     }
0161 }
0162 
0163 static bool aspeed_sgpio_is_input(unsigned int offset)
0164 {
0165     return !(offset % 2);
0166 }
0167 
0168 static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
0169 {
0170     struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
0171     const struct aspeed_sgpio_bank *bank = to_bank(offset);
0172     unsigned long flags;
0173     enum aspeed_sgpio_reg reg;
0174     int rc = 0;
0175 
0176     raw_spin_lock_irqsave(&gpio->lock, flags);
0177 
0178     reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
0179     rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
0180 
0181     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0182 
0183     return rc;
0184 }
0185 
0186 static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
0187 {
0188     struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
0189     const struct aspeed_sgpio_bank *bank = to_bank(offset);
0190     void __iomem *addr_r, *addr_w;
0191     u32 reg = 0;
0192 
0193     if (aspeed_sgpio_is_input(offset))
0194         return -EINVAL;
0195 
0196     /* Since this is an output, read the cached value from rdata, then
0197      * update val. */
0198     addr_r = bank_reg(gpio, bank, reg_rdata);
0199     addr_w = bank_reg(gpio, bank, reg_val);
0200 
0201     reg = ioread32(addr_r);
0202 
0203     if (val)
0204         reg |= GPIO_BIT(offset);
0205     else
0206         reg &= ~GPIO_BIT(offset);
0207 
0208     iowrite32(reg, addr_w);
0209 
0210     return 0;
0211 }
0212 
0213 static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
0214 {
0215     struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
0216     unsigned long flags;
0217 
0218     raw_spin_lock_irqsave(&gpio->lock, flags);
0219 
0220     sgpio_set_value(gc, offset, val);
0221 
0222     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0223 }
0224 
0225 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
0226 {
0227     return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
0228 }
0229 
0230 static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
0231 {
0232     struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
0233     unsigned long flags;
0234     int rc;
0235 
0236     /* No special action is required for setting the direction; we'll
0237      * error-out in sgpio_set_value if this isn't an output GPIO */
0238 
0239     raw_spin_lock_irqsave(&gpio->lock, flags);
0240     rc = sgpio_set_value(gc, offset, val);
0241     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0242 
0243     return rc;
0244 }
0245 
0246 static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
0247 {
0248     return !!aspeed_sgpio_is_input(offset);
0249 }
0250 
0251 static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
0252                     struct aspeed_sgpio **gpio,
0253                     const struct aspeed_sgpio_bank **bank,
0254                     u32 *bit, int *offset)
0255 {
0256     struct aspeed_sgpio *internal;
0257 
0258     *offset = irqd_to_hwirq(d);
0259     internal = irq_data_get_irq_chip_data(d);
0260     WARN_ON(!internal);
0261 
0262     *gpio = internal;
0263     *bank = to_bank(*offset);
0264     *bit = GPIO_BIT(*offset);
0265 }
0266 
0267 static void aspeed_sgpio_irq_ack(struct irq_data *d)
0268 {
0269     const struct aspeed_sgpio_bank *bank;
0270     struct aspeed_sgpio *gpio;
0271     unsigned long flags;
0272     void __iomem *status_addr;
0273     int offset;
0274     u32 bit;
0275 
0276     irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
0277 
0278     status_addr = bank_reg(gpio, bank, reg_irq_status);
0279 
0280     raw_spin_lock_irqsave(&gpio->lock, flags);
0281 
0282     iowrite32(bit, status_addr);
0283 
0284     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0285 }
0286 
0287 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
0288 {
0289     const struct aspeed_sgpio_bank *bank;
0290     struct aspeed_sgpio *gpio;
0291     unsigned long flags;
0292     u32 reg, bit;
0293     void __iomem *addr;
0294     int offset;
0295 
0296     irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
0297     addr = bank_reg(gpio, bank, reg_irq_enable);
0298 
0299     raw_spin_lock_irqsave(&gpio->lock, flags);
0300 
0301     reg = ioread32(addr);
0302     if (set)
0303         reg |= bit;
0304     else
0305         reg &= ~bit;
0306 
0307     iowrite32(reg, addr);
0308 
0309     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0310 }
0311 
0312 static void aspeed_sgpio_irq_mask(struct irq_data *d)
0313 {
0314     aspeed_sgpio_irq_set_mask(d, false);
0315 }
0316 
0317 static void aspeed_sgpio_irq_unmask(struct irq_data *d)
0318 {
0319     aspeed_sgpio_irq_set_mask(d, true);
0320 }
0321 
0322 static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
0323 {
0324     u32 type0 = 0;
0325     u32 type1 = 0;
0326     u32 type2 = 0;
0327     u32 bit, reg;
0328     const struct aspeed_sgpio_bank *bank;
0329     irq_flow_handler_t handler;
0330     struct aspeed_sgpio *gpio;
0331     unsigned long flags;
0332     void __iomem *addr;
0333     int offset;
0334 
0335     irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
0336 
0337     switch (type & IRQ_TYPE_SENSE_MASK) {
0338     case IRQ_TYPE_EDGE_BOTH:
0339         type2 |= bit;
0340         fallthrough;
0341     case IRQ_TYPE_EDGE_RISING:
0342         type0 |= bit;
0343         fallthrough;
0344     case IRQ_TYPE_EDGE_FALLING:
0345         handler = handle_edge_irq;
0346         break;
0347     case IRQ_TYPE_LEVEL_HIGH:
0348         type0 |= bit;
0349         fallthrough;
0350     case IRQ_TYPE_LEVEL_LOW:
0351         type1 |= bit;
0352         handler = handle_level_irq;
0353         break;
0354     default:
0355         return -EINVAL;
0356     }
0357 
0358     raw_spin_lock_irqsave(&gpio->lock, flags);
0359 
0360     addr = bank_reg(gpio, bank, reg_irq_type0);
0361     reg = ioread32(addr);
0362     reg = (reg & ~bit) | type0;
0363     iowrite32(reg, addr);
0364 
0365     addr = bank_reg(gpio, bank, reg_irq_type1);
0366     reg = ioread32(addr);
0367     reg = (reg & ~bit) | type1;
0368     iowrite32(reg, addr);
0369 
0370     addr = bank_reg(gpio, bank, reg_irq_type2);
0371     reg = ioread32(addr);
0372     reg = (reg & ~bit) | type2;
0373     iowrite32(reg, addr);
0374 
0375     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0376 
0377     irq_set_handler_locked(d, handler);
0378 
0379     return 0;
0380 }
0381 
0382 static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
0383 {
0384     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0385     struct irq_chip *ic = irq_desc_get_chip(desc);
0386     struct aspeed_sgpio *data = gpiochip_get_data(gc);
0387     unsigned int i, p;
0388     unsigned long reg;
0389 
0390     chained_irq_enter(ic, desc);
0391 
0392     for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
0393         const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
0394 
0395         reg = ioread32(bank_reg(data, bank, reg_irq_status));
0396 
0397         for_each_set_bit(p, &reg, 32)
0398             generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2);
0399     }
0400 
0401     chained_irq_exit(ic, desc);
0402 }
0403 
0404 static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
0405                    struct platform_device *pdev)
0406 {
0407     int rc, i;
0408     const struct aspeed_sgpio_bank *bank;
0409     struct gpio_irq_chip *irq;
0410 
0411     rc = platform_get_irq(pdev, 0);
0412     if (rc < 0)
0413         return rc;
0414 
0415     gpio->irq = rc;
0416 
0417     /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
0418     for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
0419         bank =  &aspeed_sgpio_banks[i];
0420         /* disable irq enable bits */
0421         iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
0422         /* clear status bits */
0423         iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
0424     }
0425 
0426     gpio->intc.name = dev_name(&pdev->dev);
0427     gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
0428     gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
0429     gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
0430     gpio->intc.irq_set_type = aspeed_sgpio_set_type;
0431 
0432     irq = &gpio->chip.irq;
0433     irq->chip = &gpio->intc;
0434     irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
0435     irq->handler = handle_bad_irq;
0436     irq->default_type = IRQ_TYPE_NONE;
0437     irq->parent_handler = aspeed_sgpio_irq_handler;
0438     irq->parent_handler_data = gpio;
0439     irq->parents = &gpio->irq;
0440     irq->num_parents = 1;
0441 
0442     /* Apply default IRQ settings */
0443     for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
0444         bank = &aspeed_sgpio_banks[i];
0445         /* set falling or level-low irq */
0446         iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
0447         /* trigger type is edge */
0448         iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
0449         /* single edge trigger */
0450         iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
0451     }
0452 
0453     return 0;
0454 }
0455 
0456 static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
0457     .pin_mask = GENMASK(9, 6),
0458 };
0459 
0460 static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
0461                     unsigned int offset, bool enable)
0462 {
0463     struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
0464     unsigned long flags;
0465     void __iomem *reg;
0466     u32 val;
0467 
0468     reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
0469 
0470     raw_spin_lock_irqsave(&gpio->lock, flags);
0471 
0472     val = readl(reg);
0473 
0474     if (enable)
0475         val |= GPIO_BIT(offset);
0476     else
0477         val &= ~GPIO_BIT(offset);
0478 
0479     writel(val, reg);
0480 
0481     raw_spin_unlock_irqrestore(&gpio->lock, flags);
0482 
0483     return 0;
0484 }
0485 
0486 static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
0487                    unsigned long config)
0488 {
0489     unsigned long param = pinconf_to_config_param(config);
0490     u32 arg = pinconf_to_config_argument(config);
0491 
0492     if (param == PIN_CONFIG_PERSIST_STATE)
0493         return aspeed_sgpio_reset_tolerance(chip, offset, arg);
0494 
0495     return -ENOTSUPP;
0496 }
0497 
0498 static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
0499     .pin_mask = GENMASK(10, 6),
0500 };
0501 
0502 static const struct of_device_id aspeed_sgpio_of_table[] = {
0503     { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
0504     { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
0505     { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
0506     {}
0507 };
0508 
0509 MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
0510 
0511 static int __init aspeed_sgpio_probe(struct platform_device *pdev)
0512 {
0513     u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
0514     const struct aspeed_sgpio_pdata *pdata;
0515     struct aspeed_sgpio *gpio;
0516     unsigned long apb_freq;
0517     int rc;
0518 
0519     gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
0520     if (!gpio)
0521         return -ENOMEM;
0522 
0523     gpio->base = devm_platform_ioremap_resource(pdev, 0);
0524     if (IS_ERR(gpio->base))
0525         return PTR_ERR(gpio->base);
0526 
0527     pdata = device_get_match_data(&pdev->dev);
0528     if (!pdata)
0529         return -EINVAL;
0530 
0531     pin_mask = pdata->pin_mask;
0532 
0533     rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
0534     if (rc < 0) {
0535         dev_err(&pdev->dev, "Could not read ngpios property\n");
0536         return -EINVAL;
0537     } else if (nr_gpios % 8) {
0538         dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
0539             nr_gpios);
0540         return -EINVAL;
0541     }
0542 
0543     rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
0544     if (rc < 0) {
0545         dev_err(&pdev->dev, "Could not read bus-frequency property\n");
0546         return -EINVAL;
0547     }
0548 
0549     gpio->pclk = devm_clk_get(&pdev->dev, NULL);
0550     if (IS_ERR(gpio->pclk)) {
0551         dev_err(&pdev->dev, "devm_clk_get failed\n");
0552         return PTR_ERR(gpio->pclk);
0553     }
0554 
0555     apb_freq = clk_get_rate(gpio->pclk);
0556 
0557     /*
0558      * From the datasheet,
0559      *  SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
0560      *  period = 2 * (GPIO254[31:16] + 1) / PCLK
0561      *  frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
0562      *  frequency = PCLK / (2 * (GPIO254[31:16] + 1))
0563      *  frequency * 2 * (GPIO254[31:16] + 1) = PCLK
0564      *  GPIO254[31:16] = PCLK / (frequency * 2) - 1
0565      */
0566     if (sgpio_freq == 0)
0567         return -EINVAL;
0568 
0569     sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
0570 
0571     if (sgpio_clk_div > (1 << 16) - 1)
0572         return -EINVAL;
0573 
0574     gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
0575     iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
0576           ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
0577 
0578     raw_spin_lock_init(&gpio->lock);
0579 
0580     gpio->chip.parent = &pdev->dev;
0581     gpio->chip.ngpio = nr_gpios * 2;
0582     gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
0583     gpio->chip.direction_input = aspeed_sgpio_dir_in;
0584     gpio->chip.direction_output = aspeed_sgpio_dir_out;
0585     gpio->chip.get_direction = aspeed_sgpio_get_direction;
0586     gpio->chip.request = NULL;
0587     gpio->chip.free = NULL;
0588     gpio->chip.get = aspeed_sgpio_get;
0589     gpio->chip.set = aspeed_sgpio_set;
0590     gpio->chip.set_config = aspeed_sgpio_set_config;
0591     gpio->chip.label = dev_name(&pdev->dev);
0592     gpio->chip.base = -1;
0593 
0594     aspeed_sgpio_setup_irqs(gpio, pdev);
0595 
0596     rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
0597     if (rc < 0)
0598         return rc;
0599 
0600     return 0;
0601 }
0602 
0603 static struct platform_driver aspeed_sgpio_driver = {
0604     .driver = {
0605         .name = KBUILD_MODNAME,
0606         .of_match_table = aspeed_sgpio_of_table,
0607     },
0608 };
0609 
0610 module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
0611 MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
0612 MODULE_LICENSE("GPL");
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