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0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/kernel.h>
0014 #include <linux/module.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/gpio/driver.h>
0017 #include <linux/platform_data/gpio/gpio-amd-fch.h>
0018 #include <linux/spinlock.h>
0019
0020 #define AMD_FCH_MMIO_BASE 0xFED80000
0021 #define AMD_FCH_GPIO_BANK0_BASE 0x1500
0022 #define AMD_FCH_GPIO_SIZE 0x0300
0023
0024 #define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23)
0025 #define AMD_FCH_GPIO_FLAG_WRITE BIT(22)
0026 #define AMD_FCH_GPIO_FLAG_READ BIT(16)
0027
0028 static const struct resource amd_fch_gpio_iores =
0029 DEFINE_RES_MEM_NAMED(
0030 AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE,
0031 AMD_FCH_GPIO_SIZE,
0032 "amd-fch-gpio-iomem");
0033
0034 struct amd_fch_gpio_priv {
0035 struct gpio_chip gc;
0036 void __iomem *base;
0037 struct amd_fch_gpio_pdata *pdata;
0038 spinlock_t lock;
0039 };
0040
0041 static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
0042 unsigned int gpio)
0043 {
0044 return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);
0045 }
0046
0047 static int amd_fch_gpio_direction_input(struct gpio_chip *gc,
0048 unsigned int offset)
0049 {
0050 unsigned long flags;
0051 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
0052 void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
0053
0054 spin_lock_irqsave(&priv->lock, flags);
0055 writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
0056 spin_unlock_irqrestore(&priv->lock, flags);
0057
0058 return 0;
0059 }
0060
0061 static int amd_fch_gpio_direction_output(struct gpio_chip *gc,
0062 unsigned int gpio, int value)
0063 {
0064 unsigned long flags;
0065 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
0066 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
0067 u32 val;
0068
0069 spin_lock_irqsave(&priv->lock, flags);
0070
0071 val = readl_relaxed(ptr);
0072 if (value)
0073 val |= AMD_FCH_GPIO_FLAG_WRITE;
0074 else
0075 val &= ~AMD_FCH_GPIO_FLAG_WRITE;
0076
0077 writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
0078
0079 spin_unlock_irqrestore(&priv->lock, flags);
0080
0081 return 0;
0082 }
0083
0084 static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
0085 {
0086 int ret;
0087 unsigned long flags;
0088 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
0089 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
0090
0091 spin_lock_irqsave(&priv->lock, flags);
0092 ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
0093 spin_unlock_irqrestore(&priv->lock, flags);
0094
0095 return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
0096 }
0097
0098 static void amd_fch_gpio_set(struct gpio_chip *gc,
0099 unsigned int gpio, int value)
0100 {
0101 unsigned long flags;
0102 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
0103 void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
0104 u32 mask;
0105
0106 spin_lock_irqsave(&priv->lock, flags);
0107
0108 mask = readl_relaxed(ptr);
0109 if (value)
0110 mask |= AMD_FCH_GPIO_FLAG_WRITE;
0111 else
0112 mask &= ~AMD_FCH_GPIO_FLAG_WRITE;
0113 writel_relaxed(mask, ptr);
0114
0115 spin_unlock_irqrestore(&priv->lock, flags);
0116 }
0117
0118 static int amd_fch_gpio_get(struct gpio_chip *gc,
0119 unsigned int offset)
0120 {
0121 unsigned long flags;
0122 int ret;
0123 struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
0124 void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
0125
0126 spin_lock_irqsave(&priv->lock, flags);
0127 ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ);
0128 spin_unlock_irqrestore(&priv->lock, flags);
0129
0130 return ret;
0131 }
0132
0133 static int amd_fch_gpio_request(struct gpio_chip *chip,
0134 unsigned int gpio_pin)
0135 {
0136 return 0;
0137 }
0138
0139 static int amd_fch_gpio_probe(struct platform_device *pdev)
0140 {
0141 struct amd_fch_gpio_priv *priv;
0142 struct amd_fch_gpio_pdata *pdata;
0143
0144 pdata = dev_get_platdata(&pdev->dev);
0145 if (!pdata) {
0146 dev_err(&pdev->dev, "no platform_data\n");
0147 return -ENOENT;
0148 }
0149
0150 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0151 if (!priv)
0152 return -ENOMEM;
0153
0154 priv->pdata = pdata;
0155
0156 priv->gc.owner = THIS_MODULE;
0157 priv->gc.parent = &pdev->dev;
0158 priv->gc.label = dev_name(&pdev->dev);
0159 priv->gc.ngpio = priv->pdata->gpio_num;
0160 priv->gc.names = priv->pdata->gpio_names;
0161 priv->gc.base = -1;
0162 priv->gc.request = amd_fch_gpio_request;
0163 priv->gc.direction_input = amd_fch_gpio_direction_input;
0164 priv->gc.direction_output = amd_fch_gpio_direction_output;
0165 priv->gc.get_direction = amd_fch_gpio_get_direction;
0166 priv->gc.get = amd_fch_gpio_get;
0167 priv->gc.set = amd_fch_gpio_set;
0168
0169 spin_lock_init(&priv->lock);
0170
0171 priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores);
0172 if (IS_ERR(priv->base))
0173 return PTR_ERR(priv->base);
0174
0175 platform_set_drvdata(pdev, priv);
0176
0177 return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
0178 }
0179
0180 static struct platform_driver amd_fch_gpio_driver = {
0181 .driver = {
0182 .name = AMD_FCH_GPIO_DRIVER_NAME,
0183 },
0184 .probe = amd_fch_gpio_probe,
0185 };
0186
0187 module_platform_driver(amd_fch_gpio_driver);
0188
0189 MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
0190 MODULE_DESCRIPTION("AMD G-series FCH GPIO driver");
0191 MODULE_LICENSE("GPL");
0192 MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME);
