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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2011-2012 Avionic Design GmbH
0004  */
0005 
0006 #include <linux/gpio/driver.h>
0007 #include <linux/i2c.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/mod_devicetable.h>
0010 #include <linux/module.h>
0011 #include <linux/property.h>
0012 #include <linux/seq_file.h>
0013 #include <linux/slab.h>
0014 
0015 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
0016 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
0017 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
0018 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
0019 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
0020 
0021 struct adnp {
0022     struct i2c_client *client;
0023     struct gpio_chip gpio;
0024     unsigned int reg_shift;
0025 
0026     struct mutex i2c_lock;
0027     struct mutex irq_lock;
0028 
0029     u8 *irq_enable;
0030     u8 *irq_level;
0031     u8 *irq_rise;
0032     u8 *irq_fall;
0033     u8 *irq_high;
0034     u8 *irq_low;
0035 };
0036 
0037 static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
0038 {
0039     int err;
0040 
0041     err = i2c_smbus_read_byte_data(adnp->client, offset);
0042     if (err < 0) {
0043         dev_err(adnp->gpio.parent, "%s failed: %d\n",
0044             "i2c_smbus_read_byte_data()", err);
0045         return err;
0046     }
0047 
0048     *value = err;
0049     return 0;
0050 }
0051 
0052 static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
0053 {
0054     int err;
0055 
0056     err = i2c_smbus_write_byte_data(adnp->client, offset, value);
0057     if (err < 0) {
0058         dev_err(adnp->gpio.parent, "%s failed: %d\n",
0059             "i2c_smbus_write_byte_data()", err);
0060         return err;
0061     }
0062 
0063     return 0;
0064 }
0065 
0066 static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
0067 {
0068     struct adnp *adnp = gpiochip_get_data(chip);
0069     unsigned int reg = offset >> adnp->reg_shift;
0070     unsigned int pos = offset & 7;
0071     u8 value;
0072     int err;
0073 
0074     err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
0075     if (err < 0)
0076         return err;
0077 
0078     return (value & BIT(pos)) ? 1 : 0;
0079 }
0080 
0081 static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
0082 {
0083     unsigned int reg = offset >> adnp->reg_shift;
0084     unsigned int pos = offset & 7;
0085     int err;
0086     u8 val;
0087 
0088     err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
0089     if (err < 0)
0090         return;
0091 
0092     if (value)
0093         val |= BIT(pos);
0094     else
0095         val &= ~BIT(pos);
0096 
0097     adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
0098 }
0099 
0100 static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0101 {
0102     struct adnp *adnp = gpiochip_get_data(chip);
0103 
0104     mutex_lock(&adnp->i2c_lock);
0105     __adnp_gpio_set(adnp, offset, value);
0106     mutex_unlock(&adnp->i2c_lock);
0107 }
0108 
0109 static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0110 {
0111     struct adnp *adnp = gpiochip_get_data(chip);
0112     unsigned int reg = offset >> adnp->reg_shift;
0113     unsigned int pos = offset & 7;
0114     u8 value;
0115     int err;
0116 
0117     mutex_lock(&adnp->i2c_lock);
0118 
0119     err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
0120     if (err < 0)
0121         goto out;
0122 
0123     value &= ~BIT(pos);
0124 
0125     err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
0126     if (err < 0)
0127         goto out;
0128 
0129     err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
0130     if (err < 0)
0131         goto out;
0132 
0133     if (value & BIT(pos)) {
0134         err = -EPERM;
0135         goto out;
0136     }
0137 
0138     err = 0;
0139 
0140 out:
0141     mutex_unlock(&adnp->i2c_lock);
0142     return err;
0143 }
0144 
0145 static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
0146                       int value)
0147 {
0148     struct adnp *adnp = gpiochip_get_data(chip);
0149     unsigned int reg = offset >> adnp->reg_shift;
0150     unsigned int pos = offset & 7;
0151     int err;
0152     u8 val;
0153 
0154     mutex_lock(&adnp->i2c_lock);
0155 
0156     err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
0157     if (err < 0)
0158         goto out;
0159 
0160     val |= BIT(pos);
0161 
0162     err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
0163     if (err < 0)
0164         goto out;
0165 
0166     err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
0167     if (err < 0)
0168         goto out;
0169 
0170     if (!(val & BIT(pos))) {
0171         err = -EPERM;
0172         goto out;
0173     }
0174 
0175     __adnp_gpio_set(adnp, offset, value);
0176     err = 0;
0177 
0178 out:
0179     mutex_unlock(&adnp->i2c_lock);
0180     return err;
0181 }
0182 
0183 static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0184 {
0185     struct adnp *adnp = gpiochip_get_data(chip);
0186     unsigned int num_regs = 1 << adnp->reg_shift, i, j;
0187     int err;
0188 
0189     for (i = 0; i < num_regs; i++) {
0190         u8 ddr, plr, ier, isr;
0191 
0192         mutex_lock(&adnp->i2c_lock);
0193 
0194         err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
0195         if (err < 0)
0196             goto unlock;
0197 
0198         err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
0199         if (err < 0)
0200             goto unlock;
0201 
0202         err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
0203         if (err < 0)
0204             goto unlock;
0205 
0206         err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
0207         if (err < 0)
0208             goto unlock;
0209 
0210         mutex_unlock(&adnp->i2c_lock);
0211 
0212         for (j = 0; j < 8; j++) {
0213             unsigned int bit = (i << adnp->reg_shift) + j;
0214             const char *direction = "input ";
0215             const char *level = "low ";
0216             const char *interrupt = "disabled";
0217             const char *pending = "";
0218 
0219             if (ddr & BIT(j))
0220                 direction = "output";
0221 
0222             if (plr & BIT(j))
0223                 level = "high";
0224 
0225             if (ier & BIT(j))
0226                 interrupt = "enabled ";
0227 
0228             if (isr & BIT(j))
0229                 pending = "pending";
0230 
0231             seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
0232                    direction, level, interrupt, pending);
0233         }
0234     }
0235 
0236     return;
0237 
0238 unlock:
0239     mutex_unlock(&adnp->i2c_lock);
0240 }
0241 
0242 static irqreturn_t adnp_irq(int irq, void *data)
0243 {
0244     struct adnp *adnp = data;
0245     unsigned int num_regs, i;
0246 
0247     num_regs = 1 << adnp->reg_shift;
0248 
0249     for (i = 0; i < num_regs; i++) {
0250         unsigned int base = i << adnp->reg_shift, bit;
0251         u8 changed, level, isr, ier;
0252         unsigned long pending;
0253         int err;
0254 
0255         mutex_lock(&adnp->i2c_lock);
0256 
0257         err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
0258         if (err < 0) {
0259             mutex_unlock(&adnp->i2c_lock);
0260             continue;
0261         }
0262 
0263         err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
0264         if (err < 0) {
0265             mutex_unlock(&adnp->i2c_lock);
0266             continue;
0267         }
0268 
0269         err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
0270         if (err < 0) {
0271             mutex_unlock(&adnp->i2c_lock);
0272             continue;
0273         }
0274 
0275         mutex_unlock(&adnp->i2c_lock);
0276 
0277         /* determine pins that changed levels */
0278         changed = level ^ adnp->irq_level[i];
0279 
0280         /* compute edge-triggered interrupts */
0281         pending = changed & ((adnp->irq_fall[i] & ~level) |
0282                      (adnp->irq_rise[i] & level));
0283 
0284         /* add in level-triggered interrupts */
0285         pending |= (adnp->irq_high[i] & level) |
0286                (adnp->irq_low[i] & ~level);
0287 
0288         /* mask out non-pending and disabled interrupts */
0289         pending &= isr & ier;
0290 
0291         for_each_set_bit(bit, &pending, 8) {
0292             unsigned int child_irq;
0293             child_irq = irq_find_mapping(adnp->gpio.irq.domain,
0294                              base + bit);
0295             handle_nested_irq(child_irq);
0296         }
0297     }
0298 
0299     return IRQ_HANDLED;
0300 }
0301 
0302 static void adnp_irq_mask(struct irq_data *d)
0303 {
0304     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0305     struct adnp *adnp = gpiochip_get_data(gc);
0306     unsigned int reg = d->hwirq >> adnp->reg_shift;
0307     unsigned int pos = d->hwirq & 7;
0308 
0309     adnp->irq_enable[reg] &= ~BIT(pos);
0310 }
0311 
0312 static void adnp_irq_unmask(struct irq_data *d)
0313 {
0314     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0315     struct adnp *adnp = gpiochip_get_data(gc);
0316     unsigned int reg = d->hwirq >> adnp->reg_shift;
0317     unsigned int pos = d->hwirq & 7;
0318 
0319     adnp->irq_enable[reg] |= BIT(pos);
0320 }
0321 
0322 static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
0323 {
0324     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0325     struct adnp *adnp = gpiochip_get_data(gc);
0326     unsigned int reg = d->hwirq >> adnp->reg_shift;
0327     unsigned int pos = d->hwirq & 7;
0328 
0329     if (type & IRQ_TYPE_EDGE_RISING)
0330         adnp->irq_rise[reg] |= BIT(pos);
0331     else
0332         adnp->irq_rise[reg] &= ~BIT(pos);
0333 
0334     if (type & IRQ_TYPE_EDGE_FALLING)
0335         adnp->irq_fall[reg] |= BIT(pos);
0336     else
0337         adnp->irq_fall[reg] &= ~BIT(pos);
0338 
0339     if (type & IRQ_TYPE_LEVEL_HIGH)
0340         adnp->irq_high[reg] |= BIT(pos);
0341     else
0342         adnp->irq_high[reg] &= ~BIT(pos);
0343 
0344     if (type & IRQ_TYPE_LEVEL_LOW)
0345         adnp->irq_low[reg] |= BIT(pos);
0346     else
0347         adnp->irq_low[reg] &= ~BIT(pos);
0348 
0349     return 0;
0350 }
0351 
0352 static void adnp_irq_bus_lock(struct irq_data *d)
0353 {
0354     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0355     struct adnp *adnp = gpiochip_get_data(gc);
0356 
0357     mutex_lock(&adnp->irq_lock);
0358 }
0359 
0360 static void adnp_irq_bus_unlock(struct irq_data *d)
0361 {
0362     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0363     struct adnp *adnp = gpiochip_get_data(gc);
0364     unsigned int num_regs = 1 << adnp->reg_shift, i;
0365 
0366     mutex_lock(&adnp->i2c_lock);
0367 
0368     for (i = 0; i < num_regs; i++)
0369         adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
0370 
0371     mutex_unlock(&adnp->i2c_lock);
0372     mutex_unlock(&adnp->irq_lock);
0373 }
0374 
0375 static struct irq_chip adnp_irq_chip = {
0376     .name = "gpio-adnp",
0377     .irq_mask = adnp_irq_mask,
0378     .irq_unmask = adnp_irq_unmask,
0379     .irq_set_type = adnp_irq_set_type,
0380     .irq_bus_lock = adnp_irq_bus_lock,
0381     .irq_bus_sync_unlock = adnp_irq_bus_unlock,
0382 };
0383 
0384 static int adnp_irq_setup(struct adnp *adnp)
0385 {
0386     unsigned int num_regs = 1 << adnp->reg_shift, i;
0387     struct gpio_chip *chip = &adnp->gpio;
0388     int err;
0389 
0390     mutex_init(&adnp->irq_lock);
0391 
0392     /*
0393      * Allocate memory to keep track of the current level and trigger
0394      * modes of the interrupts. To avoid multiple allocations, a single
0395      * large buffer is allocated and pointers are setup to point at the
0396      * corresponding offsets. For consistency, the layout of the buffer
0397      * is chosen to match the register layout of the hardware in that
0398      * each segment contains the corresponding bits for all interrupts.
0399      */
0400     adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6,
0401                     GFP_KERNEL);
0402     if (!adnp->irq_enable)
0403         return -ENOMEM;
0404 
0405     adnp->irq_level = adnp->irq_enable + (num_regs * 1);
0406     adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
0407     adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
0408     adnp->irq_high = adnp->irq_enable + (num_regs * 4);
0409     adnp->irq_low = adnp->irq_enable + (num_regs * 5);
0410 
0411     for (i = 0; i < num_regs; i++) {
0412         /*
0413          * Read the initial level of all pins to allow the emulation
0414          * of edge triggered interrupts.
0415          */
0416         err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
0417         if (err < 0)
0418             return err;
0419 
0420         /* disable all interrupts */
0421         err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
0422         if (err < 0)
0423             return err;
0424 
0425         adnp->irq_enable[i] = 0x00;
0426     }
0427 
0428     err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
0429                     NULL, adnp_irq,
0430                     IRQF_TRIGGER_RISING | IRQF_ONESHOT,
0431                     dev_name(chip->parent), adnp);
0432     if (err != 0) {
0433         dev_err(chip->parent, "can't request IRQ#%d: %d\n",
0434             adnp->client->irq, err);
0435         return err;
0436     }
0437 
0438     return 0;
0439 }
0440 
0441 static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios,
0442                bool is_irq_controller)
0443 {
0444     struct gpio_chip *chip = &adnp->gpio;
0445     int err;
0446 
0447     adnp->reg_shift = get_count_order(num_gpios) - 3;
0448 
0449     chip->direction_input = adnp_gpio_direction_input;
0450     chip->direction_output = adnp_gpio_direction_output;
0451     chip->get = adnp_gpio_get;
0452     chip->set = adnp_gpio_set;
0453     chip->can_sleep = true;
0454 
0455     if (IS_ENABLED(CONFIG_DEBUG_FS))
0456         chip->dbg_show = adnp_gpio_dbg_show;
0457 
0458     chip->base = -1;
0459     chip->ngpio = num_gpios;
0460     chip->label = adnp->client->name;
0461     chip->parent = &adnp->client->dev;
0462     chip->owner = THIS_MODULE;
0463 
0464     if (is_irq_controller) {
0465         struct gpio_irq_chip *girq;
0466 
0467         err = adnp_irq_setup(adnp);
0468         if (err)
0469             return err;
0470 
0471         girq = &chip->irq;
0472         girq->chip = &adnp_irq_chip;
0473         /* This will let us handle the parent IRQ in the driver */
0474         girq->parent_handler = NULL;
0475         girq->num_parents = 0;
0476         girq->parents = NULL;
0477         girq->default_type = IRQ_TYPE_NONE;
0478         girq->handler = handle_simple_irq;
0479         girq->threaded = true;
0480     }
0481 
0482     err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
0483     if (err)
0484         return err;
0485 
0486     return 0;
0487 }
0488 
0489 static int adnp_i2c_probe(struct i2c_client *client)
0490 {
0491     struct device *dev = &client->dev;
0492     struct adnp *adnp;
0493     u32 num_gpios;
0494     int err;
0495 
0496     err = device_property_read_u32(dev, "nr-gpios", &num_gpios);
0497     if (err < 0)
0498         return err;
0499 
0500     adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
0501     if (!adnp)
0502         return -ENOMEM;
0503 
0504     mutex_init(&adnp->i2c_lock);
0505     adnp->client = client;
0506 
0507     err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller"));
0508     if (err)
0509         return err;
0510 
0511     i2c_set_clientdata(client, adnp);
0512 
0513     return 0;
0514 }
0515 
0516 static const struct i2c_device_id adnp_i2c_id[] = {
0517     { "gpio-adnp" },
0518     { },
0519 };
0520 MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
0521 
0522 static const struct of_device_id adnp_of_match[] = {
0523     { .compatible = "ad,gpio-adnp", },
0524     { },
0525 };
0526 MODULE_DEVICE_TABLE(of, adnp_of_match);
0527 
0528 static struct i2c_driver adnp_i2c_driver = {
0529     .driver = {
0530         .name = "gpio-adnp",
0531         .of_match_table = adnp_of_match,
0532     },
0533     .probe_new = adnp_i2c_probe,
0534     .id_table = adnp_i2c_id,
0535 };
0536 module_i2c_driver(adnp_i2c_driver);
0537 
0538 MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
0539 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
0540 MODULE_LICENSE("GPL");
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