drivers/gpio/gpio-104-dio-48e.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * GPIO driver for the ACCES 104-DIO-48E series
0004  * Copyright (C) 2016 William Breathitt Gray
0005  *
0006  * This driver supports the following ACCES devices: 104-DIO-48E and
0007  * 104-DIO-24E.
0008  */
0009 #include <linux/bits.h>
0010 #include <linux/device.h>
0011 #include <linux/errno.h>
0012 #include <linux/gpio/driver.h>
0013 #include <linux/io.h>
0014 #include <linux/ioport.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irqdesc.h>
0017 #include <linux/isa.h>
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/moduleparam.h>
0021 #include <linux/spinlock.h>
0022 #include <linux/types.h>
0023
0024 #include "gpio-i8255.h"
0025
0026 MODULE_IMPORT_NS(I8255);
0027
0028 #define DIO48E_EXTENT 16
0029 #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
0030
0031 static unsigned int base[MAX_NUM_DIO48E];
0032 static unsigned int num_dio48e;
0033 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
0034 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
0035
0036 static unsigned int irq[MAX_NUM_DIO48E];
0037 module_param_hw_array(irq, uint, irq, NULL, 0);
0038 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
0039
0040 #define DIO48E_NUM_PPI 2
0041
0042 /**
0043  * struct dio48e_reg - device register structure
0044  * @ppi:        Programmable Peripheral Interface groups
0045  * @enable_buffer:  Enable/Disable Buffer groups
0046  * @unused1:        Unused
0047  * @enable_interrupt:   Write: Enable Interrupt
0048  *          Read: Disable Interrupt
0049  * @unused2:        Unused
0050  * @enable_counter: Write: Enable Counter/Timer Addressing
0051  *          Read: Disable Counter/Timer Addressing
0052  * @unused3:        Unused
0053  * @clear_interrupt:    Clear Interrupt
0054  */
0055 struct dio48e_reg {
0056     struct i8255 ppi[DIO48E_NUM_PPI];
0057     u8 enable_buffer[DIO48E_NUM_PPI];
0058     u8 unused1;
0059     u8 enable_interrupt;
0060     u8 unused2;
0061     u8 enable_counter;
0062     u8 unused3;
0063     u8 clear_interrupt;
0064 };
0065
0066 /**
0067  * struct dio48e_gpio - GPIO device private data structure
0068  * @chip:       instance of the gpio_chip
0069  * @ppi_state:      PPI device states
0070  * @lock:       synchronization lock to prevent I/O race conditions
0071  * @reg:        I/O address offset for the device registers
0072  * @irq_mask:       I/O bits affected by interrupts
0073  */
0074 struct dio48e_gpio {
0075     struct gpio_chip chip;
0076     struct i8255_state ppi_state[DIO48E_NUM_PPI];
0077     raw_spinlock_t lock;
0078     struct dio48e_reg __iomem *reg;
0079     unsigned char irq_mask;
0080 };
0081
0082 static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0083 {
0084     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0085
0086     if (i8255_get_direction(dio48egpio->ppi_state, offset))
0087         return GPIO_LINE_DIRECTION_IN;
0088
0089     return GPIO_LINE_DIRECTION_OUT;
0090 }
0091
0092 static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0093 {
0094     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0095
0096     i8255_direction_input(dio48egpio->reg->ppi, dio48egpio->ppi_state,
0097                   offset);
0098
0099     return 0;
0100 }
0101
0102 static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
0103                     int value)
0104 {
0105     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0106
0107     i8255_direction_output(dio48egpio->reg->ppi, dio48egpio->ppi_state,
0108                    offset, value);
0109
0110     return 0;
0111 }
0112
0113 static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset)
0114 {
0115     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0116
0117     return i8255_get(dio48egpio->reg->ppi, offset);
0118 }
0119
0120 static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
0121     unsigned long *bits)
0122 {
0123     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0124
0125     i8255_get_multiple(dio48egpio->reg->ppi, mask, bits, chip->ngpio);
0126
0127     return 0;
0128 }
0129
0130 static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
0131 {
0132     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0133
0134     i8255_set(dio48egpio->reg->ppi, dio48egpio->ppi_state, offset, value);
0135 }
0136
0137 static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
0138     unsigned long *mask, unsigned long *bits)
0139 {
0140     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0141
0142     i8255_set_multiple(dio48egpio->reg->ppi, dio48egpio->ppi_state, mask,
0143                bits, chip->ngpio);
0144 }
0145
0146 static void dio48e_irq_ack(struct irq_data *data)
0147 {
0148 }
0149
0150 static void dio48e_irq_mask(struct irq_data *data)
0151 {
0152     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0153     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0154     const unsigned long offset = irqd_to_hwirq(data);
0155     unsigned long flags;
0156
0157     /* only bit 3 on each respective Port C supports interrupts */
0158     if (offset != 19 && offset != 43)
0159         return;
0160
0161     raw_spin_lock_irqsave(&dio48egpio->lock, flags);
0162
0163     if (offset == 19)
0164         dio48egpio->irq_mask &= ~BIT(0);
0165     else
0166         dio48egpio->irq_mask &= ~BIT(1);
0167     gpiochip_disable_irq(chip, offset);
0168
0169     if (!dio48egpio->irq_mask)
0170         /* disable interrupts */
0171         ioread8(&dio48egpio->reg->enable_interrupt);
0172
0173     raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
0174 }
0175
0176 static void dio48e_irq_unmask(struct irq_data *data)
0177 {
0178     struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
0179     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
0180     const unsigned long offset = irqd_to_hwirq(data);
0181     unsigned long flags;
0182
0183     /* only bit 3 on each respective Port C supports interrupts */
0184     if (offset != 19 && offset != 43)
0185         return;
0186
0187     raw_spin_lock_irqsave(&dio48egpio->lock, flags);
0188
0189     if (!dio48egpio->irq_mask) {
0190         /* enable interrupts */
0191         iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
0192         iowrite8(0x00, &dio48egpio->reg->enable_interrupt);
0193     }
0194
0195     gpiochip_enable_irq(chip, offset);
0196     if (offset == 19)
0197         dio48egpio->irq_mask |= BIT(0);
0198     else
0199         dio48egpio->irq_mask |= BIT(1);
0200
0201     raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
0202 }
0203
0204 static int dio48e_irq_set_type(struct irq_data *data, unsigned int flow_type)
0205 {
0206     const unsigned long offset = irqd_to_hwirq(data);
0207
0208     /* only bit 3 on each respective Port C supports interrupts */
0209     if (offset != 19 && offset != 43)
0210         return -EINVAL;
0211
0212     if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
0213         return -EINVAL;
0214
0215     return 0;
0216 }
0217
0218 static const struct irq_chip dio48e_irqchip = {
0219     .name = "104-dio-48e",
0220     .irq_ack = dio48e_irq_ack,
0221     .irq_mask = dio48e_irq_mask,
0222     .irq_unmask = dio48e_irq_unmask,
0223     .irq_set_type = dio48e_irq_set_type,
0224     .flags = IRQCHIP_IMMUTABLE,
0225     GPIOCHIP_IRQ_RESOURCE_HELPERS,
0226 };
0227
0228 static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
0229 {
0230     struct dio48e_gpio *const dio48egpio = dev_id;
0231     struct gpio_chip *const chip = &dio48egpio->chip;
0232     const unsigned long irq_mask = dio48egpio->irq_mask;
0233     unsigned long gpio;
0234
0235     for_each_set_bit(gpio, &irq_mask, 2)
0236         generic_handle_domain_irq(chip->irq.domain,
0237                       19 + gpio*24);
0238
0239     raw_spin_lock(&dio48egpio->lock);
0240
0241     iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
0242
0243     raw_spin_unlock(&dio48egpio->lock);
0244
0245     return IRQ_HANDLED;
0246 }
0247
0248 #define DIO48E_NGPIO 48
0249 static const char *dio48e_names[DIO48E_NGPIO] = {
0250     "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
0251     "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
0252     "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
0253     "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
0254     "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
0255     "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
0256     "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
0257     "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
0258     "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
0259     "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
0260     "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
0261     "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
0262     "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
0263     "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
0264     "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
0265     "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
0266 };
0267
0268 static int dio48e_irq_init_hw(struct gpio_chip *gc)
0269 {
0270     struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
0271
0272     /* Disable IRQ by default */
0273     ioread8(&dio48egpio->reg->enable_interrupt);
0274
0275     return 0;
0276 }
0277
0278 static void dio48e_init_ppi(struct i8255 __iomem *const ppi,
0279                 struct i8255_state *const ppi_state)
0280 {
0281     const unsigned long ngpio = 24;
0282     const unsigned long mask = GENMASK(ngpio - 1, 0);
0283     const unsigned long bits = 0;
0284     unsigned long i;
0285
0286     /* Initialize all GPIO to output 0 */
0287     for (i = 0; i < DIO48E_NUM_PPI; i++) {
0288         i8255_mode0_output(&ppi[i]);
0289         i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
0290     }
0291 }
0292
0293 static int dio48e_probe(struct device *dev, unsigned int id)
0294 {
0295     struct dio48e_gpio *dio48egpio;
0296     const char *const name = dev_name(dev);
0297     struct gpio_irq_chip *girq;
0298     int err;
0299
0300     dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
0301     if (!dio48egpio)
0302         return -ENOMEM;
0303
0304     if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
0305         dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
0306             base[id], base[id] + DIO48E_EXTENT);
0307         return -EBUSY;
0308     }
0309
0310     dio48egpio->reg = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
0311     if (!dio48egpio->reg)
0312         return -ENOMEM;
0313
0314     dio48egpio->chip.label = name;
0315     dio48egpio->chip.parent = dev;
0316     dio48egpio->chip.owner = THIS_MODULE;
0317     dio48egpio->chip.base = -1;
0318     dio48egpio->chip.ngpio = DIO48E_NGPIO;
0319     dio48egpio->chip.names = dio48e_names;
0320     dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
0321     dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
0322     dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
0323     dio48egpio->chip.get = dio48e_gpio_get;
0324     dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
0325     dio48egpio->chip.set = dio48e_gpio_set;
0326     dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
0327
0328     girq = &dio48egpio->chip.irq;
0329     gpio_irq_chip_set_chip(girq, &dio48e_irqchip);
0330     /* This will let us handle the parent IRQ in the driver */
0331     girq->parent_handler = NULL;
0332     girq->num_parents = 0;
0333     girq->parents = NULL;
0334     girq->default_type = IRQ_TYPE_NONE;
0335     girq->handler = handle_edge_irq;
0336     girq->init_hw = dio48e_irq_init_hw;
0337
0338     raw_spin_lock_init(&dio48egpio->lock);
0339
0340     i8255_state_init(dio48egpio->ppi_state, DIO48E_NUM_PPI);
0341     dio48e_init_ppi(dio48egpio->reg->ppi, dio48egpio->ppi_state);
0342
0343     err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
0344     if (err) {
0345         dev_err(dev, "GPIO registering failed (%d)\n", err);
0346         return err;
0347     }
0348
0349     err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
0350         dio48egpio);
0351     if (err) {
0352         dev_err(dev, "IRQ handler registering failed (%d)\n", err);
0353         return err;
0354     }
0355
0356     return 0;
0357 }
0358
0359 static struct isa_driver dio48e_driver = {
0360     .probe = dio48e_probe,
0361     .driver = {
0362         .name = "104-dio-48e"
0363     },
0364 };
0365 module_isa_driver(dio48e_driver, num_dio48e);
0366
0367 MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
0368 MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
0369 MODULE_LICENSE("GPL v2");