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0001 // SPDX-License-Identifier: GPL-2.0+
0002 // Copyright 2018 IBM Corp
0003 /*
0004  * A FSI master controller, using a simple GPIO bit-banging interface
0005  */
0006 
0007 #include <linux/crc4.h>
0008 #include <linux/delay.h>
0009 #include <linux/device.h>
0010 #include <linux/fsi.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/io.h>
0013 #include <linux/irqflags.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018 #include <linux/regmap.h>
0019 #include <linux/firmware.h>
0020 #include <linux/gpio/aspeed.h>
0021 #include <linux/mfd/syscon.h>
0022 #include <linux/of_address.h>
0023 #include <linux/genalloc.h>
0024 
0025 #include "fsi-master.h"
0026 #include "cf-fsi-fw.h"
0027 
0028 #define FW_FILE_NAME    "cf-fsi-fw.bin"
0029 
0030 /* Common SCU based coprocessor control registers */
0031 #define SCU_COPRO_CTRL          0x100
0032 #define   SCU_COPRO_RESET           0x00000002
0033 #define   SCU_COPRO_CLK_EN          0x00000001
0034 
0035 /* AST2500 specific ones */
0036 #define SCU_2500_COPRO_SEG0     0x104
0037 #define SCU_2500_COPRO_SEG1     0x108
0038 #define SCU_2500_COPRO_SEG2     0x10c
0039 #define SCU_2500_COPRO_SEG3     0x110
0040 #define SCU_2500_COPRO_SEG4     0x114
0041 #define SCU_2500_COPRO_SEG5     0x118
0042 #define SCU_2500_COPRO_SEG6     0x11c
0043 #define SCU_2500_COPRO_SEG7     0x120
0044 #define SCU_2500_COPRO_SEG8     0x124
0045 #define   SCU_2500_COPRO_SEG_SWAP       0x00000001
0046 #define SCU_2500_COPRO_CACHE_CTL    0x128
0047 #define   SCU_2500_COPRO_CACHE_EN       0x00000001
0048 #define   SCU_2500_COPRO_SEG0_CACHE_EN      0x00000002
0049 #define   SCU_2500_COPRO_SEG1_CACHE_EN      0x00000004
0050 #define   SCU_2500_COPRO_SEG2_CACHE_EN      0x00000008
0051 #define   SCU_2500_COPRO_SEG3_CACHE_EN      0x00000010
0052 #define   SCU_2500_COPRO_SEG4_CACHE_EN      0x00000020
0053 #define   SCU_2500_COPRO_SEG5_CACHE_EN      0x00000040
0054 #define   SCU_2500_COPRO_SEG6_CACHE_EN      0x00000080
0055 #define   SCU_2500_COPRO_SEG7_CACHE_EN      0x00000100
0056 #define   SCU_2500_COPRO_SEG8_CACHE_EN      0x00000200
0057 
0058 #define SCU_2400_COPRO_SEG0     0x104
0059 #define SCU_2400_COPRO_SEG2     0x108
0060 #define SCU_2400_COPRO_SEG4     0x10c
0061 #define SCU_2400_COPRO_SEG6     0x110
0062 #define SCU_2400_COPRO_SEG8     0x114
0063 #define   SCU_2400_COPRO_SEG_SWAP       0x80000000
0064 #define SCU_2400_COPRO_CACHE_CTL    0x118
0065 #define   SCU_2400_COPRO_CACHE_EN       0x00000001
0066 #define   SCU_2400_COPRO_SEG0_CACHE_EN      0x00000002
0067 #define   SCU_2400_COPRO_SEG2_CACHE_EN      0x00000004
0068 #define   SCU_2400_COPRO_SEG4_CACHE_EN      0x00000008
0069 #define   SCU_2400_COPRO_SEG6_CACHE_EN      0x00000010
0070 #define   SCU_2400_COPRO_SEG8_CACHE_EN      0x00000020
0071 
0072 /* CVIC registers */
0073 #define CVIC_EN_REG         0x10
0074 #define CVIC_TRIG_REG           0x18
0075 
0076 /*
0077  * System register base address (needed for configuring the
0078  * coldfire maps)
0079  */
0080 #define SYSREG_BASE         0x1e600000
0081 
0082 /* Amount of SRAM required */
0083 #define SRAM_SIZE           0x1000
0084 
0085 #define LAST_ADDR_INVALID       0x1
0086 
0087 struct fsi_master_acf {
0088     struct fsi_master   master;
0089     struct device       *dev;
0090     struct regmap       *scu;
0091     struct mutex        lock;   /* mutex for command ordering */
0092     struct gpio_desc    *gpio_clk;
0093     struct gpio_desc    *gpio_data;
0094     struct gpio_desc    *gpio_trans;    /* Voltage translator */
0095     struct gpio_desc    *gpio_enable;   /* FSI enable */
0096     struct gpio_desc    *gpio_mux;  /* Mux control */
0097     uint16_t        gpio_clk_vreg;
0098     uint16_t        gpio_clk_dreg;
0099     uint16_t            gpio_dat_vreg;
0100     uint16_t            gpio_dat_dreg;
0101     uint16_t            gpio_tra_vreg;
0102     uint16_t            gpio_tra_dreg;
0103     uint8_t         gpio_clk_bit;
0104     uint8_t         gpio_dat_bit;
0105     uint8_t         gpio_tra_bit;
0106     uint32_t        cf_mem_addr;
0107     size_t          cf_mem_size;
0108     void __iomem        *cf_mem;
0109     void __iomem        *cvic;
0110     struct gen_pool     *sram_pool;
0111     void __iomem        *sram;
0112     bool            is_ast2500;
0113     bool            external_mode;
0114     bool            trace_enabled;
0115     uint32_t        last_addr;
0116     uint8_t         t_send_delay;
0117     uint8_t         t_echo_delay;
0118     uint32_t        cvic_sw_irq;
0119 };
0120 #define to_fsi_master_acf(m) container_of(m, struct fsi_master_acf, master)
0121 
0122 struct fsi_msg {
0123     uint64_t    msg;
0124     uint8_t     bits;
0125 };
0126 
0127 #define CREATE_TRACE_POINTS
0128 #include <trace/events/fsi_master_ast_cf.h>
0129 
0130 static void msg_push_bits(struct fsi_msg *msg, uint64_t data, int bits)
0131 {
0132     msg->msg <<= bits;
0133     msg->msg |= data & ((1ull << bits) - 1);
0134     msg->bits += bits;
0135 }
0136 
0137 static void msg_push_crc(struct fsi_msg *msg)
0138 {
0139     uint8_t crc;
0140     int top;
0141 
0142     top = msg->bits & 0x3;
0143 
0144     /* start bit, and any non-aligned top bits */
0145     crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
0146 
0147     /* aligned bits */
0148     crc = crc4(crc, msg->msg, msg->bits - top);
0149 
0150     msg_push_bits(msg, crc, 4);
0151 }
0152 
0153 static void msg_finish_cmd(struct fsi_msg *cmd)
0154 {
0155     /* Left align message */
0156     cmd->msg <<= (64 - cmd->bits);
0157 }
0158 
0159 static bool check_same_address(struct fsi_master_acf *master, int id,
0160                    uint32_t addr)
0161 {
0162     /* this will also handle LAST_ADDR_INVALID */
0163     return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));
0164 }
0165 
0166 static bool check_relative_address(struct fsi_master_acf *master, int id,
0167                    uint32_t addr, uint32_t *rel_addrp)
0168 {
0169     uint32_t last_addr = master->last_addr;
0170     int32_t rel_addr;
0171 
0172     if (last_addr == LAST_ADDR_INVALID)
0173         return false;
0174 
0175     /* We may be in 23-bit addressing mode, which uses the id as the
0176      * top two address bits. So, if we're referencing a different ID,
0177      * use absolute addresses.
0178      */
0179     if (((last_addr >> 21) & 0x3) != id)
0180         return false;
0181 
0182     /* remove the top two bits from any 23-bit addressing */
0183     last_addr &= (1 << 21) - 1;
0184 
0185     /* We know that the addresses are limited to 21 bits, so this won't
0186      * overflow the signed rel_addr */
0187     rel_addr = addr - last_addr;
0188     if (rel_addr > 255 || rel_addr < -256)
0189         return false;
0190 
0191     *rel_addrp = (uint32_t)rel_addr;
0192 
0193     return true;
0194 }
0195 
0196 static void last_address_update(struct fsi_master_acf *master,
0197                 int id, bool valid, uint32_t addr)
0198 {
0199     if (!valid)
0200         master->last_addr = LAST_ADDR_INVALID;
0201     else
0202         master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);
0203 }
0204 
0205 /*
0206  * Encode an Absolute/Relative/Same Address command
0207  */
0208 static void build_ar_command(struct fsi_master_acf *master,
0209                  struct fsi_msg *cmd, uint8_t id,
0210                  uint32_t addr, size_t size,
0211                  const void *data)
0212 {
0213     int i, addr_bits, opcode_bits;
0214     bool write = !!data;
0215     uint8_t ds, opcode;
0216     uint32_t rel_addr;
0217 
0218     cmd->bits = 0;
0219     cmd->msg = 0;
0220 
0221     /* we have 21 bits of address max */
0222     addr &= ((1 << 21) - 1);
0223 
0224     /* cmd opcodes are variable length - SAME_AR is only two bits */
0225     opcode_bits = 3;
0226 
0227     if (check_same_address(master, id, addr)) {
0228         /* we still address the byte offset within the word */
0229         addr_bits = 2;
0230         opcode_bits = 2;
0231         opcode = FSI_CMD_SAME_AR;
0232         trace_fsi_master_acf_cmd_same_addr(master);
0233 
0234     } else if (check_relative_address(master, id, addr, &rel_addr)) {
0235         /* 8 bits plus sign */
0236         addr_bits = 9;
0237         addr = rel_addr;
0238         opcode = FSI_CMD_REL_AR;
0239         trace_fsi_master_acf_cmd_rel_addr(master, rel_addr);
0240 
0241     } else {
0242         addr_bits = 21;
0243         opcode = FSI_CMD_ABS_AR;
0244         trace_fsi_master_acf_cmd_abs_addr(master, addr);
0245     }
0246 
0247     /*
0248      * The read/write size is encoded in the lower bits of the address
0249      * (as it must be naturally-aligned), and the following ds bit.
0250      *
0251      *  size    addr:1  addr:0  ds
0252      *  1   x   x   0
0253      *  2   x   0   1
0254      *  4   0   1   1
0255      *
0256      */
0257     ds = size > 1 ? 1 : 0;
0258     addr &= ~(size - 1);
0259     if (size == 4)
0260         addr |= 1;
0261 
0262     msg_push_bits(cmd, id, 2);
0263     msg_push_bits(cmd, opcode, opcode_bits);
0264     msg_push_bits(cmd, write ? 0 : 1, 1);
0265     msg_push_bits(cmd, addr, addr_bits);
0266     msg_push_bits(cmd, ds, 1);
0267     for (i = 0; write && i < size; i++)
0268         msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
0269 
0270     msg_push_crc(cmd);
0271     msg_finish_cmd(cmd);
0272 }
0273 
0274 static void build_dpoll_command(struct fsi_msg *cmd, uint8_t slave_id)
0275 {
0276     cmd->bits = 0;
0277     cmd->msg = 0;
0278 
0279     msg_push_bits(cmd, slave_id, 2);
0280     msg_push_bits(cmd, FSI_CMD_DPOLL, 3);
0281     msg_push_crc(cmd);
0282     msg_finish_cmd(cmd);
0283 }
0284 
0285 static void build_epoll_command(struct fsi_msg *cmd, uint8_t slave_id)
0286 {
0287     cmd->bits = 0;
0288     cmd->msg = 0;
0289 
0290     msg_push_bits(cmd, slave_id, 2);
0291     msg_push_bits(cmd, FSI_CMD_EPOLL, 3);
0292     msg_push_crc(cmd);
0293     msg_finish_cmd(cmd);
0294 }
0295 
0296 static void build_term_command(struct fsi_msg *cmd, uint8_t slave_id)
0297 {
0298     cmd->bits = 0;
0299     cmd->msg = 0;
0300 
0301     msg_push_bits(cmd, slave_id, 2);
0302     msg_push_bits(cmd, FSI_CMD_TERM, 6);
0303     msg_push_crc(cmd);
0304     msg_finish_cmd(cmd);
0305 }
0306 
0307 static int do_copro_command(struct fsi_master_acf *master, uint32_t op)
0308 {
0309     uint32_t timeout = 10000000;
0310     uint8_t stat;
0311 
0312     trace_fsi_master_acf_copro_command(master, op);
0313 
0314     /* Send command */
0315     iowrite32be(op, master->sram + CMD_STAT_REG);
0316 
0317     /* Ring doorbell if any */
0318     if (master->cvic)
0319         iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
0320 
0321     /* Wait for status to indicate completion (or error) */
0322     do {
0323         if (timeout-- == 0) {
0324             dev_warn(master->dev,
0325                  "Timeout waiting for coprocessor completion\n");
0326             return -ETIMEDOUT;
0327         }
0328         stat = ioread8(master->sram + CMD_STAT_REG);
0329     } while(stat < STAT_COMPLETE || stat == 0xff);
0330 
0331     if (stat == STAT_COMPLETE)
0332         return 0;
0333     switch(stat) {
0334     case STAT_ERR_INVAL_CMD:
0335         return -EINVAL;
0336     case STAT_ERR_INVAL_IRQ:
0337         return -EIO;
0338     case STAT_ERR_MTOE:
0339         return -ESHUTDOWN;
0340     }
0341     return -ENXIO;
0342 }
0343 
0344 static int clock_zeros(struct fsi_master_acf *master, int count)
0345 {
0346     while (count) {
0347         int rc, lcnt = min(count, 255);
0348 
0349         rc = do_copro_command(master,
0350                       CMD_IDLE_CLOCKS | (lcnt << CMD_REG_CLEN_SHIFT));
0351         if (rc)
0352             return rc;
0353         count -= lcnt;
0354     }
0355     return 0;
0356 }
0357 
0358 static int send_request(struct fsi_master_acf *master, struct fsi_msg *cmd,
0359             unsigned int resp_bits)
0360 {
0361     uint32_t op;
0362 
0363     trace_fsi_master_acf_send_request(master, cmd, resp_bits);
0364 
0365     /* Store message into SRAM */
0366     iowrite32be((cmd->msg >> 32), master->sram + CMD_DATA);
0367     iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4);
0368 
0369     op = CMD_COMMAND;
0370     op |= cmd->bits << CMD_REG_CLEN_SHIFT;
0371     if (resp_bits)
0372         op |= resp_bits << CMD_REG_RLEN_SHIFT;
0373 
0374     return do_copro_command(master, op);
0375 }
0376 
0377 static int read_copro_response(struct fsi_master_acf *master, uint8_t size,
0378                    uint32_t *response, u8 *tag)
0379 {
0380     uint8_t rtag = ioread8(master->sram + STAT_RTAG) & 0xf;
0381     uint8_t rcrc = ioread8(master->sram + STAT_RCRC) & 0xf;
0382     uint32_t rdata = 0;
0383     uint32_t crc;
0384     uint8_t ack;
0385 
0386     *tag = ack = rtag & 3;
0387 
0388     /* we have a whole message now; check CRC */
0389     crc = crc4(0, 1, 1);
0390     crc = crc4(crc, rtag, 4);
0391     if (ack == FSI_RESP_ACK && size) {
0392         rdata = ioread32be(master->sram + RSP_DATA);
0393         crc = crc4(crc, rdata, size);
0394         if (response)
0395             *response = rdata;
0396     }
0397     crc = crc4(crc, rcrc, 4);
0398 
0399     trace_fsi_master_acf_copro_response(master, rtag, rcrc, rdata, crc == 0);
0400 
0401     if (crc) {
0402         /*
0403          * Check if it's all 1's or all 0's, that probably means
0404          * the host is off
0405          */
0406         if ((rtag == 0xf && rcrc == 0xf) || (rtag == 0 && rcrc == 0))
0407             return -ENODEV;
0408         dev_dbg(master->dev, "Bad response CRC !\n");
0409         return -EAGAIN;
0410     }
0411     return 0;
0412 }
0413 
0414 static int send_term(struct fsi_master_acf *master, uint8_t slave)
0415 {
0416     struct fsi_msg cmd;
0417     uint8_t tag;
0418     int rc;
0419 
0420     build_term_command(&cmd, slave);
0421 
0422     rc = send_request(master, &cmd, 0);
0423     if (rc) {
0424         dev_warn(master->dev, "Error %d sending term\n", rc);
0425         return rc;
0426     }
0427 
0428     rc = read_copro_response(master, 0, NULL, &tag);
0429     if (rc < 0) {
0430         dev_err(master->dev,
0431                 "TERM failed; lost communication with slave\n");
0432         return -EIO;
0433     } else if (tag != FSI_RESP_ACK) {
0434         dev_err(master->dev, "TERM failed; response %d\n", tag);
0435         return -EIO;
0436     }
0437     return 0;
0438 }
0439 
0440 static void dump_ucode_trace(struct fsi_master_acf *master)
0441 {
0442     char trbuf[52];
0443     char *p;
0444     int i;
0445 
0446     dev_dbg(master->dev,
0447         "CMDSTAT:%08x RTAG=%02x RCRC=%02x RDATA=%02x #INT=%08x\n",
0448         ioread32be(master->sram + CMD_STAT_REG),
0449         ioread8(master->sram + STAT_RTAG),
0450         ioread8(master->sram + STAT_RCRC),
0451         ioread32be(master->sram + RSP_DATA),
0452         ioread32be(master->sram + INT_CNT));
0453 
0454     for (i = 0; i < 512; i++) {
0455         uint8_t v;
0456         if ((i % 16) == 0)
0457             p = trbuf;
0458         v = ioread8(master->sram + TRACEBUF + i);
0459         p += sprintf(p, "%02x ", v);
0460         if (((i % 16) == 15) || v == TR_END)
0461             dev_dbg(master->dev, "%s\n", trbuf);
0462         if (v == TR_END)
0463             break;
0464     }
0465 }
0466 
0467 static int handle_response(struct fsi_master_acf *master,
0468                uint8_t slave, uint8_t size, void *data)
0469 {
0470     int busy_count = 0, rc;
0471     int crc_err_retries = 0;
0472     struct fsi_msg cmd;
0473     uint32_t response;
0474     uint8_t tag;
0475 retry:
0476     rc = read_copro_response(master, size, &response, &tag);
0477 
0478     /* Handle retries on CRC errors */
0479     if (rc == -EAGAIN) {
0480         /* Too many retries ? */
0481         if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) {
0482             /*
0483              * Pass it up as a -EIO otherwise upper level will retry
0484              * the whole command which isn't what we want here.
0485              */
0486             rc = -EIO;
0487             goto bail;
0488         }
0489         trace_fsi_master_acf_crc_rsp_error(master, crc_err_retries);
0490         if (master->trace_enabled)
0491             dump_ucode_trace(master);
0492         rc = clock_zeros(master, FSI_MASTER_EPOLL_CLOCKS);
0493         if (rc) {
0494             dev_warn(master->dev,
0495                  "Error %d clocking zeros for E_POLL\n", rc);
0496             return rc;
0497         }
0498         build_epoll_command(&cmd, slave);
0499         rc = send_request(master, &cmd, size);
0500         if (rc) {
0501             dev_warn(master->dev, "Error %d sending E_POLL\n", rc);
0502             return -EIO;
0503         }
0504         goto retry;
0505     }
0506     if (rc)
0507         return rc;
0508 
0509     switch (tag) {
0510     case FSI_RESP_ACK:
0511         if (size && data) {
0512             if (size == 32)
0513                 *(__be32 *)data = cpu_to_be32(response);
0514             else if (size == 16)
0515                 *(__be16 *)data = cpu_to_be16(response);
0516             else
0517                 *(u8 *)data = response;
0518         }
0519         break;
0520     case FSI_RESP_BUSY:
0521         /*
0522          * Its necessary to clock slave before issuing
0523          * d-poll, not indicated in the hardware protocol
0524          * spec. < 20 clocks causes slave to hang, 21 ok.
0525          */
0526         dev_dbg(master->dev, "Busy, retrying...\n");
0527         if (master->trace_enabled)
0528             dump_ucode_trace(master);
0529         rc = clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS);
0530         if (rc) {
0531             dev_warn(master->dev,
0532                  "Error %d clocking zeros for D_POLL\n", rc);
0533             break;
0534         }
0535         if (busy_count++ < FSI_MASTER_MAX_BUSY) {
0536             build_dpoll_command(&cmd, slave);
0537             rc = send_request(master, &cmd, size);
0538             if (rc) {
0539                 dev_warn(master->dev, "Error %d sending D_POLL\n", rc);
0540                 break;
0541             }
0542             goto retry;
0543         }
0544         dev_dbg(master->dev,
0545             "ERR slave is stuck in busy state, issuing TERM\n");
0546         send_term(master, slave);
0547         rc = -EIO;
0548         break;
0549 
0550     case FSI_RESP_ERRA:
0551         dev_dbg(master->dev, "ERRA received\n");
0552         if (master->trace_enabled)
0553             dump_ucode_trace(master);
0554         rc = -EIO;
0555         break;
0556     case FSI_RESP_ERRC:
0557         dev_dbg(master->dev, "ERRC received\n");
0558         if (master->trace_enabled)
0559             dump_ucode_trace(master);
0560         rc = -EAGAIN;
0561         break;
0562     }
0563  bail:
0564     if (busy_count > 0) {
0565         trace_fsi_master_acf_poll_response_busy(master, busy_count);
0566     }
0567 
0568     return rc;
0569 }
0570 
0571 static int fsi_master_acf_xfer(struct fsi_master_acf *master, uint8_t slave,
0572                    struct fsi_msg *cmd, size_t resp_len, void *resp)
0573 {
0574     int rc = -EAGAIN, retries = 0;
0575 
0576     resp_len <<= 3;
0577     while ((retries++) < FSI_CRC_ERR_RETRIES) {
0578         rc = send_request(master, cmd, resp_len);
0579         if (rc) {
0580             if (rc != -ESHUTDOWN)
0581                 dev_warn(master->dev, "Error %d sending command\n", rc);
0582             break;
0583         }
0584         rc = handle_response(master, slave, resp_len, resp);
0585         if (rc != -EAGAIN)
0586             break;
0587         rc = -EIO;
0588         dev_dbg(master->dev, "ECRC retry %d\n", retries);
0589 
0590         /* Pace it a bit before retry */
0591         msleep(1);
0592     }
0593 
0594     return rc;
0595 }
0596 
0597 static int fsi_master_acf_read(struct fsi_master *_master, int link,
0598                    uint8_t id, uint32_t addr, void *val,
0599                    size_t size)
0600 {
0601     struct fsi_master_acf *master = to_fsi_master_acf(_master);
0602     struct fsi_msg cmd;
0603     int rc;
0604 
0605     if (link != 0)
0606         return -ENODEV;
0607 
0608     mutex_lock(&master->lock);
0609     dev_dbg(master->dev, "read id %d addr %x size %zd\n", id, addr, size);
0610     build_ar_command(master, &cmd, id, addr, size, NULL);
0611     rc = fsi_master_acf_xfer(master, id, &cmd, size, val);
0612     last_address_update(master, id, rc == 0, addr);
0613     if (rc)
0614         dev_dbg(master->dev, "read id %d addr 0x%08x err: %d\n",
0615             id, addr, rc);
0616     mutex_unlock(&master->lock);
0617 
0618     return rc;
0619 }
0620 
0621 static int fsi_master_acf_write(struct fsi_master *_master, int link,
0622                 uint8_t id, uint32_t addr, const void *val,
0623                 size_t size)
0624 {
0625     struct fsi_master_acf *master = to_fsi_master_acf(_master);
0626     struct fsi_msg cmd;
0627     int rc;
0628 
0629     if (link != 0)
0630         return -ENODEV;
0631 
0632     mutex_lock(&master->lock);
0633     build_ar_command(master, &cmd, id, addr, size, val);
0634     dev_dbg(master->dev, "write id %d addr %x size %zd raw_data: %08x\n",
0635         id, addr, size, *(uint32_t *)val);
0636     rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
0637     last_address_update(master, id, rc == 0, addr);
0638     if (rc)
0639         dev_dbg(master->dev, "write id %d addr 0x%08x err: %d\n",
0640             id, addr, rc);
0641     mutex_unlock(&master->lock);
0642 
0643     return rc;
0644 }
0645 
0646 static int fsi_master_acf_term(struct fsi_master *_master,
0647                    int link, uint8_t id)
0648 {
0649     struct fsi_master_acf *master = to_fsi_master_acf(_master);
0650     struct fsi_msg cmd;
0651     int rc;
0652 
0653     if (link != 0)
0654         return -ENODEV;
0655 
0656     mutex_lock(&master->lock);
0657     build_term_command(&cmd, id);
0658     dev_dbg(master->dev, "term id %d\n", id);
0659     rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
0660     last_address_update(master, id, false, 0);
0661     mutex_unlock(&master->lock);
0662 
0663     return rc;
0664 }
0665 
0666 static int fsi_master_acf_break(struct fsi_master *_master, int link)
0667 {
0668     struct fsi_master_acf *master = to_fsi_master_acf(_master);
0669     int rc;
0670 
0671     if (link != 0)
0672         return -ENODEV;
0673 
0674     mutex_lock(&master->lock);
0675     if (master->external_mode) {
0676         mutex_unlock(&master->lock);
0677         return -EBUSY;
0678     }
0679     dev_dbg(master->dev, "sending BREAK\n");
0680     rc = do_copro_command(master, CMD_BREAK);
0681     last_address_update(master, 0, false, 0);
0682     mutex_unlock(&master->lock);
0683 
0684     /* Wait for logic reset to take effect */
0685     udelay(200);
0686 
0687     return rc;
0688 }
0689 
0690 static void reset_cf(struct fsi_master_acf *master)
0691 {
0692     regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_RESET);
0693     usleep_range(20,20);
0694     regmap_write(master->scu, SCU_COPRO_CTRL, 0);
0695     usleep_range(20,20);
0696 }
0697 
0698 static void start_cf(struct fsi_master_acf *master)
0699 {
0700     regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_CLK_EN);
0701 }
0702 
0703 static void setup_ast2500_cf_maps(struct fsi_master_acf *master)
0704 {
0705     /*
0706      * Note about byteswap setting: the bus is wired backwards,
0707      * so setting the byteswap bit actually makes the ColdFire
0708      * work "normally" for a BE processor, ie, put the MSB in
0709      * the lowest address byte.
0710      *
0711      * We thus need to set the bit for our main memory which
0712      * contains our program code. We create two mappings for
0713      * the register, one with each setting.
0714      *
0715      * Segments 2 and 3 has a "swapped" mapping (BE)
0716      * and 6 and 7 have a non-swapped mapping (LE) which allows
0717      * us to avoid byteswapping register accesses since the
0718      * registers are all LE.
0719      */
0720 
0721     /* Setup segment 0 to our memory region */
0722     regmap_write(master->scu, SCU_2500_COPRO_SEG0, master->cf_mem_addr |
0723              SCU_2500_COPRO_SEG_SWAP);
0724 
0725     /* Segments 2 and 3 to sysregs with byteswap (for SRAM) */
0726     regmap_write(master->scu, SCU_2500_COPRO_SEG2, SYSREG_BASE |
0727              SCU_2500_COPRO_SEG_SWAP);
0728     regmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 |
0729              SCU_2500_COPRO_SEG_SWAP);
0730 
0731     /* And segment 6 and 7 to sysregs no byteswap */
0732     regmap_write(master->scu, SCU_2500_COPRO_SEG6, SYSREG_BASE);
0733     regmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000);
0734 
0735     /* Memory cachable, regs and SRAM not cachable */
0736     regmap_write(master->scu, SCU_2500_COPRO_CACHE_CTL,
0737              SCU_2500_COPRO_SEG0_CACHE_EN | SCU_2500_COPRO_CACHE_EN);
0738 }
0739 
0740 static void setup_ast2400_cf_maps(struct fsi_master_acf *master)
0741 {
0742     /* Setup segment 0 to our memory region */
0743     regmap_write(master->scu, SCU_2400_COPRO_SEG0, master->cf_mem_addr |
0744              SCU_2400_COPRO_SEG_SWAP);
0745 
0746     /* Segments 2 to sysregs with byteswap (for SRAM) */
0747     regmap_write(master->scu, SCU_2400_COPRO_SEG2, SYSREG_BASE |
0748              SCU_2400_COPRO_SEG_SWAP);
0749 
0750     /* And segment 6 to sysregs no byteswap */
0751     regmap_write(master->scu, SCU_2400_COPRO_SEG6, SYSREG_BASE);
0752 
0753     /* Memory cachable, regs and SRAM not cachable */
0754     regmap_write(master->scu, SCU_2400_COPRO_CACHE_CTL,
0755              SCU_2400_COPRO_SEG0_CACHE_EN | SCU_2400_COPRO_CACHE_EN);
0756 }
0757 
0758 static void setup_common_fw_config(struct fsi_master_acf *master,
0759                    void __iomem *base)
0760 {
0761     iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR);
0762     iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR);
0763     iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR);
0764     iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR);
0765     iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR);
0766     iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR);
0767     iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT);
0768     iowrite8(master->gpio_dat_bit, base + HDR_DATA_GPIO_BIT);
0769     iowrite8(master->gpio_tra_bit, base + HDR_TRANS_GPIO_BIT);
0770 }
0771 
0772 static void setup_ast2500_fw_config(struct fsi_master_acf *master)
0773 {
0774     void __iomem *base = master->cf_mem + HDR_OFFSET;
0775 
0776     setup_common_fw_config(master, base);
0777     iowrite32be(FW_CONTROL_USE_STOP, base + HDR_FW_CONTROL);
0778 }
0779 
0780 static void setup_ast2400_fw_config(struct fsi_master_acf *master)
0781 {
0782     void __iomem *base = master->cf_mem + HDR_OFFSET;
0783 
0784     setup_common_fw_config(master, base);
0785     iowrite32be(FW_CONTROL_CONT_CLOCK|FW_CONTROL_DUMMY_RD, base + HDR_FW_CONTROL);
0786 }
0787 
0788 static int setup_gpios_for_copro(struct fsi_master_acf *master)
0789 {
0790 
0791     int rc;
0792 
0793     /* This aren't under ColdFire control, just set them up appropriately */
0794     gpiod_direction_output(master->gpio_mux, 1);
0795     gpiod_direction_output(master->gpio_enable, 1);
0796 
0797     /* Those are under ColdFire control, let it configure them */
0798     rc = aspeed_gpio_copro_grab_gpio(master->gpio_clk, &master->gpio_clk_vreg,
0799                      &master->gpio_clk_dreg, &master->gpio_clk_bit);
0800     if (rc) {
0801         dev_err(master->dev, "failed to assign clock gpio to coprocessor\n");
0802         return rc;
0803     }
0804     rc = aspeed_gpio_copro_grab_gpio(master->gpio_data, &master->gpio_dat_vreg,
0805                      &master->gpio_dat_dreg, &master->gpio_dat_bit);
0806     if (rc) {
0807         dev_err(master->dev, "failed to assign data gpio to coprocessor\n");
0808         aspeed_gpio_copro_release_gpio(master->gpio_clk);
0809         return rc;
0810     }
0811     rc = aspeed_gpio_copro_grab_gpio(master->gpio_trans, &master->gpio_tra_vreg,
0812                      &master->gpio_tra_dreg, &master->gpio_tra_bit);
0813     if (rc) {
0814         dev_err(master->dev, "failed to assign trans gpio to coprocessor\n");
0815         aspeed_gpio_copro_release_gpio(master->gpio_clk);
0816         aspeed_gpio_copro_release_gpio(master->gpio_data);
0817         return rc;
0818     }
0819     return 0;
0820 }
0821 
0822 static void release_copro_gpios(struct fsi_master_acf *master)
0823 {
0824     aspeed_gpio_copro_release_gpio(master->gpio_clk);
0825     aspeed_gpio_copro_release_gpio(master->gpio_data);
0826     aspeed_gpio_copro_release_gpio(master->gpio_trans);
0827 }
0828 
0829 static int load_copro_firmware(struct fsi_master_acf *master)
0830 {
0831     const struct firmware *fw;
0832     uint16_t sig = 0, wanted_sig;
0833     const u8 *data;
0834     size_t size = 0;
0835     int rc;
0836 
0837     /* Get the binary */
0838     rc = request_firmware(&fw, FW_FILE_NAME, master->dev);
0839     if (rc) {
0840         dev_err(
0841             master->dev, "Error %d to load firmware '%s' !\n",
0842             rc, FW_FILE_NAME);
0843         return rc;
0844     }
0845 
0846     /* Which image do we want ? (shared vs. split clock/data GPIOs) */
0847     if (master->gpio_clk_vreg == master->gpio_dat_vreg)
0848         wanted_sig = SYS_SIG_SHARED;
0849     else
0850         wanted_sig = SYS_SIG_SPLIT;
0851     dev_dbg(master->dev, "Looking for image sig %04x\n", wanted_sig);
0852 
0853     /* Try to find it */
0854     for (data = fw->data; data < (fw->data + fw->size);) {
0855         sig = be16_to_cpup((__be16 *)(data + HDR_OFFSET + HDR_SYS_SIG));
0856         size = be32_to_cpup((__be32 *)(data + HDR_OFFSET + HDR_FW_SIZE));
0857         if (sig == wanted_sig)
0858             break;
0859         data += size;
0860     }
0861     if (sig != wanted_sig) {
0862         dev_err(master->dev, "Failed to locate image sig %04x in FW blob\n",
0863             wanted_sig);
0864         rc = -ENODEV;
0865         goto release_fw;
0866     }
0867     if (size > master->cf_mem_size) {
0868         dev_err(master->dev, "FW size (%zd) bigger than memory reserve (%zd)\n",
0869             fw->size, master->cf_mem_size);
0870         rc = -ENOMEM;
0871     } else {
0872         memcpy_toio(master->cf_mem, data, size);
0873     }
0874 
0875 release_fw:
0876     release_firmware(fw);
0877     return rc;
0878 }
0879 
0880 static int check_firmware_image(struct fsi_master_acf *master)
0881 {
0882     uint32_t fw_vers, fw_api, fw_options;
0883 
0884     fw_vers = ioread16be(master->cf_mem + HDR_OFFSET + HDR_FW_VERS);
0885     fw_api = ioread16be(master->cf_mem + HDR_OFFSET + HDR_API_VERS);
0886     fw_options = ioread32be(master->cf_mem + HDR_OFFSET + HDR_FW_OPTIONS);
0887     master->trace_enabled = !!(fw_options & FW_OPTION_TRACE_EN);
0888 
0889     /* Check version and signature */
0890     dev_info(master->dev, "ColdFire initialized, firmware v%d API v%d.%d (trace %s)\n",
0891          fw_vers, fw_api >> 8, fw_api & 0xff,
0892          master->trace_enabled ? "enabled" : "disabled");
0893 
0894     if ((fw_api >> 8) != API_VERSION_MAJ) {
0895         dev_err(master->dev, "Unsupported coprocessor API version !\n");
0896         return -ENODEV;
0897     }
0898 
0899     return 0;
0900 }
0901 
0902 static int copro_enable_sw_irq(struct fsi_master_acf *master)
0903 {
0904     int timeout;
0905     uint32_t val;
0906 
0907     /*
0908      * Enable coprocessor interrupt input. I've had problems getting the
0909      * value to stick, so try in a loop
0910      */
0911     for (timeout = 0; timeout < 10; timeout++) {
0912         iowrite32(0x2, master->cvic + CVIC_EN_REG);
0913         val = ioread32(master->cvic + CVIC_EN_REG);
0914         if (val & 2)
0915             break;
0916         msleep(1);
0917     }
0918     if (!(val & 2)) {
0919         dev_err(master->dev, "Failed to enable coprocessor interrupt !\n");
0920         return -ENODEV;
0921     }
0922     return 0;
0923 }
0924 
0925 static int fsi_master_acf_setup(struct fsi_master_acf *master)
0926 {
0927     int timeout, rc;
0928     uint32_t val;
0929 
0930     /* Make sure the ColdFire is stopped  */
0931     reset_cf(master);
0932 
0933     /*
0934      * Clear SRAM. This needs to happen before we setup the GPIOs
0935      * as we might start trying to arbitrate as soon as that happens.
0936      */
0937     memset_io(master->sram, 0, SRAM_SIZE);
0938 
0939     /* Configure GPIOs */
0940     rc = setup_gpios_for_copro(master);
0941     if (rc)
0942         return rc;
0943 
0944     /* Load the firmware into the reserved memory */
0945     rc = load_copro_firmware(master);
0946     if (rc)
0947         return rc;
0948 
0949     /* Read signature and check versions */
0950     rc = check_firmware_image(master);
0951     if (rc)
0952         return rc;
0953 
0954     /* Setup coldfire memory map */
0955     if (master->is_ast2500) {
0956         setup_ast2500_cf_maps(master);
0957         setup_ast2500_fw_config(master);
0958     } else {
0959         setup_ast2400_cf_maps(master);
0960         setup_ast2400_fw_config(master);
0961     }
0962 
0963     /* Start the ColdFire */
0964     start_cf(master);
0965 
0966     /* Wait for status register to indicate command completion
0967      * which signals the initialization is complete
0968      */
0969     for (timeout = 0; timeout < 10; timeout++) {
0970         val = ioread8(master->sram + CF_STARTED);
0971         if (val)
0972             break;
0973         msleep(1);
0974     }
0975     if (!val) {
0976         dev_err(master->dev, "Coprocessor startup timeout !\n");
0977         rc = -ENODEV;
0978         goto err;
0979     }
0980 
0981     /* Configure echo & send delay */
0982     iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
0983     iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
0984 
0985     /* Enable SW interrupt to copro if any */
0986     if (master->cvic) {
0987         rc = copro_enable_sw_irq(master);
0988         if (rc)
0989             goto err;
0990     }
0991     return 0;
0992  err:
0993     /* An error occurred, don't leave the coprocessor running */
0994     reset_cf(master);
0995 
0996     /* Release the GPIOs */
0997     release_copro_gpios(master);
0998 
0999     return rc;
1000 }
1001 
1002 
1003 static void fsi_master_acf_terminate(struct fsi_master_acf *master)
1004 {
1005     unsigned long flags;
1006 
1007     /*
1008      * A GPIO arbitration requestion could come in while this is
1009      * happening. To avoid problems, we disable interrupts so it
1010      * cannot preempt us on this CPU
1011      */
1012 
1013     local_irq_save(flags);
1014 
1015     /* Stop the coprocessor */
1016     reset_cf(master);
1017 
1018     /* We mark the copro not-started */
1019     iowrite32(0, master->sram + CF_STARTED);
1020 
1021     /* We mark the ARB register as having given up arbitration to
1022      * deal with a potential race with the arbitration request
1023      */
1024     iowrite8(ARB_ARM_ACK, master->sram + ARB_REG);
1025 
1026     local_irq_restore(flags);
1027 
1028     /* Return the GPIOs to the ARM */
1029     release_copro_gpios(master);
1030 }
1031 
1032 static void fsi_master_acf_setup_external(struct fsi_master_acf *master)
1033 {
1034     /* Setup GPIOs for external FSI master (FSP box) */
1035     gpiod_direction_output(master->gpio_mux, 0);
1036     gpiod_direction_output(master->gpio_trans, 0);
1037     gpiod_direction_output(master->gpio_enable, 1);
1038     gpiod_direction_input(master->gpio_clk);
1039     gpiod_direction_input(master->gpio_data);
1040 }
1041 
1042 static int fsi_master_acf_link_enable(struct fsi_master *_master, int link,
1043                       bool enable)
1044 {
1045     struct fsi_master_acf *master = to_fsi_master_acf(_master);
1046     int rc = -EBUSY;
1047 
1048     if (link != 0)
1049         return -ENODEV;
1050 
1051     mutex_lock(&master->lock);
1052     if (!master->external_mode) {
1053         gpiod_set_value(master->gpio_enable, enable ? 1 : 0);
1054         rc = 0;
1055     }
1056     mutex_unlock(&master->lock);
1057 
1058     return rc;
1059 }
1060 
1061 static int fsi_master_acf_link_config(struct fsi_master *_master, int link,
1062                       u8 t_send_delay, u8 t_echo_delay)
1063 {
1064     struct fsi_master_acf *master = to_fsi_master_acf(_master);
1065 
1066     if (link != 0)
1067         return -ENODEV;
1068 
1069     mutex_lock(&master->lock);
1070     master->t_send_delay = t_send_delay;
1071     master->t_echo_delay = t_echo_delay;
1072     dev_dbg(master->dev, "Changing delays: send=%d echo=%d\n",
1073         t_send_delay, t_echo_delay);
1074     iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
1075     iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
1076     mutex_unlock(&master->lock);
1077 
1078     return 0;
1079 }
1080 
1081 static ssize_t external_mode_show(struct device *dev,
1082                   struct device_attribute *attr, char *buf)
1083 {
1084     struct fsi_master_acf *master = dev_get_drvdata(dev);
1085 
1086     return snprintf(buf, PAGE_SIZE - 1, "%u\n",
1087             master->external_mode ? 1 : 0);
1088 }
1089 
1090 static ssize_t external_mode_store(struct device *dev,
1091         struct device_attribute *attr, const char *buf, size_t count)
1092 {
1093     struct fsi_master_acf *master = dev_get_drvdata(dev);
1094     unsigned long val;
1095     bool external_mode;
1096     int err;
1097 
1098     err = kstrtoul(buf, 0, &val);
1099     if (err)
1100         return err;
1101 
1102     external_mode = !!val;
1103 
1104     mutex_lock(&master->lock);
1105 
1106     if (external_mode == master->external_mode) {
1107         mutex_unlock(&master->lock);
1108         return count;
1109     }
1110 
1111     master->external_mode = external_mode;
1112     if (master->external_mode) {
1113         fsi_master_acf_terminate(master);
1114         fsi_master_acf_setup_external(master);
1115     } else
1116         fsi_master_acf_setup(master);
1117 
1118     mutex_unlock(&master->lock);
1119 
1120     fsi_master_rescan(&master->master);
1121 
1122     return count;
1123 }
1124 
1125 static DEVICE_ATTR(external_mode, 0664,
1126         external_mode_show, external_mode_store);
1127 
1128 static int fsi_master_acf_gpio_request(void *data)
1129 {
1130     struct fsi_master_acf *master = data;
1131     int timeout;
1132     u8 val;
1133 
1134     /* Note: This doesn't require holding out mutex */
1135 
1136     /* Write reqest */
1137     iowrite8(ARB_ARM_REQ, master->sram + ARB_REG);
1138 
1139     /*
1140      * There is a race (which does happen at boot time) when we get an
1141      * arbitration request as we are either about to or just starting
1142      * the coprocessor.
1143      *
1144      * To handle it, we first check if we are running. If not yet we
1145      * check whether the copro is started in the SCU.
1146      *
1147      * If it's not started, we can basically just assume we have arbitration
1148      * and return. Otherwise, we wait normally expecting for the arbitration
1149      * to eventually complete.
1150      */
1151     if (ioread32(master->sram + CF_STARTED) == 0) {
1152         unsigned int reg = 0;
1153 
1154         regmap_read(master->scu, SCU_COPRO_CTRL, &reg);
1155         if (!(reg & SCU_COPRO_CLK_EN))
1156             return 0;
1157     }
1158 
1159     /* Ring doorbell if any */
1160     if (master->cvic)
1161         iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
1162 
1163     for (timeout = 0; timeout < 10000; timeout++) {
1164         val = ioread8(master->sram + ARB_REG);
1165         if (val != ARB_ARM_REQ)
1166             break;
1167         udelay(1);
1168     }
1169 
1170     /* If it failed, override anyway */
1171     if (val != ARB_ARM_ACK)
1172         dev_warn(master->dev, "GPIO request arbitration timeout\n");
1173 
1174     return 0;
1175 }
1176 
1177 static int fsi_master_acf_gpio_release(void *data)
1178 {
1179     struct fsi_master_acf *master = data;
1180 
1181     /* Write release */
1182     iowrite8(0, master->sram + ARB_REG);
1183 
1184     /* Ring doorbell if any */
1185     if (master->cvic)
1186         iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
1187 
1188     return 0;
1189 }
1190 
1191 static void fsi_master_acf_release(struct device *dev)
1192 {
1193     struct fsi_master_acf *master = to_fsi_master_acf(dev_to_fsi_master(dev));
1194 
1195     /* Cleanup, stop coprocessor */
1196     mutex_lock(&master->lock);
1197     fsi_master_acf_terminate(master);
1198     aspeed_gpio_copro_set_ops(NULL, NULL);
1199     mutex_unlock(&master->lock);
1200 
1201     /* Free resources */
1202     gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
1203     of_node_put(dev_of_node(master->dev));
1204 
1205     kfree(master);
1206 }
1207 
1208 static const struct aspeed_gpio_copro_ops fsi_master_acf_gpio_ops = {
1209     .request_access = fsi_master_acf_gpio_request,
1210     .release_access = fsi_master_acf_gpio_release,
1211 };
1212 
1213 static int fsi_master_acf_probe(struct platform_device *pdev)
1214 {
1215     struct device_node *np, *mnode = dev_of_node(&pdev->dev);
1216     struct genpool_data_fixed gpdf;
1217     struct fsi_master_acf *master;
1218     struct gpio_desc *gpio;
1219     struct resource res;
1220     uint32_t cf_mem_align;
1221     int rc;
1222 
1223     master = kzalloc(sizeof(*master), GFP_KERNEL);
1224     if (!master)
1225         return -ENOMEM;
1226 
1227     master->dev = &pdev->dev;
1228     master->master.dev.parent = master->dev;
1229     master->last_addr = LAST_ADDR_INVALID;
1230 
1231     /* AST2400 vs. AST2500 */
1232     master->is_ast2500 = of_device_is_compatible(mnode, "aspeed,ast2500-cf-fsi-master");
1233 
1234     /* Grab the SCU, we'll need to access it to configure the coprocessor */
1235     if (master->is_ast2500)
1236         master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu");
1237     else
1238         master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2400-scu");
1239     if (IS_ERR(master->scu)) {
1240         dev_err(&pdev->dev, "failed to find SCU regmap\n");
1241         rc = PTR_ERR(master->scu);
1242         goto err_free;
1243     }
1244 
1245     /* Grab all the GPIOs we need */
1246     gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
1247     if (IS_ERR(gpio)) {
1248         dev_err(&pdev->dev, "failed to get clock gpio\n");
1249         rc = PTR_ERR(gpio);
1250         goto err_free;
1251     }
1252     master->gpio_clk = gpio;
1253 
1254     gpio = devm_gpiod_get(&pdev->dev, "data", 0);
1255     if (IS_ERR(gpio)) {
1256         dev_err(&pdev->dev, "failed to get data gpio\n");
1257         rc = PTR_ERR(gpio);
1258         goto err_free;
1259     }
1260     master->gpio_data = gpio;
1261 
1262     /* Optional GPIOs */
1263     gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
1264     if (IS_ERR(gpio)) {
1265         dev_err(&pdev->dev, "failed to get trans gpio\n");
1266         rc = PTR_ERR(gpio);
1267         goto err_free;
1268     }
1269     master->gpio_trans = gpio;
1270 
1271     gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
1272     if (IS_ERR(gpio)) {
1273         dev_err(&pdev->dev, "failed to get enable gpio\n");
1274         rc = PTR_ERR(gpio);
1275         goto err_free;
1276     }
1277     master->gpio_enable = gpio;
1278 
1279     gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
1280     if (IS_ERR(gpio)) {
1281         dev_err(&pdev->dev, "failed to get mux gpio\n");
1282         rc = PTR_ERR(gpio);
1283         goto err_free;
1284     }
1285     master->gpio_mux = gpio;
1286 
1287     /* Grab the reserved memory region (use DMA API instead ?) */
1288     np = of_parse_phandle(mnode, "memory-region", 0);
1289     if (!np) {
1290         dev_err(&pdev->dev, "Didn't find reserved memory\n");
1291         rc = -EINVAL;
1292         goto err_free;
1293     }
1294     rc = of_address_to_resource(np, 0, &res);
1295     of_node_put(np);
1296     if (rc) {
1297         dev_err(&pdev->dev, "Couldn't address to resource for reserved memory\n");
1298         rc = -ENOMEM;
1299         goto err_free;
1300     }
1301     master->cf_mem_size = resource_size(&res);
1302     master->cf_mem_addr = (uint32_t)res.start;
1303     cf_mem_align = master->is_ast2500 ? 0x00100000 : 0x00200000;
1304     if (master->cf_mem_addr & (cf_mem_align - 1)) {
1305         dev_err(&pdev->dev, "Reserved memory has insufficient alignment\n");
1306         rc = -ENOMEM;
1307         goto err_free;
1308     }
1309     master->cf_mem = devm_ioremap_resource(&pdev->dev, &res);
1310     if (IS_ERR(master->cf_mem)) {
1311         rc = PTR_ERR(master->cf_mem);
1312         goto err_free;
1313     }
1314     dev_dbg(&pdev->dev, "DRAM allocation @%x\n", master->cf_mem_addr);
1315 
1316     /* AST2500 has a SW interrupt to the coprocessor */
1317     if (master->is_ast2500) {
1318         /* Grab the CVIC (ColdFire interrupts controller) */
1319         np = of_parse_phandle(mnode, "aspeed,cvic", 0);
1320         if (!np) {
1321             dev_err(&pdev->dev, "Didn't find CVIC\n");
1322             rc = -EINVAL;
1323             goto err_free;
1324         }
1325         master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL);
1326         if (IS_ERR(master->cvic)) {
1327             rc = PTR_ERR(master->cvic);
1328             dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc);
1329             goto err_free;
1330         }
1331         rc = of_property_read_u32(np, "copro-sw-interrupts",
1332                       &master->cvic_sw_irq);
1333         if (rc) {
1334             dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n");
1335             goto err_free;
1336         }
1337     }
1338 
1339     /* Grab the SRAM */
1340     master->sram_pool = of_gen_pool_get(dev_of_node(&pdev->dev), "aspeed,sram", 0);
1341     if (!master->sram_pool) {
1342         rc = -ENODEV;
1343         dev_err(&pdev->dev, "Can't find sram pool\n");
1344         goto err_free;
1345     }
1346 
1347     /* Current microcode only deals with fixed location in SRAM */
1348     gpdf.offset = 0;
1349     master->sram = (void __iomem *)gen_pool_alloc_algo(master->sram_pool, SRAM_SIZE,
1350                                gen_pool_fixed_alloc, &gpdf);
1351     if (!master->sram) {
1352         rc = -ENOMEM;
1353         dev_err(&pdev->dev, "Failed to allocate sram from pool\n");
1354         goto err_free;
1355     }
1356     dev_dbg(&pdev->dev, "SRAM allocation @%lx\n",
1357         (unsigned long)gen_pool_virt_to_phys(master->sram_pool,
1358                              (unsigned long)master->sram));
1359 
1360     /*
1361      * Hookup with the GPIO driver for arbitration of GPIO banks
1362      * ownership.
1363      */
1364     aspeed_gpio_copro_set_ops(&fsi_master_acf_gpio_ops, master);
1365 
1366     /* Default FSI command delays */
1367     master->t_send_delay = FSI_SEND_DELAY_CLOCKS;
1368     master->t_echo_delay = FSI_ECHO_DELAY_CLOCKS;
1369     master->master.n_links = 1;
1370     if (master->is_ast2500)
1371         master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
1372     master->master.read = fsi_master_acf_read;
1373     master->master.write = fsi_master_acf_write;
1374     master->master.term = fsi_master_acf_term;
1375     master->master.send_break = fsi_master_acf_break;
1376     master->master.link_enable = fsi_master_acf_link_enable;
1377     master->master.link_config = fsi_master_acf_link_config;
1378     master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
1379     master->master.dev.release = fsi_master_acf_release;
1380     platform_set_drvdata(pdev, master);
1381     mutex_init(&master->lock);
1382 
1383     mutex_lock(&master->lock);
1384     rc = fsi_master_acf_setup(master);
1385     mutex_unlock(&master->lock);
1386     if (rc)
1387         goto release_of_dev;
1388 
1389     rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
1390     if (rc)
1391         goto stop_copro;
1392 
1393     rc = fsi_master_register(&master->master);
1394     if (!rc)
1395         return 0;
1396 
1397     device_remove_file(master->dev, &dev_attr_external_mode);
1398     put_device(&master->master.dev);
1399     return rc;
1400 
1401  stop_copro:
1402     fsi_master_acf_terminate(master);
1403  release_of_dev:
1404     aspeed_gpio_copro_set_ops(NULL, NULL);
1405     gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
1406     of_node_put(dev_of_node(master->dev));
1407  err_free:
1408     kfree(master);
1409     return rc;
1410 }
1411 
1412 
1413 static int fsi_master_acf_remove(struct platform_device *pdev)
1414 {
1415     struct fsi_master_acf *master = platform_get_drvdata(pdev);
1416 
1417     device_remove_file(master->dev, &dev_attr_external_mode);
1418 
1419     fsi_master_unregister(&master->master);
1420 
1421     return 0;
1422 }
1423 
1424 static const struct of_device_id fsi_master_acf_match[] = {
1425     { .compatible = "aspeed,ast2400-cf-fsi-master" },
1426     { .compatible = "aspeed,ast2500-cf-fsi-master" },
1427     { },
1428 };
1429 MODULE_DEVICE_TABLE(of, fsi_master_acf_match);
1430 
1431 static struct platform_driver fsi_master_acf = {
1432     .driver = {
1433         .name       = "fsi-master-acf",
1434         .of_match_table = fsi_master_acf_match,
1435     },
1436     .probe  = fsi_master_acf_probe,
1437     .remove = fsi_master_acf_remove,
1438 };
1439 
1440 module_platform_driver(fsi_master_acf);
1441 MODULE_LICENSE("GPL");
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