drivers/fsi/cf-fsi-fw.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 #ifndef __CF_FSI_FW_H
0003 #define __CF_FSI_FW_H
0004
0005 /*
0006  * uCode file layout
0007  *
0008  * 0000...03ff : m68k exception vectors
0009  * 0400...04ff : Header info & boot config block
0010  * 0500....... : Code & stack
0011  */
0012
0013 /*
0014  * Header info & boot config area
0015  *
0016  * The Header info is built into the ucode and provide version and
0017  * platform information.
0018  *
0019  * the Boot config needs to be adjusted by the ARM prior to starting
0020  * the ucode if the Command/Status area isn't at 0x320000 in CF space
0021  * (ie. beginning of SRAM).
0022  */
0023
0024 #define HDR_OFFSET          0x400
0025
0026 /* Info: Signature & version */
0027 #define HDR_SYS_SIG     0x00    /* 2 bytes system signature */
0028 #define  SYS_SIG_SHARED     0x5348
0029 #define  SYS_SIG_SPLIT      0x5350
0030 #define HDR_FW_VERS     0x02    /* 2 bytes Major.Minor */
0031 #define HDR_API_VERS        0x04    /* 2 bytes Major.Minor */
0032 #define  API_VERSION_MAJ    2   /* Current version */
0033 #define  API_VERSION_MIN    1
0034 #define HDR_FW_OPTIONS      0x08    /* 4 bytes option flags */
0035 #define  FW_OPTION_TRACE_EN 0x00000001  /* FW tracing enabled */
0036 #define  FW_OPTION_CONT_CLOCK   0x00000002  /* Continuous clocking supported */
0037 #define HDR_FW_SIZE     0x10    /* 4 bytes size for combo image */
0038
0039 /* Boot Config: Address of Command/Status area */
0040 #define HDR_CMD_STAT_AREA   0x80    /* 4 bytes CF address */
0041 #define HDR_FW_CONTROL      0x84    /* 4 bytes control flags */
0042 #define  FW_CONTROL_CONT_CLOCK  0x00000002  /* Continuous clocking enabled */
0043 #define  FW_CONTROL_DUMMY_RD    0x00000004  /* Extra dummy read (AST2400) */
0044 #define  FW_CONTROL_USE_STOP    0x00000008  /* Use STOP instructions */
0045 #define HDR_CLOCK_GPIO_VADDR    0x90    /* 2 bytes offset from GPIO base */
0046 #define HDR_CLOCK_GPIO_DADDR    0x92    /* 2 bytes offset from GPIO base */
0047 #define HDR_DATA_GPIO_VADDR 0x94    /* 2 bytes offset from GPIO base */
0048 #define HDR_DATA_GPIO_DADDR 0x96    /* 2 bytes offset from GPIO base */
0049 #define HDR_TRANS_GPIO_VADDR    0x98    /* 2 bytes offset from GPIO base */
0050 #define HDR_TRANS_GPIO_DADDR    0x9a    /* 2 bytes offset from GPIO base */
0051 #define HDR_CLOCK_GPIO_BIT  0x9c    /* 1 byte bit number */
0052 #define HDR_DATA_GPIO_BIT   0x9d    /* 1 byte bit number */
0053 #define HDR_TRANS_GPIO_BIT  0x9e    /* 1 byte bit number */
0054
0055 /*
0056  *  Command/Status area layout: Main part
0057  */
0058
0059 /* Command/Status register:
0060  *
0061  * +---------------------------+
0062  * | STAT | RLEN | CLEN | CMD  |
0063  * |   8  |   8  |   8  |   8  |
0064  * +---------------------------+
0065  *    |       |      |      |
0066  *    status  |      |      |
0067  * Response len      |      |
0068  * (in bits)         |      |
0069  *                   |      |
0070  *         Command len      |
0071  *         (in bits)        |
0072  *                          |
0073  *               Command code
0074  *
0075  * Due to the big endian layout, that means that a byte read will
0076  * return the status byte
0077  */
0078 #define CMD_STAT_REG            0x00
0079 #define  CMD_REG_CMD_MASK   0x000000ff
0080 #define  CMD_REG_CMD_SHIFT  0
0081 #define   CMD_NONE      0x00
0082 #define   CMD_COMMAND       0x01
0083 #define   CMD_BREAK     0x02
0084 #define   CMD_IDLE_CLOCKS   0x03 /* clen = #clocks */
0085 #define   CMD_INVALID       0xff
0086 #define  CMD_REG_CLEN_MASK  0x0000ff00
0087 #define  CMD_REG_CLEN_SHIFT 8
0088 #define  CMD_REG_RLEN_MASK  0x00ff0000
0089 #define  CMD_REG_RLEN_SHIFT 16
0090 #define  CMD_REG_STAT_MASK  0xff000000
0091 #define  CMD_REG_STAT_SHIFT 24
0092 #define   STAT_WORKING      0x00
0093 #define   STAT_COMPLETE     0x01
0094 #define   STAT_ERR_INVAL_CMD    0x80
0095 #define   STAT_ERR_INVAL_IRQ    0x81
0096 #define   STAT_ERR_MTOE     0x82
0097
0098 /* Response tag & CRC */
0099 #define STAT_RTAG       0x04
0100
0101 /* Response CRC */
0102 #define STAT_RCRC       0x05
0103
0104 /* Echo and Send delay */
0105 #define ECHO_DLY_REG        0x08
0106 #define SEND_DLY_REG        0x09
0107
0108 /* Command data area
0109  *
0110  * Last byte of message must be left aligned
0111  */
0112 #define CMD_DATA        0x10 /* 64 bit of data */
0113
0114 /* Response data area, right aligned, unused top bits are 1 */
0115 #define RSP_DATA        0x20 /* 32 bit of data */
0116
0117 /* Misc */
0118 #define INT_CNT         0x30 /* 32-bit interrupt count */
0119 #define BAD_INT_VEC     0x34 /* 32-bit bad interrupt vector # */
0120 #define CF_STARTED      0x38 /* byte, set to -1 when copro started */
0121 #define CLK_CNT         0x3c /* 32-bit, clock count (debug only) */
0122
0123 /*
0124  *  SRAM layout: GPIO arbitration part
0125  */
0126 #define ARB_REG         0x40
0127 #define  ARB_ARM_REQ        0x01
0128 #define  ARB_ARM_ACK        0x02
0129
0130 /* Misc2 */
0131 #define CF_RESET_D0     0x50
0132 #define CF_RESET_D1     0x54
0133 #define BAD_INT_S0      0x58
0134 #define BAD_INT_S1      0x5c
0135 #define STOP_CNT        0x60
0136
0137 /* Internal */
0138
0139 /*
0140  * SRAM layout: Trace buffer (debug builds only)
0141  */
0142 #define TRACEBUF        0x100
0143 #define   TR_CLKOBIT0       0xc0
0144 #define   TR_CLKOBIT1       0xc1
0145 #define   TR_CLKOSTART      0x82
0146 #define   TR_OLEN       0x83 /* + len */
0147 #define   TR_CLKZ       0x84 /* + count */
0148 #define   TR_CLKWSTART      0x85
0149 #define   TR_CLKTAG     0x86 /* + tag */
0150 #define   TR_CLKDATA        0x87 /* + len */
0151 #define   TR_CLKCRC     0x88 /* + raw crc */
0152 #define   TR_CLKIBIT0       0x90
0153 #define   TR_CLKIBIT1       0x91
0154 #define   TR_END        0xff
0155
0156 #endif /* __CF_FSI_FW_H */
0157