drivers/fpga/zynqmp-fpga.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2019 Xilinx, Inc.
0004  */
0005
0006 #include <linux/dma-mapping.h>
0007 #include <linux/fpga/fpga-mgr.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of_address.h>
0012 #include <linux/string.h>
0013 #include <linux/firmware/xlnx-zynqmp.h>
0014
0015 /* Constant Definitions */
0016 #define IXR_FPGA_DONE_MASK  BIT(3)
0017
0018 /**
0019  * struct zynqmp_fpga_priv - Private data structure
0020  * @dev:    Device data structure
0021  * @flags:  flags which is used to identify the bitfile type
0022  */
0023 struct zynqmp_fpga_priv {
0024     struct device *dev;
0025     u32 flags;
0026 };
0027
0028 static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
0029                       struct fpga_image_info *info,
0030                       const char *buf, size_t size)
0031 {
0032     struct zynqmp_fpga_priv *priv;
0033
0034     priv = mgr->priv;
0035     priv->flags = info->flags;
0036
0037     return 0;
0038 }
0039
0040 static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
0041                  const char *buf, size_t size)
0042 {
0043     struct zynqmp_fpga_priv *priv;
0044     dma_addr_t dma_addr;
0045     u32 eemi_flags = 0;
0046     char *kbuf;
0047     int ret;
0048
0049     priv = mgr->priv;
0050
0051     kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
0052     if (!kbuf)
0053         return -ENOMEM;
0054
0055     memcpy(kbuf, buf, size);
0056
0057     wmb(); /* ensure all writes are done before initiate FW call */
0058
0059     if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
0060         eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
0061
0062     ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags);
0063
0064     dma_free_coherent(priv->dev, size, kbuf, dma_addr);
0065
0066     return ret;
0067 }
0068
0069 static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
0070 {
0071     u32 status = 0;
0072
0073     zynqmp_pm_fpga_get_status(&status);
0074     if (status & IXR_FPGA_DONE_MASK)
0075         return FPGA_MGR_STATE_OPERATING;
0076
0077     return FPGA_MGR_STATE_UNKNOWN;
0078 }
0079
0080 static const struct fpga_manager_ops zynqmp_fpga_ops = {
0081     .state = zynqmp_fpga_ops_state,
0082     .write_init = zynqmp_fpga_ops_write_init,
0083     .write = zynqmp_fpga_ops_write,
0084 };
0085
0086 static int zynqmp_fpga_probe(struct platform_device *pdev)
0087 {
0088     struct device *dev = &pdev->dev;
0089     struct zynqmp_fpga_priv *priv;
0090     struct fpga_manager *mgr;
0091
0092     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0093     if (!priv)
0094         return -ENOMEM;
0095
0096     priv->dev = dev;
0097
0098     mgr = devm_fpga_mgr_register(dev, "Xilinx ZynqMP FPGA Manager",
0099                      &zynqmp_fpga_ops, priv);
0100     return PTR_ERR_OR_ZERO(mgr);
0101 }
0102
0103 #ifdef CONFIG_OF
0104 static const struct of_device_id zynqmp_fpga_of_match[] = {
0105     { .compatible = "xlnx,zynqmp-pcap-fpga", },
0106     {},
0107 };
0108 MODULE_DEVICE_TABLE(of, zynqmp_fpga_of_match);
0109 #endif
0110
0111 static struct platform_driver zynqmp_fpga_driver = {
0112     .probe = zynqmp_fpga_probe,
0113     .driver = {
0114         .name = "zynqmp_fpga_manager",
0115         .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
0116     },
0117 };
0118
0119 module_platform_driver(zynqmp_fpga_driver);
0120
0121 MODULE_AUTHOR("Nava kishore Manne <navam@xilinx.com>");
0122 MODULE_DESCRIPTION("Xilinx ZynqMp FPGA Manager");
0123 MODULE_LICENSE("GPL");