drivers/fpga/zynq-fpga.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2011-2015 Xilinx Inc.
0004  * Copyright (c) 2015, National Instruments Corp.
0005  *
0006  * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
0007  * in their vendor tree.
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/completion.h>
0012 #include <linux/delay.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/fpga/fpga-mgr.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/module.h>
0019 #include <linux/mfd/syscon.h>
0020 #include <linux/of_address.h>
0021 #include <linux/of_irq.h>
0022 #include <linux/pm.h>
0023 #include <linux/regmap.h>
0024 #include <linux/string.h>
0025 #include <linux/scatterlist.h>
0026
0027 /* Offsets into SLCR regmap */
0028
0029 /* FPGA Software Reset Control */
0030 #define SLCR_FPGA_RST_CTRL_OFFSET   0x240
0031 /* Level Shifters Enable */
0032 #define SLCR_LVL_SHFTR_EN_OFFSET    0x900
0033
0034 /* Constant Definitions */
0035
0036 /* Control Register */
0037 #define CTRL_OFFSET         0x00
0038 /* Lock Register */
0039 #define LOCK_OFFSET         0x04
0040 /* Interrupt Status Register */
0041 #define INT_STS_OFFSET          0x0c
0042 /* Interrupt Mask Register */
0043 #define INT_MASK_OFFSET         0x10
0044 /* Status Register */
0045 #define STATUS_OFFSET           0x14
0046 /* DMA Source Address Register */
0047 #define DMA_SRC_ADDR_OFFSET     0x18
0048 /* DMA Destination Address Reg */
0049 #define DMA_DST_ADDR_OFFSET     0x1c
0050 /* DMA Source Transfer Length */
0051 #define DMA_SRC_LEN_OFFSET      0x20
0052 /* DMA Destination Transfer */
0053 #define DMA_DEST_LEN_OFFSET     0x24
0054 /* Unlock Register */
0055 #define UNLOCK_OFFSET           0x34
0056 /* Misc. Control Register */
0057 #define MCTRL_OFFSET            0x80
0058
0059 /* Control Register Bit definitions */
0060
0061 /* Signal to reset FPGA */
0062 #define CTRL_PCFG_PROG_B_MASK       BIT(30)
0063 /* Enable PCAP for PR */
0064 #define CTRL_PCAP_PR_MASK       BIT(27)
0065 /* Enable PCAP */
0066 #define CTRL_PCAP_MODE_MASK     BIT(26)
0067 /* Lower rate to allow decrypt on the fly */
0068 #define CTRL_PCAP_RATE_EN_MASK      BIT(25)
0069 /* System booted in secure mode */
0070 #define CTRL_SEC_EN_MASK        BIT(7)
0071
0072 /* Miscellaneous Control Register bit definitions */
0073 /* Internal PCAP loopback */
0074 #define MCTRL_PCAP_LPBK_MASK        BIT(4)
0075
0076 /* Status register bit definitions */
0077
0078 /* FPGA init status */
0079 #define STATUS_DMA_Q_F          BIT(31)
0080 #define STATUS_DMA_Q_E          BIT(30)
0081 #define STATUS_PCFG_INIT_MASK       BIT(4)
0082
0083 /* Interrupt Status/Mask Register Bit definitions */
0084 /* DMA command done */
0085 #define IXR_DMA_DONE_MASK       BIT(13)
0086 /* DMA and PCAP cmd done */
0087 #define IXR_D_P_DONE_MASK       BIT(12)
0088  /* FPGA programmed */
0089 #define IXR_PCFG_DONE_MASK      BIT(2)
0090 #define IXR_ERROR_FLAGS_MASK        0x00F0C860
0091 #define IXR_ALL_MASK            0xF8F7F87F
0092
0093 /* Miscellaneous constant values */
0094
0095 /* Invalid DMA addr */
0096 #define DMA_INVALID_ADDRESS     GENMASK(31, 0)
0097 /* Used to unlock the dev */
0098 #define UNLOCK_MASK         0x757bdf0d
0099 /* Timeout for polling reset bits */
0100 #define INIT_POLL_TIMEOUT       2500000
0101 /* Delay for polling reset bits */
0102 #define INIT_POLL_DELAY         20
0103 /* Signal this is the last DMA transfer, wait for the AXI and PCAP before
0104  * interrupting
0105  */
0106 #define DMA_SRC_LAST_TRANSFER       1
0107 /* Timeout for DMA completion */
0108 #define DMA_TIMEOUT_MS          5000
0109
0110 /* Masks for controlling stuff in SLCR */
0111 /* Disable all Level shifters */
0112 #define LVL_SHFTR_DISABLE_ALL_MASK  0x0
0113 /* Enable Level shifters from PS to PL */
0114 #define LVL_SHFTR_ENABLE_PS_TO_PL   0xa
0115 /* Enable Level shifters from PL to PS */
0116 #define LVL_SHFTR_ENABLE_PL_TO_PS   0xf
0117 /* Enable global resets */
0118 #define FPGA_RST_ALL_MASK       0xf
0119 /* Disable global resets */
0120 #define FPGA_RST_NONE_MASK      0x0
0121
0122 struct zynq_fpga_priv {
0123     int irq;
0124     struct clk *clk;
0125
0126     void __iomem *io_base;
0127     struct regmap *slcr;
0128
0129     spinlock_t dma_lock;
0130     unsigned int dma_elm;
0131     unsigned int dma_nelms;
0132     struct scatterlist *cur_sg;
0133
0134     struct completion dma_done;
0135 };
0136
0137 static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
0138                    u32 val)
0139 {
0140     writel(val, priv->io_base + offset);
0141 }
0142
0143 static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
0144                  u32 offset)
0145 {
0146     return readl(priv->io_base + offset);
0147 }
0148
0149 #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
0150     readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
0151                timeout_us)
0152
0153 /* Cause the specified irq mask bits to generate IRQs */
0154 static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
0155 {
0156     zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
0157 }
0158
0159 /* Must be called with dma_lock held */
0160 static void zynq_step_dma(struct zynq_fpga_priv *priv)
0161 {
0162     u32 addr;
0163     u32 len;
0164     bool first;
0165
0166     first = priv->dma_elm == 0;
0167     while (priv->cur_sg) {
0168         /* Feed the DMA queue until it is full. */
0169         if (zynq_fpga_read(priv, STATUS_OFFSET) & STATUS_DMA_Q_F)
0170             break;
0171
0172         addr = sg_dma_address(priv->cur_sg);
0173         len = sg_dma_len(priv->cur_sg);
0174         if (priv->dma_elm + 1 == priv->dma_nelms) {
0175             /* The last transfer waits for the PCAP to finish too,
0176              * notice this also changes the irq_mask to ignore
0177              * IXR_DMA_DONE_MASK which ensures we do not trigger
0178              * the completion too early.
0179              */
0180             addr |= DMA_SRC_LAST_TRANSFER;
0181             priv->cur_sg = NULL;
0182         } else {
0183             priv->cur_sg = sg_next(priv->cur_sg);
0184             priv->dma_elm++;
0185         }
0186
0187         zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, addr);
0188         zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, DMA_INVALID_ADDRESS);
0189         zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, len / 4);
0190         zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
0191     }
0192
0193     /* Once the first transfer is queued we can turn on the ISR, future
0194      * calls to zynq_step_dma will happen from the ISR context. The
0195      * dma_lock spinlock guarantees this handover is done coherently, the
0196      * ISR enable is put at the end to avoid another CPU spinning in the
0197      * ISR on this lock.
0198      */
0199     if (first && priv->cur_sg) {
0200         zynq_fpga_set_irq(priv,
0201                   IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
0202     } else if (!priv->cur_sg) {
0203         /* The last transfer changes to DMA & PCAP mode since we do
0204          * not want to continue until everything has been flushed into
0205          * the PCAP.
0206          */
0207         zynq_fpga_set_irq(priv,
0208                   IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);
0209     }
0210 }
0211
0212 static irqreturn_t zynq_fpga_isr(int irq, void *data)
0213 {
0214     struct zynq_fpga_priv *priv = data;
0215     u32 intr_status;
0216
0217     /* If anything other than DMA completion is reported stop and hand
0218      * control back to zynq_fpga_ops_write, something went wrong,
0219      * otherwise progress the DMA.
0220      */
0221     spin_lock(&priv->dma_lock);
0222     intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
0223     if (!(intr_status & IXR_ERROR_FLAGS_MASK) &&
0224         (intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {
0225         zynq_fpga_write(priv, INT_STS_OFFSET, IXR_DMA_DONE_MASK);
0226         zynq_step_dma(priv);
0227         spin_unlock(&priv->dma_lock);
0228         return IRQ_HANDLED;
0229     }
0230     spin_unlock(&priv->dma_lock);
0231
0232     zynq_fpga_set_irq(priv, 0);
0233     complete(&priv->dma_done);
0234
0235     return IRQ_HANDLED;
0236 }
0237
0238 /* Sanity check the proposed bitstream. It must start with the sync word in
0239  * the correct byte order, and be dword aligned. The input is a Xilinx .bin
0240  * file with every 32 bit quantity swapped.
0241  */
0242 static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
0243 {
0244     for (; count >= 4; buf += 4, count -= 4)
0245         if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
0246             buf[3] == 0xaa)
0247             return true;
0248     return false;
0249 }
0250
0251 static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
0252                     struct fpga_image_info *info,
0253                     const char *buf, size_t count)
0254 {
0255     struct zynq_fpga_priv *priv;
0256     u32 ctrl, status;
0257     int err;
0258
0259     priv = mgr->priv;
0260
0261     err = clk_enable(priv->clk);
0262     if (err)
0263         return err;
0264
0265     /* check if bitstream is encrypted & and system's still secure */
0266     if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) {
0267         ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
0268         if (!(ctrl & CTRL_SEC_EN_MASK)) {
0269             dev_err(&mgr->dev,
0270                 "System not secure, can't use encrypted bitstreams\n");
0271             err = -EINVAL;
0272             goto out_err;
0273         }
0274     }
0275
0276     /* don't globally reset PL if we're doing partial reconfig */
0277     if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
0278         if (!zynq_fpga_has_sync(buf, count)) {
0279             dev_err(&mgr->dev,
0280                 "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
0281             err = -EINVAL;
0282             goto out_err;
0283         }
0284
0285         /* assert AXI interface resets */
0286         regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
0287                  FPGA_RST_ALL_MASK);
0288
0289         /* disable all level shifters */
0290         regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
0291                  LVL_SHFTR_DISABLE_ALL_MASK);
0292         /* enable level shifters from PS to PL */
0293         regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
0294                  LVL_SHFTR_ENABLE_PS_TO_PL);
0295
0296         /* create a rising edge on PCFG_INIT. PCFG_INIT follows
0297          * PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
0298          * to make sure the rising edge actually happens.
0299          * Note: PCFG_PROG_B is low active, sequence as described in
0300          * UG585 v1.10 page 211
0301          */
0302         ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
0303         ctrl |= CTRL_PCFG_PROG_B_MASK;
0304
0305         zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
0306
0307         err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
0308                          status & STATUS_PCFG_INIT_MASK,
0309                          INIT_POLL_DELAY,
0310                          INIT_POLL_TIMEOUT);
0311         if (err) {
0312             dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
0313             goto out_err;
0314         }
0315
0316         ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
0317         ctrl &= ~CTRL_PCFG_PROG_B_MASK;
0318
0319         zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
0320
0321         err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
0322                          !(status & STATUS_PCFG_INIT_MASK),
0323                          INIT_POLL_DELAY,
0324                          INIT_POLL_TIMEOUT);
0325         if (err) {
0326             dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
0327             goto out_err;
0328         }
0329
0330         ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
0331         ctrl |= CTRL_PCFG_PROG_B_MASK;
0332
0333         zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
0334
0335         err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
0336                          status & STATUS_PCFG_INIT_MASK,
0337                          INIT_POLL_DELAY,
0338                          INIT_POLL_TIMEOUT);
0339         if (err) {
0340             dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
0341             goto out_err;
0342         }
0343     }
0344
0345     /* set configuration register with following options:
0346      * - enable PCAP interface
0347      * - set throughput for maximum speed (if bistream not encrypted)
0348      * - set CPU in user mode
0349      */
0350     ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
0351     if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM)
0352         zynq_fpga_write(priv, CTRL_OFFSET,
0353                 (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK
0354                  | CTRL_PCAP_RATE_EN_MASK | ctrl));
0355     else
0356         zynq_fpga_write(priv, CTRL_OFFSET,
0357                 (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK
0358                  | ctrl));
0359
0360
0361     /* We expect that the command queue is empty right now. */
0362     status = zynq_fpga_read(priv, STATUS_OFFSET);
0363     if ((status & STATUS_DMA_Q_F) ||
0364         (status & STATUS_DMA_Q_E) != STATUS_DMA_Q_E) {
0365         dev_err(&mgr->dev, "DMA command queue not right\n");
0366         err = -EBUSY;
0367         goto out_err;
0368     }
0369
0370     /* ensure internal PCAP loopback is disabled */
0371     ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
0372     zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));
0373
0374     clk_disable(priv->clk);
0375
0376     return 0;
0377
0378 out_err:
0379     clk_disable(priv->clk);
0380
0381     return err;
0382 }
0383
0384 static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
0385 {
0386     struct zynq_fpga_priv *priv;
0387     const char *why;
0388     int err;
0389     u32 intr_status;
0390     unsigned long timeout;
0391     unsigned long flags;
0392     struct scatterlist *sg;
0393     int i;
0394
0395     priv = mgr->priv;
0396
0397     /* The hardware can only DMA multiples of 4 bytes, and it requires the
0398      * starting addresses to be aligned to 64 bits (UG585 pg 212).
0399      */
0400     for_each_sg(sgt->sgl, sg, sgt->nents, i) {
0401         if ((sg->offset % 8) || (sg->length % 4)) {
0402             dev_err(&mgr->dev,
0403                 "Invalid bitstream, chunks must be aligned\n");
0404             return -EINVAL;
0405         }
0406     }
0407
0408     priv->dma_nelms =
0409         dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
0410     if (priv->dma_nelms == 0) {
0411         dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
0412         return -ENOMEM;
0413     }
0414
0415     /* enable clock */
0416     err = clk_enable(priv->clk);
0417     if (err)
0418         goto out_free;
0419
0420     zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
0421     reinit_completion(&priv->dma_done);
0422
0423     /* zynq_step_dma will turn on interrupts */
0424     spin_lock_irqsave(&priv->dma_lock, flags);
0425     priv->dma_elm = 0;
0426     priv->cur_sg = sgt->sgl;
0427     zynq_step_dma(priv);
0428     spin_unlock_irqrestore(&priv->dma_lock, flags);
0429
0430     timeout = wait_for_completion_timeout(&priv->dma_done,
0431                           msecs_to_jiffies(DMA_TIMEOUT_MS));
0432
0433     spin_lock_irqsave(&priv->dma_lock, flags);
0434     zynq_fpga_set_irq(priv, 0);
0435     priv->cur_sg = NULL;
0436     spin_unlock_irqrestore(&priv->dma_lock, flags);
0437
0438     intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
0439     zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
0440
0441     /* There doesn't seem to be a way to force cancel any DMA, so if
0442      * something went wrong we are relying on the hardware to have halted
0443      * the DMA before we get here, if there was we could use
0444      * wait_for_completion_interruptible too.
0445      */
0446
0447     if (intr_status & IXR_ERROR_FLAGS_MASK) {
0448         why = "DMA reported error";
0449         err = -EIO;
0450         goto out_report;
0451     }
0452
0453     if (priv->cur_sg ||
0454         !((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
0455         if (timeout == 0)
0456             why = "DMA timed out";
0457         else
0458             why = "DMA did not complete";
0459         err = -EIO;
0460         goto out_report;
0461     }
0462
0463     err = 0;
0464     goto out_clk;
0465
0466 out_report:
0467     dev_err(&mgr->dev,
0468         "%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
0469         why,
0470         intr_status,
0471         zynq_fpga_read(priv, CTRL_OFFSET),
0472         zynq_fpga_read(priv, LOCK_OFFSET),
0473         zynq_fpga_read(priv, INT_MASK_OFFSET),
0474         zynq_fpga_read(priv, STATUS_OFFSET),
0475         zynq_fpga_read(priv, MCTRL_OFFSET));
0476
0477 out_clk:
0478     clk_disable(priv->clk);
0479
0480 out_free:
0481     dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
0482     return err;
0483 }
0484
0485 static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
0486                     struct fpga_image_info *info)
0487 {
0488     struct zynq_fpga_priv *priv = mgr->priv;
0489     int err;
0490     u32 intr_status;
0491
0492     err = clk_enable(priv->clk);
0493     if (err)
0494         return err;
0495
0496     /* Release 'PR' control back to the ICAP */
0497     zynq_fpga_write(priv, CTRL_OFFSET,
0498         zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
0499
0500     err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
0501                      intr_status & IXR_PCFG_DONE_MASK,
0502                      INIT_POLL_DELAY,
0503                      INIT_POLL_TIMEOUT);
0504
0505     clk_disable(priv->clk);
0506
0507     if (err)
0508         return err;
0509
0510     /* for the partial reconfig case we didn't touch the level shifters */
0511     if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
0512         /* enable level shifters from PL to PS */
0513         regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
0514                  LVL_SHFTR_ENABLE_PL_TO_PS);
0515
0516         /* deassert AXI interface resets */
0517         regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
0518                  FPGA_RST_NONE_MASK);
0519     }
0520
0521     return 0;
0522 }
0523
0524 static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
0525 {
0526     int err;
0527     u32 intr_status;
0528     struct zynq_fpga_priv *priv;
0529
0530     priv = mgr->priv;
0531
0532     err = clk_enable(priv->clk);
0533     if (err)
0534         return FPGA_MGR_STATE_UNKNOWN;
0535
0536     intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
0537     clk_disable(priv->clk);
0538
0539     if (intr_status & IXR_PCFG_DONE_MASK)
0540         return FPGA_MGR_STATE_OPERATING;
0541
0542     return FPGA_MGR_STATE_UNKNOWN;
0543 }
0544
0545 static const struct fpga_manager_ops zynq_fpga_ops = {
0546     .initial_header_size = 128,
0547     .state = zynq_fpga_ops_state,
0548     .write_init = zynq_fpga_ops_write_init,
0549     .write_sg = zynq_fpga_ops_write,
0550     .write_complete = zynq_fpga_ops_write_complete,
0551 };
0552
0553 static int zynq_fpga_probe(struct platform_device *pdev)
0554 {
0555     struct device *dev = &pdev->dev;
0556     struct zynq_fpga_priv *priv;
0557     struct fpga_manager *mgr;
0558     struct resource *res;
0559     int err;
0560
0561     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0562     if (!priv)
0563         return -ENOMEM;
0564     spin_lock_init(&priv->dma_lock);
0565
0566     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0567     priv->io_base = devm_ioremap_resource(dev, res);
0568     if (IS_ERR(priv->io_base))
0569         return PTR_ERR(priv->io_base);
0570
0571     priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
0572         "syscon");
0573     if (IS_ERR(priv->slcr)) {
0574         dev_err(dev, "unable to get zynq-slcr regmap\n");
0575         return PTR_ERR(priv->slcr);
0576     }
0577
0578     init_completion(&priv->dma_done);
0579
0580     priv->irq = platform_get_irq(pdev, 0);
0581     if (priv->irq < 0)
0582         return priv->irq;
0583
0584     priv->clk = devm_clk_get(dev, "ref_clk");
0585     if (IS_ERR(priv->clk)) {
0586         if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
0587             dev_err(dev, "input clock not found\n");
0588         return PTR_ERR(priv->clk);
0589     }
0590
0591     err = clk_prepare_enable(priv->clk);
0592     if (err) {
0593         dev_err(dev, "unable to enable clock\n");
0594         return err;
0595     }
0596
0597     /* unlock the device */
0598     zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
0599
0600     zynq_fpga_set_irq(priv, 0);
0601     zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
0602     err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
0603                    priv);
0604     if (err) {
0605         dev_err(dev, "unable to request IRQ\n");
0606         clk_disable_unprepare(priv->clk);
0607         return err;
0608     }
0609
0610     clk_disable(priv->clk);
0611
0612     mgr = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager",
0613                 &zynq_fpga_ops, priv);
0614     if (IS_ERR(mgr)) {
0615         dev_err(dev, "unable to register FPGA manager\n");
0616         clk_unprepare(priv->clk);
0617         return PTR_ERR(mgr);
0618     }
0619
0620     platform_set_drvdata(pdev, mgr);
0621
0622     return 0;
0623 }
0624
0625 static int zynq_fpga_remove(struct platform_device *pdev)
0626 {
0627     struct zynq_fpga_priv *priv;
0628     struct fpga_manager *mgr;
0629
0630     mgr = platform_get_drvdata(pdev);
0631     priv = mgr->priv;
0632
0633     fpga_mgr_unregister(mgr);
0634
0635     clk_unprepare(priv->clk);
0636
0637     return 0;
0638 }
0639
0640 #ifdef CONFIG_OF
0641 static const struct of_device_id zynq_fpga_of_match[] = {
0642     { .compatible = "xlnx,zynq-devcfg-1.0", },
0643     {},
0644 };
0645
0646 MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
0647 #endif
0648
0649 static struct platform_driver zynq_fpga_driver = {
0650     .probe = zynq_fpga_probe,
0651     .remove = zynq_fpga_remove,
0652     .driver = {
0653         .name = "zynq_fpga_manager",
0654         .of_match_table = of_match_ptr(zynq_fpga_of_match),
0655     },
0656 };
0657
0658 module_platform_driver(zynq_fpga_driver);
0659
0660 MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
0661 MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
0662 MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
0663 MODULE_LICENSE("GPL v2");