drivers/fpga/xilinx-spi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
0004  *
0005  * Copyright (C) 2017 DENX Software Engineering
0006  *
0007  * Anatolij Gustschin <agust@denx.de>
0008  *
0009  * Manage Xilinx FPGA firmware that is loaded over SPI using
0010  * the slave serial configuration interface.
0011  */
0012
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/fpga/fpga-mgr.h>
0016 #include <linux/gpio/consumer.h>
0017 #include <linux/module.h>
0018 #include <linux/mod_devicetable.h>
0019 #include <linux/of.h>
0020 #include <linux/spi/spi.h>
0021 #include <linux/sizes.h>
0022
0023 struct xilinx_spi_conf {
0024     struct spi_device *spi;
0025     struct gpio_desc *prog_b;
0026     struct gpio_desc *init_b;
0027     struct gpio_desc *done;
0028 };
0029
0030 static int get_done_gpio(struct fpga_manager *mgr)
0031 {
0032     struct xilinx_spi_conf *conf = mgr->priv;
0033     int ret;
0034
0035     ret = gpiod_get_value(conf->done);
0036
0037     if (ret < 0)
0038         dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret);
0039
0040     return ret;
0041 }
0042
0043 static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
0044 {
0045     if (!get_done_gpio(mgr))
0046         return FPGA_MGR_STATE_RESET;
0047
0048     return FPGA_MGR_STATE_UNKNOWN;
0049 }
0050
0051 /**
0052  * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
0053  * a given delay if the pin is unavailable
0054  *
0055  * @mgr:        The FPGA manager object
0056  * @value:      Value INIT_B to wait for (1 = asserted = low)
0057  * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
0058  *
0059  * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
0060  * too much time passed waiting for that. If no INIT_B GPIO is available
0061  * then always return 0.
0062  */
0063 static int wait_for_init_b(struct fpga_manager *mgr, int value,
0064                unsigned long alt_udelay)
0065 {
0066     struct xilinx_spi_conf *conf = mgr->priv;
0067     unsigned long timeout = jiffies + msecs_to_jiffies(1000);
0068
0069     if (conf->init_b) {
0070         while (time_before(jiffies, timeout)) {
0071             int ret = gpiod_get_value(conf->init_b);
0072
0073             if (ret == value)
0074                 return 0;
0075
0076             if (ret < 0) {
0077                 dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
0078                 return ret;
0079             }
0080
0081             usleep_range(100, 400);
0082         }
0083
0084         dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
0085             value ? "assert" : "deassert");
0086         return -ETIMEDOUT;
0087     }
0088
0089     udelay(alt_udelay);
0090
0091     return 0;
0092 }
0093
0094 static int xilinx_spi_write_init(struct fpga_manager *mgr,
0095                  struct fpga_image_info *info,
0096                  const char *buf, size_t count)
0097 {
0098     struct xilinx_spi_conf *conf = mgr->priv;
0099     int err;
0100
0101     if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
0102         dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
0103         return -EINVAL;
0104     }
0105
0106     gpiod_set_value(conf->prog_b, 1);
0107
0108     err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
0109     if (err) {
0110         gpiod_set_value(conf->prog_b, 0);
0111         return err;
0112     }
0113
0114     gpiod_set_value(conf->prog_b, 0);
0115
0116     err = wait_for_init_b(mgr, 0, 0);
0117     if (err)
0118         return err;
0119
0120     if (get_done_gpio(mgr)) {
0121         dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
0122         return -EIO;
0123     }
0124
0125     /* program latency */
0126     usleep_range(7500, 7600);
0127     return 0;
0128 }
0129
0130 static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
0131                 size_t count)
0132 {
0133     struct xilinx_spi_conf *conf = mgr->priv;
0134     const char *fw_data = buf;
0135     const char *fw_data_end = fw_data + count;
0136
0137     while (fw_data < fw_data_end) {
0138         size_t remaining, stride;
0139         int ret;
0140
0141         remaining = fw_data_end - fw_data;
0142         stride = min_t(size_t, remaining, SZ_4K);
0143
0144         ret = spi_write(conf->spi, fw_data, stride);
0145         if (ret) {
0146             dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
0147                 ret);
0148             return ret;
0149         }
0150         fw_data += stride;
0151     }
0152
0153     return 0;
0154 }
0155
0156 static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
0157 {
0158     struct spi_device *spi = conf->spi;
0159     const u8 din_data[1] = { 0xff };
0160     int ret;
0161
0162     ret = spi_write(conf->spi, din_data, sizeof(din_data));
0163     if (ret)
0164         dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
0165
0166     return ret;
0167 }
0168
0169 static int xilinx_spi_write_complete(struct fpga_manager *mgr,
0170                      struct fpga_image_info *info)
0171 {
0172     struct xilinx_spi_conf *conf = mgr->priv;
0173     unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
0174     bool expired = false;
0175     int done;
0176     int ret;
0177
0178     /*
0179      * This loop is carefully written such that if the driver is
0180      * scheduled out for more than 'timeout', we still check for DONE
0181      * before giving up and we apply 8 extra CCLK cycles in all cases.
0182      */
0183     while (!expired) {
0184         expired = time_after(jiffies, timeout);
0185
0186         done = get_done_gpio(mgr);
0187         if (done < 0)
0188             return done;
0189
0190         ret = xilinx_spi_apply_cclk_cycles(conf);
0191         if (ret)
0192             return ret;
0193
0194         if (done)
0195             return 0;
0196     }
0197
0198     if (conf->init_b) {
0199         ret = gpiod_get_value(conf->init_b);
0200
0201         if (ret < 0) {
0202             dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
0203             return ret;
0204         }
0205
0206         dev_err(&mgr->dev,
0207             ret ? "CRC error or invalid device\n"
0208             : "Missing sync word or incomplete bitstream\n");
0209     } else {
0210         dev_err(&mgr->dev, "Timeout after config data transfer\n");
0211     }
0212
0213     return -ETIMEDOUT;
0214 }
0215
0216 static const struct fpga_manager_ops xilinx_spi_ops = {
0217     .state = xilinx_spi_state,
0218     .write_init = xilinx_spi_write_init,
0219     .write = xilinx_spi_write,
0220     .write_complete = xilinx_spi_write_complete,
0221 };
0222
0223 static int xilinx_spi_probe(struct spi_device *spi)
0224 {
0225     struct xilinx_spi_conf *conf;
0226     struct fpga_manager *mgr;
0227
0228     conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
0229     if (!conf)
0230         return -ENOMEM;
0231
0232     conf->spi = spi;
0233
0234     /* PROGRAM_B is active low */
0235     conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
0236     if (IS_ERR(conf->prog_b))
0237         return dev_err_probe(&spi->dev, PTR_ERR(conf->prog_b),
0238                      "Failed to get PROGRAM_B gpio\n");
0239
0240     conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
0241     if (IS_ERR(conf->init_b))
0242         return dev_err_probe(&spi->dev, PTR_ERR(conf->init_b),
0243                      "Failed to get INIT_B gpio\n");
0244
0245     conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
0246     if (IS_ERR(conf->done))
0247         return dev_err_probe(&spi->dev, PTR_ERR(conf->done),
0248                      "Failed to get DONE gpio\n");
0249
0250     mgr = devm_fpga_mgr_register(&spi->dev,
0251                      "Xilinx Slave Serial FPGA Manager",
0252                      &xilinx_spi_ops, conf);
0253     return PTR_ERR_OR_ZERO(mgr);
0254 }
0255
0256 #ifdef CONFIG_OF
0257 static const struct of_device_id xlnx_spi_of_match[] = {
0258     { .compatible = "xlnx,fpga-slave-serial", },
0259     {}
0260 };
0261 MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
0262 #endif
0263
0264 static struct spi_driver xilinx_slave_spi_driver = {
0265     .driver = {
0266         .name = "xlnx-slave-spi",
0267         .of_match_table = of_match_ptr(xlnx_spi_of_match),
0268     },
0269     .probe = xilinx_spi_probe,
0270 };
0271
0272 module_spi_driver(xilinx_slave_spi_driver)
0273
0274 MODULE_LICENSE("GPL v2");
0275 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
0276 MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");