drivers/fpga/stratix10-soc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FPGA Manager Driver for Intel Stratix10 SoC
0004  *
0005  *  Copyright (C) 2018 Intel Corporation
0006  */
0007 #include <linux/completion.h>
0008 #include <linux/fpga/fpga-mgr.h>
0009 #include <linux/firmware/intel/stratix10-svc-client.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_platform.h>
0013
0014 /*
0015  * FPGA programming requires a higher level of privilege (EL3), per the SoC
0016  * design.
0017  */
0018 #define NUM_SVC_BUFS    4
0019 #define SVC_BUF_SIZE    SZ_512K
0020
0021 /* Indicates buffer is in use if set */
0022 #define SVC_BUF_LOCK    0
0023
0024 #define S10_BUFFER_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_BUFFER_TIMEOUT_MS))
0025 #define S10_RECONFIG_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_REQUEST_TIMEOUT_MS))
0026
0027 /*
0028  * struct s10_svc_buf
0029  * buf:  virtual address of buf provided by service layer
0030  * lock: locked if buffer is in use
0031  */
0032 struct s10_svc_buf {
0033     char *buf;
0034     unsigned long lock;
0035 };
0036
0037 struct s10_priv {
0038     struct stratix10_svc_chan *chan;
0039     struct stratix10_svc_client client;
0040     struct completion status_return_completion;
0041     struct s10_svc_buf svc_bufs[NUM_SVC_BUFS];
0042     unsigned long status;
0043 };
0044
0045 static int s10_svc_send_msg(struct s10_priv *priv,
0046                 enum stratix10_svc_command_code command,
0047                 void *payload, u32 payload_length)
0048 {
0049     struct stratix10_svc_chan *chan = priv->chan;
0050     struct device *dev = priv->client.dev;
0051     struct stratix10_svc_client_msg msg;
0052     int ret;
0053
0054     dev_dbg(dev, "%s cmd=%d payload=%p length=%d\n",
0055         __func__, command, payload, payload_length);
0056
0057     msg.command = command;
0058     msg.payload = payload;
0059     msg.payload_length = payload_length;
0060
0061     ret = stratix10_svc_send(chan, &msg);
0062     dev_dbg(dev, "stratix10_svc_send returned status %d\n", ret);
0063
0064     return ret;
0065 }
0066
0067 /*
0068  * Free buffers allocated from the service layer's pool that are not in use.
0069  * Return true when all buffers are freed.
0070  */
0071 static bool s10_free_buffers(struct fpga_manager *mgr)
0072 {
0073     struct s10_priv *priv = mgr->priv;
0074     uint num_free = 0;
0075     uint i;
0076
0077     for (i = 0; i < NUM_SVC_BUFS; i++) {
0078         if (!priv->svc_bufs[i].buf) {
0079             num_free++;
0080             continue;
0081         }
0082
0083         if (!test_and_set_bit_lock(SVC_BUF_LOCK,
0084                        &priv->svc_bufs[i].lock)) {
0085             stratix10_svc_free_memory(priv->chan,
0086                           priv->svc_bufs[i].buf);
0087             priv->svc_bufs[i].buf = NULL;
0088             num_free++;
0089         }
0090     }
0091
0092     return num_free == NUM_SVC_BUFS;
0093 }
0094
0095 /*
0096  * Returns count of how many buffers are not in use.
0097  */
0098 static uint s10_free_buffer_count(struct fpga_manager *mgr)
0099 {
0100     struct s10_priv *priv = mgr->priv;
0101     uint num_free = 0;
0102     uint i;
0103
0104     for (i = 0; i < NUM_SVC_BUFS; i++)
0105         if (!priv->svc_bufs[i].buf)
0106             num_free++;
0107
0108     return num_free;
0109 }
0110
0111 /*
0112  * s10_unlock_bufs
0113  * Given the returned buffer address, match that address to our buffer struct
0114  * and unlock that buffer.  This marks it as available to be refilled and sent
0115  * (or freed).
0116  * priv: private data
0117  * kaddr: kernel address of buffer that was returned from service layer
0118  */
0119 static void s10_unlock_bufs(struct s10_priv *priv, void *kaddr)
0120 {
0121     uint i;
0122
0123     if (!kaddr)
0124         return;
0125
0126     for (i = 0; i < NUM_SVC_BUFS; i++)
0127         if (priv->svc_bufs[i].buf == kaddr) {
0128             clear_bit_unlock(SVC_BUF_LOCK,
0129                      &priv->svc_bufs[i].lock);
0130             return;
0131         }
0132
0133     WARN(1, "Unknown buffer returned from service layer %p\n", kaddr);
0134 }
0135
0136 /*
0137  * s10_receive_callback - callback for service layer to use to provide client
0138  * (this driver) messages received through the mailbox.
0139  * client: service layer client struct
0140  * data: message from service layer
0141  */
0142 static void s10_receive_callback(struct stratix10_svc_client *client,
0143                  struct stratix10_svc_cb_data *data)
0144 {
0145     struct s10_priv *priv = client->priv;
0146     u32 status;
0147     int i;
0148
0149     WARN_ONCE(!data, "%s: stratix10_svc_rc_data = NULL", __func__);
0150
0151     status = data->status;
0152
0153     /*
0154      * Here we set status bits as we receive them.  Elsewhere, we always use
0155      * test_and_clear_bit() to check status in priv->status
0156      */
0157     for (i = 0; i <= SVC_STATUS_ERROR; i++)
0158         if (status & (1 << i))
0159             set_bit(i, &priv->status);
0160
0161     if (status & BIT(SVC_STATUS_BUFFER_DONE)) {
0162         s10_unlock_bufs(priv, data->kaddr1);
0163         s10_unlock_bufs(priv, data->kaddr2);
0164         s10_unlock_bufs(priv, data->kaddr3);
0165     }
0166
0167     complete(&priv->status_return_completion);
0168 }
0169
0170 /*
0171  * s10_ops_write_init - prepare for FPGA reconfiguration by requesting
0172  * partial reconfig and allocating buffers from the service layer.
0173  */
0174 static int s10_ops_write_init(struct fpga_manager *mgr,
0175                   struct fpga_image_info *info,
0176                   const char *buf, size_t count)
0177 {
0178     struct s10_priv *priv = mgr->priv;
0179     struct device *dev = priv->client.dev;
0180     struct stratix10_svc_command_config_type ctype;
0181     char *kbuf;
0182     uint i;
0183     int ret;
0184
0185     ctype.flags = 0;
0186     if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
0187         dev_dbg(dev, "Requesting partial reconfiguration.\n");
0188         ctype.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
0189     } else {
0190         dev_dbg(dev, "Requesting full reconfiguration.\n");
0191     }
0192
0193     reinit_completion(&priv->status_return_completion);
0194     ret = s10_svc_send_msg(priv, COMMAND_RECONFIG,
0195                    &ctype, sizeof(ctype));
0196     if (ret < 0)
0197         goto init_done;
0198
0199     ret = wait_for_completion_timeout(
0200         &priv->status_return_completion, S10_RECONFIG_TIMEOUT);
0201     if (!ret) {
0202         dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n");
0203         ret = -ETIMEDOUT;
0204         goto init_done;
0205     }
0206
0207     ret = 0;
0208     if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) {
0209         ret = -ETIMEDOUT;
0210         goto init_done;
0211     }
0212
0213     /* Allocate buffers from the service layer's pool. */
0214     for (i = 0; i < NUM_SVC_BUFS; i++) {
0215         kbuf = stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE);
0216         if (!kbuf) {
0217             s10_free_buffers(mgr);
0218             ret = -ENOMEM;
0219             goto init_done;
0220         }
0221
0222         priv->svc_bufs[i].buf = kbuf;
0223         priv->svc_bufs[i].lock = 0;
0224     }
0225
0226 init_done:
0227     stratix10_svc_done(priv->chan);
0228     return ret;
0229 }
0230
0231 /*
0232  * s10_send_buf - send a buffer to the service layer queue
0233  * mgr: fpga manager struct
0234  * buf: fpga image buffer
0235  * count: size of buf in bytes
0236  * Returns # of bytes transferred or -ENOBUFS if the all the buffers are in use
0237  * or if the service queue is full. Never returns 0.
0238  */
0239 static int s10_send_buf(struct fpga_manager *mgr, const char *buf, size_t count)
0240 {
0241     struct s10_priv *priv = mgr->priv;
0242     struct device *dev = priv->client.dev;
0243     void *svc_buf;
0244     size_t xfer_sz;
0245     int ret;
0246     uint i;
0247
0248     /* get/lock a buffer that that's not being used */
0249     for (i = 0; i < NUM_SVC_BUFS; i++)
0250         if (!test_and_set_bit_lock(SVC_BUF_LOCK,
0251                        &priv->svc_bufs[i].lock))
0252             break;
0253
0254     if (i == NUM_SVC_BUFS)
0255         return -ENOBUFS;
0256
0257     xfer_sz = count < SVC_BUF_SIZE ? count : SVC_BUF_SIZE;
0258
0259     svc_buf = priv->svc_bufs[i].buf;
0260     memcpy(svc_buf, buf, xfer_sz);
0261     ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_DATA_SUBMIT,
0262                    svc_buf, xfer_sz);
0263     if (ret < 0) {
0264         dev_err(dev,
0265             "Error while sending data to service layer (%d)", ret);
0266         clear_bit_unlock(SVC_BUF_LOCK, &priv->svc_bufs[i].lock);
0267         return ret;
0268     }
0269
0270     return xfer_sz;
0271 }
0272
0273 /*
0274  * Send an FPGA image to privileged layers to write to the FPGA.  When done
0275  * sending, free all service layer buffers we allocated in write_init.
0276  */
0277 static int s10_ops_write(struct fpga_manager *mgr, const char *buf,
0278              size_t count)
0279 {
0280     struct s10_priv *priv = mgr->priv;
0281     struct device *dev = priv->client.dev;
0282     long wait_status;
0283     int sent = 0;
0284     int ret = 0;
0285
0286     /*
0287      * Loop waiting for buffers to be returned.  When a buffer is returned,
0288      * reuse it to send more data or free if if all data has been sent.
0289      */
0290     while (count > 0 || s10_free_buffer_count(mgr) != NUM_SVC_BUFS) {
0291         reinit_completion(&priv->status_return_completion);
0292
0293         if (count > 0) {
0294             sent = s10_send_buf(mgr, buf, count);
0295             if (sent < 0)
0296                 continue;
0297
0298             count -= sent;
0299             buf += sent;
0300         } else {
0301             if (s10_free_buffers(mgr))
0302                 return 0;
0303
0304             ret = s10_svc_send_msg(
0305                 priv, COMMAND_RECONFIG_DATA_CLAIM,
0306                 NULL, 0);
0307             if (ret < 0)
0308                 break;
0309         }
0310
0311         /*
0312          * If callback hasn't already happened, wait for buffers to be
0313          * returned from service layer
0314          */
0315         wait_status = 1; /* not timed out */
0316         if (!priv->status)
0317             wait_status = wait_for_completion_timeout(
0318                 &priv->status_return_completion,
0319                 S10_BUFFER_TIMEOUT);
0320
0321         if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) ||
0322             test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED,
0323                        &priv->status)) {
0324             ret = 0;
0325             continue;
0326         }
0327
0328         if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) {
0329             dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n");
0330             ret = -EFAULT;
0331             break;
0332         }
0333
0334         if (!wait_status) {
0335             dev_err(dev, "timeout waiting for svc layer buffers\n");
0336             ret = -ETIMEDOUT;
0337             break;
0338         }
0339     }
0340
0341     if (!s10_free_buffers(mgr))
0342         dev_err(dev, "%s not all buffers were freed\n", __func__);
0343
0344     return ret;
0345 }
0346
0347 static int s10_ops_write_complete(struct fpga_manager *mgr,
0348                   struct fpga_image_info *info)
0349 {
0350     struct s10_priv *priv = mgr->priv;
0351     struct device *dev = priv->client.dev;
0352     unsigned long timeout;
0353     int ret;
0354
0355     timeout = usecs_to_jiffies(info->config_complete_timeout_us);
0356
0357     do {
0358         reinit_completion(&priv->status_return_completion);
0359
0360         ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_STATUS, NULL, 0);
0361         if (ret < 0)
0362             break;
0363
0364         ret = wait_for_completion_timeout(
0365             &priv->status_return_completion, timeout);
0366         if (!ret) {
0367             dev_err(dev,
0368                 "timeout waiting for RECONFIG_COMPLETED\n");
0369             ret = -ETIMEDOUT;
0370             break;
0371         }
0372         /* Not error or timeout, so ret is # of jiffies until timeout */
0373         timeout = ret;
0374         ret = 0;
0375
0376         if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status))
0377             break;
0378
0379         if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) {
0380             dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n");
0381             ret = -EFAULT;
0382             break;
0383         }
0384     } while (1);
0385
0386     stratix10_svc_done(priv->chan);
0387
0388     return ret;
0389 }
0390
0391 static const struct fpga_manager_ops s10_ops = {
0392     .write_init = s10_ops_write_init,
0393     .write = s10_ops_write,
0394     .write_complete = s10_ops_write_complete,
0395 };
0396
0397 static int s10_probe(struct platform_device *pdev)
0398 {
0399     struct device *dev = &pdev->dev;
0400     struct s10_priv *priv;
0401     struct fpga_manager *mgr;
0402     int ret;
0403
0404     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0405     if (!priv)
0406         return -ENOMEM;
0407
0408     priv->client.dev = dev;
0409     priv->client.receive_cb = s10_receive_callback;
0410     priv->client.priv = priv;
0411
0412     priv->chan = stratix10_svc_request_channel_byname(&priv->client,
0413                               SVC_CLIENT_FPGA);
0414     if (IS_ERR(priv->chan)) {
0415         dev_err(dev, "couldn't get service channel (%s)\n",
0416             SVC_CLIENT_FPGA);
0417         return PTR_ERR(priv->chan);
0418     }
0419
0420     init_completion(&priv->status_return_completion);
0421
0422     mgr = fpga_mgr_register(dev, "Stratix10 SOC FPGA Manager",
0423                 &s10_ops, priv);
0424     if (IS_ERR(mgr)) {
0425         dev_err(dev, "unable to register FPGA manager\n");
0426         ret = PTR_ERR(mgr);
0427         goto probe_err;
0428     }
0429
0430     platform_set_drvdata(pdev, mgr);
0431     return 0;
0432
0433 probe_err:
0434     stratix10_svc_free_channel(priv->chan);
0435     return ret;
0436 }
0437
0438 static int s10_remove(struct platform_device *pdev)
0439 {
0440     struct fpga_manager *mgr = platform_get_drvdata(pdev);
0441     struct s10_priv *priv = mgr->priv;
0442
0443     fpga_mgr_unregister(mgr);
0444     stratix10_svc_free_channel(priv->chan);
0445
0446     return 0;
0447 }
0448
0449 static const struct of_device_id s10_of_match[] = {
0450     {.compatible = "intel,stratix10-soc-fpga-mgr"},
0451     {.compatible = "intel,agilex-soc-fpga-mgr"},
0452     {},
0453 };
0454
0455 MODULE_DEVICE_TABLE(of, s10_of_match);
0456
0457 static struct platform_driver s10_driver = {
0458     .probe = s10_probe,
0459     .remove = s10_remove,
0460     .driver = {
0461         .name   = "Stratix10 SoC FPGA manager",
0462         .of_match_table = of_match_ptr(s10_of_match),
0463     },
0464 };
0465
0466 static int __init s10_init(void)
0467 {
0468     struct device_node *fw_np;
0469     struct device_node *np;
0470     int ret;
0471
0472     fw_np = of_find_node_by_name(NULL, "svc");
0473     if (!fw_np)
0474         return -ENODEV;
0475
0476     of_node_get(fw_np);
0477     np = of_find_matching_node(fw_np, s10_of_match);
0478     if (!np) {
0479         of_node_put(fw_np);
0480         return -ENODEV;
0481     }
0482
0483     of_node_put(np);
0484     ret = of_platform_populate(fw_np, s10_of_match, NULL, NULL);
0485     of_node_put(fw_np);
0486     if (ret)
0487         return ret;
0488
0489     return platform_driver_register(&s10_driver);
0490 }
0491
0492 static void __exit s10_exit(void)
0493 {
0494     return platform_driver_unregister(&s10_driver);
0495 }
0496
0497 module_init(s10_init);
0498 module_exit(s10_exit);
0499
0500 MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
0501 MODULE_DESCRIPTION("Intel Stratix 10 SOC FPGA Manager");
0502 MODULE_LICENSE("GPL v2");