drivers/fpga/socfpga.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FPGA Manager Driver for Altera SOCFPGA
0004  *
0005  *  Copyright (C) 2013-2015 Altera Corporation
0006  */
0007 #include <linux/completion.h>
0008 #include <linux/delay.h>
0009 #include <linux/fpga/fpga-mgr.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/pm.h>
0016
0017 /* Register offsets */
0018 #define SOCFPGA_FPGMGR_STAT_OFST                0x0
0019 #define SOCFPGA_FPGMGR_CTL_OFST                 0x4
0020 #define SOCFPGA_FPGMGR_DCLKCNT_OFST             0x8
0021 #define SOCFPGA_FPGMGR_DCLKSTAT_OFST                0xc
0022 #define SOCFPGA_FPGMGR_GPIO_INTEN_OFST              0x830
0023 #define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST             0x834
0024 #define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST          0x838
0025 #define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST            0x83c
0026 #define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST            0x840
0027 #define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST            0x844
0028 #define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST          0x84c
0029 #define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST          0x850
0030
0031 /* Register bit defines */
0032 /* SOCFPGA_FPGMGR_STAT register mode field values */
0033 #define SOCFPGA_FPGMGR_STAT_POWER_UP                0x0 /*ramping*/
0034 #define SOCFPGA_FPGMGR_STAT_RESET               0x1
0035 #define SOCFPGA_FPGMGR_STAT_CFG                 0x2
0036 #define SOCFPGA_FPGMGR_STAT_INIT                0x3
0037 #define SOCFPGA_FPGMGR_STAT_USER_MODE               0x4
0038 #define SOCFPGA_FPGMGR_STAT_UNKNOWN             0x5
0039 #define SOCFPGA_FPGMGR_STAT_STATE_MASK              0x7
0040 /* This is a flag value that doesn't really happen in this register field */
0041 #define SOCFPGA_FPGMGR_STAT_POWER_OFF               0x0
0042
0043 #define MSEL_PP16_FAST_NOAES_NODC               0x0
0044 #define MSEL_PP16_FAST_AES_NODC                 0x1
0045 #define MSEL_PP16_FAST_AESOPT_DC                0x2
0046 #define MSEL_PP16_SLOW_NOAES_NODC               0x4
0047 #define MSEL_PP16_SLOW_AES_NODC                 0x5
0048 #define MSEL_PP16_SLOW_AESOPT_DC                0x6
0049 #define MSEL_PP32_FAST_NOAES_NODC               0x8
0050 #define MSEL_PP32_FAST_AES_NODC                 0x9
0051 #define MSEL_PP32_FAST_AESOPT_DC                0xa
0052 #define MSEL_PP32_SLOW_NOAES_NODC               0xc
0053 #define MSEL_PP32_SLOW_AES_NODC                 0xd
0054 #define MSEL_PP32_SLOW_AESOPT_DC                0xe
0055 #define SOCFPGA_FPGMGR_STAT_MSEL_MASK               0x000000f8
0056 #define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT              3
0057
0058 /* SOCFPGA_FPGMGR_CTL register */
0059 #define SOCFPGA_FPGMGR_CTL_EN                   0x00000001
0060 #define SOCFPGA_FPGMGR_CTL_NCE                  0x00000002
0061 #define SOCFPGA_FPGMGR_CTL_NCFGPULL             0x00000004
0062
0063 #define CDRATIO_X1                      0x00000000
0064 #define CDRATIO_X2                      0x00000040
0065 #define CDRATIO_X4                      0x00000080
0066 #define CDRATIO_X8                      0x000000c0
0067 #define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK             0x000000c0
0068
0069 #define SOCFPGA_FPGMGR_CTL_AXICFGEN             0x00000100
0070
0071 #define CFGWDTH_16                      0x00000000
0072 #define CFGWDTH_32                      0x00000200
0073 #define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK             0x00000200
0074
0075 /* SOCFPGA_FPGMGR_DCLKSTAT register */
0076 #define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE         0x1
0077
0078 /* SOCFPGA_FPGMGR_GPIO_* registers share the same bit positions */
0079 #define SOCFPGA_FPGMGR_MON_NSTATUS              0x0001
0080 #define SOCFPGA_FPGMGR_MON_CONF_DONE                0x0002
0081 #define SOCFPGA_FPGMGR_MON_INIT_DONE                0x0004
0082 #define SOCFPGA_FPGMGR_MON_CRC_ERROR                0x0008
0083 #define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE            0x0010
0084 #define SOCFPGA_FPGMGR_MON_PR_READY             0x0020
0085 #define SOCFPGA_FPGMGR_MON_PR_ERROR             0x0040
0086 #define SOCFPGA_FPGMGR_MON_PR_DONE              0x0080
0087 #define SOCFPGA_FPGMGR_MON_NCONFIG_PIN              0x0100
0088 #define SOCFPGA_FPGMGR_MON_NSTATUS_PIN              0x0200
0089 #define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN            0x0400
0090 #define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON            0x0800
0091 #define SOCFPGA_FPGMGR_MON_STATUS_MASK              0x0fff
0092
0093 #define SOCFPGA_FPGMGR_NUM_SUPPLIES 3
0094 #define SOCFPGA_RESUME_TIMEOUT 3
0095
0096 /* In power-up order. Reverse for power-down. */
0097 static const char *supply_names[SOCFPGA_FPGMGR_NUM_SUPPLIES] __maybe_unused = {
0098     "FPGA-1.5V",
0099     "FPGA-1.1V",
0100     "FPGA-2.5V",
0101 };
0102
0103 struct socfpga_fpga_priv {
0104     void __iomem *fpga_base_addr;
0105     void __iomem *fpga_data_addr;
0106     struct completion status_complete;
0107     int irq;
0108 };
0109
0110 struct cfgmgr_mode {
0111     /* Values to set in the CTRL register */
0112     u32 ctrl;
0113
0114     /* flag that this table entry is a valid mode */
0115     bool valid;
0116 };
0117
0118 /* For SOCFPGA_FPGMGR_STAT_MSEL field */
0119 static struct cfgmgr_mode cfgmgr_modes[] = {
0120     [MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
0121     [MSEL_PP16_FAST_AES_NODC] =   { CFGWDTH_16 | CDRATIO_X2, 1 },
0122     [MSEL_PP16_FAST_AESOPT_DC] =  { CFGWDTH_16 | CDRATIO_X4, 1 },
0123     [MSEL_PP16_SLOW_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
0124     [MSEL_PP16_SLOW_AES_NODC] =   { CFGWDTH_16 | CDRATIO_X2, 1 },
0125     [MSEL_PP16_SLOW_AESOPT_DC] =  { CFGWDTH_16 | CDRATIO_X4, 1 },
0126     [MSEL_PP32_FAST_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
0127     [MSEL_PP32_FAST_AES_NODC] =   { CFGWDTH_32 | CDRATIO_X4, 1 },
0128     [MSEL_PP32_FAST_AESOPT_DC] =  { CFGWDTH_32 | CDRATIO_X8, 1 },
0129     [MSEL_PP32_SLOW_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
0130     [MSEL_PP32_SLOW_AES_NODC] =   { CFGWDTH_32 | CDRATIO_X4, 1 },
0131     [MSEL_PP32_SLOW_AESOPT_DC] =  { CFGWDTH_32 | CDRATIO_X8, 1 },
0132 };
0133
0134 static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset)
0135 {
0136     return readl(priv->fpga_base_addr + reg_offset);
0137 }
0138
0139 static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset,
0140                 u32 value)
0141 {
0142     writel(value, priv->fpga_base_addr + reg_offset);
0143 }
0144
0145 static u32 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv,
0146                   u32 reg_offset)
0147 {
0148     return __raw_readl(priv->fpga_base_addr + reg_offset);
0149 }
0150
0151 static void socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv,
0152                     u32 reg_offset, u32 value)
0153 {
0154     __raw_writel(value, priv->fpga_base_addr + reg_offset);
0155 }
0156
0157 static void socfpga_fpga_data_writel(struct socfpga_fpga_priv *priv, u32 value)
0158 {
0159     writel(value, priv->fpga_data_addr);
0160 }
0161
0162 static inline void socfpga_fpga_set_bitsl(struct socfpga_fpga_priv *priv,
0163                       u32 offset, u32 bits)
0164 {
0165     u32 val;
0166
0167     val = socfpga_fpga_readl(priv, offset);
0168     val |= bits;
0169     socfpga_fpga_writel(priv, offset, val);
0170 }
0171
0172 static inline void socfpga_fpga_clr_bitsl(struct socfpga_fpga_priv *priv,
0173                       u32 offset, u32 bits)
0174 {
0175     u32 val;
0176
0177     val = socfpga_fpga_readl(priv, offset);
0178     val &= ~bits;
0179     socfpga_fpga_writel(priv, offset, val);
0180 }
0181
0182 static u32 socfpga_fpga_mon_status_get(struct socfpga_fpga_priv *priv)
0183 {
0184     return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST) &
0185         SOCFPGA_FPGMGR_MON_STATUS_MASK;
0186 }
0187
0188 static u32 socfpga_fpga_state_get(struct socfpga_fpga_priv *priv)
0189 {
0190     u32 status = socfpga_fpga_mon_status_get(priv);
0191
0192     if ((status & SOCFPGA_FPGMGR_MON_FPGA_POWER_ON) == 0)
0193         return SOCFPGA_FPGMGR_STAT_POWER_OFF;
0194
0195     return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST) &
0196         SOCFPGA_FPGMGR_STAT_STATE_MASK;
0197 }
0198
0199 static void socfpga_fpga_clear_done_status(struct socfpga_fpga_priv *priv)
0200 {
0201     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST,
0202                 SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE);
0203 }
0204
0205 /*
0206  * Set the DCLKCNT, wait for DCLKSTAT to report the count completed, and clear
0207  * the complete status.
0208  */
0209 static int socfpga_fpga_dclk_set_and_wait_clear(struct socfpga_fpga_priv *priv,
0210                         u32 count)
0211 {
0212     int timeout = 2;
0213     u32 done;
0214
0215     /* Clear any existing DONE status. */
0216     if (socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST))
0217         socfpga_fpga_clear_done_status(priv);
0218
0219     /* Issue the DCLK count. */
0220     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKCNT_OFST, count);
0221
0222     /* Poll DCLKSTAT to see if it completed in the timeout period. */
0223     do {
0224         done = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST);
0225         if (done == SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE) {
0226             socfpga_fpga_clear_done_status(priv);
0227             return 0;
0228         }
0229         udelay(1);
0230     } while (timeout--);
0231
0232     return -ETIMEDOUT;
0233 }
0234
0235 static int socfpga_fpga_wait_for_state(struct socfpga_fpga_priv *priv,
0236                        u32 state)
0237 {
0238     int timeout = 2;
0239
0240     /*
0241      * HW doesn't support an interrupt for changes in state, so poll to see
0242      * if it matches the requested state within the timeout period.
0243      */
0244     do {
0245         if ((socfpga_fpga_state_get(priv) & state) != 0)
0246             return 0;
0247         msleep(20);
0248     } while (timeout--);
0249
0250     return -ETIMEDOUT;
0251 }
0252
0253 static void socfpga_fpga_enable_irqs(struct socfpga_fpga_priv *priv, u32 irqs)
0254 {
0255     /* set irqs to level sensitive */
0256     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST, 0);
0257
0258     /* set interrupt polarity */
0259     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INT_POL_OFST, irqs);
0260
0261     /* clear irqs */
0262     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);
0263
0264     /* unmask interrupts */
0265     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTMSK_OFST, 0);
0266
0267     /* enable interrupts */
0268     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, irqs);
0269 }
0270
0271 static void socfpga_fpga_disable_irqs(struct socfpga_fpga_priv *priv)
0272 {
0273     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);
0274 }
0275
0276 static irqreturn_t socfpga_fpga_isr(int irq, void *dev_id)
0277 {
0278     struct socfpga_fpga_priv *priv = dev_id;
0279     u32 irqs, st;
0280     bool conf_done, nstatus;
0281
0282     /* clear irqs */
0283     irqs = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST);
0284
0285     socfpga_fpga_raw_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);
0286
0287     st = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST);
0288     conf_done = (st & SOCFPGA_FPGMGR_MON_CONF_DONE) != 0;
0289     nstatus = (st & SOCFPGA_FPGMGR_MON_NSTATUS) != 0;
0290
0291     /* success */
0292     if (conf_done && nstatus) {
0293         /* disable irqs */
0294         socfpga_fpga_raw_writel(priv,
0295                     SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);
0296         complete(&priv->status_complete);
0297     }
0298
0299     return IRQ_HANDLED;
0300 }
0301
0302 static int socfpga_fpga_wait_for_config_done(struct socfpga_fpga_priv *priv)
0303 {
0304     int timeout, ret = 0;
0305
0306     socfpga_fpga_disable_irqs(priv);
0307     init_completion(&priv->status_complete);
0308     socfpga_fpga_enable_irqs(priv, SOCFPGA_FPGMGR_MON_CONF_DONE);
0309
0310     timeout = wait_for_completion_interruptible_timeout(
0311                         &priv->status_complete,
0312                         msecs_to_jiffies(10));
0313     if (timeout == 0)
0314         ret = -ETIMEDOUT;
0315
0316     socfpga_fpga_disable_irqs(priv);
0317     return ret;
0318 }
0319
0320 static int socfpga_fpga_cfg_mode_get(struct socfpga_fpga_priv *priv)
0321 {
0322     u32 msel;
0323
0324     msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST);
0325     msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK;
0326     msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT;
0327
0328     /* Check that this MSEL setting is supported */
0329     if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid)
0330         return -EINVAL;
0331
0332     return msel;
0333 }
0334
0335 static int socfpga_fpga_cfg_mode_set(struct socfpga_fpga_priv *priv)
0336 {
0337     u32 ctrl_reg;
0338     int mode;
0339
0340     /* get value from MSEL pins */
0341     mode = socfpga_fpga_cfg_mode_get(priv);
0342     if (mode < 0)
0343         return mode;
0344
0345     /* Adjust CTRL for the CDRATIO */
0346     ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
0347     ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK;
0348     ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK;
0349     ctrl_reg |= cfgmgr_modes[mode].ctrl;
0350
0351     /* Set NCE to 0. */
0352     ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE;
0353     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
0354
0355     return 0;
0356 }
0357
0358 static int socfpga_fpga_reset(struct fpga_manager *mgr)
0359 {
0360     struct socfpga_fpga_priv *priv = mgr->priv;
0361     u32 ctrl_reg, status;
0362     int ret;
0363
0364     /*
0365      * Step 1:
0366      *  - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode
0367      *  - Set CTRL.NCE to 0
0368      */
0369     ret = socfpga_fpga_cfg_mode_set(priv);
0370     if (ret)
0371         return ret;
0372
0373     /* Step 2: Set CTRL.EN to 1 */
0374     socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
0375                    SOCFPGA_FPGMGR_CTL_EN);
0376
0377     /* Step 3: Set CTRL.NCONFIGPULL to 1 to put FPGA in reset */
0378     ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
0379     ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL;
0380     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
0381
0382     /* Step 4: Wait for STATUS.MODE to report FPGA is in reset phase */
0383     status = socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_RESET);
0384
0385     /* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */
0386     ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCFGPULL;
0387     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
0388
0389     /* Timeout waiting for reset */
0390     if (status)
0391         return -ETIMEDOUT;
0392
0393     return 0;
0394 }
0395
0396 /*
0397  * Prepare the FPGA to receive the configuration data.
0398  */
0399 static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr,
0400                        struct fpga_image_info *info,
0401                        const char *buf, size_t count)
0402 {
0403     struct socfpga_fpga_priv *priv = mgr->priv;
0404     int ret;
0405
0406     if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
0407         dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
0408         return -EINVAL;
0409     }
0410     /* Steps 1 - 5: Reset the FPGA */
0411     ret = socfpga_fpga_reset(mgr);
0412     if (ret)
0413         return ret;
0414
0415     /* Step 6: Wait for FPGA to enter configuration phase */
0416     if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_CFG))
0417         return -ETIMEDOUT;
0418
0419     /* Step 7: Clear nSTATUS interrupt */
0420     socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST,
0421                 SOCFPGA_FPGMGR_MON_NSTATUS);
0422
0423     /* Step 8: Set CTRL.AXICFGEN to 1 to enable transfer of config data */
0424     socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
0425                    SOCFPGA_FPGMGR_CTL_AXICFGEN);
0426
0427     return 0;
0428 }
0429
0430 /*
0431  * Step 9: write data to the FPGA data register
0432  */
0433 static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr,
0434                         const char *buf, size_t count)
0435 {
0436     struct socfpga_fpga_priv *priv = mgr->priv;
0437     u32 *buffer_32 = (u32 *)buf;
0438     size_t i = 0;
0439
0440     if (count <= 0)
0441         return -EINVAL;
0442
0443     /* Write out the complete 32-bit chunks. */
0444     while (count >= sizeof(u32)) {
0445         socfpga_fpga_data_writel(priv, buffer_32[i++]);
0446         count -= sizeof(u32);
0447     }
0448
0449     /* Write out remaining non 32-bit chunks. */
0450     switch (count) {
0451     case 3:
0452         socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x00ffffff);
0453         break;
0454     case 2:
0455         socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x0000ffff);
0456         break;
0457     case 1:
0458         socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x000000ff);
0459         break;
0460     case 0:
0461         break;
0462     default:
0463         /* This will never happen. */
0464         return -EFAULT;
0465     }
0466
0467     return 0;
0468 }
0469
0470 static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr,
0471                            struct fpga_image_info *info)
0472 {
0473     struct socfpga_fpga_priv *priv = mgr->priv;
0474     u32 status;
0475
0476     /*
0477      * Step 10:
0478      *  - Observe CONF_DONE and nSTATUS (active low)
0479      *  - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful
0480      *  - if CONF_DONE = 0 and nSTATUS = 0, configuration failed
0481      */
0482     status = socfpga_fpga_wait_for_config_done(priv);
0483     if (status)
0484         return status;
0485
0486     /* Step 11: Clear CTRL.AXICFGEN to disable transfer of config data */
0487     socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
0488                    SOCFPGA_FPGMGR_CTL_AXICFGEN);
0489
0490     /*
0491      * Step 12:
0492      *  - Write 4 to DCLKCNT
0493      *  - Wait for STATUS.DCNTDONE = 1
0494      *  - Clear W1C bit in STATUS.DCNTDONE
0495      */
0496     if (socfpga_fpga_dclk_set_and_wait_clear(priv, 4))
0497         return -ETIMEDOUT;
0498
0499     /* Step 13: Wait for STATUS.MODE to report USER MODE */
0500     if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_USER_MODE))
0501         return -ETIMEDOUT;
0502
0503     /* Step 14: Set CTRL.EN to 0 */
0504     socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
0505                    SOCFPGA_FPGMGR_CTL_EN);
0506
0507     return 0;
0508 }
0509
0510 /* Translate state register values to FPGA framework state */
0511 static const enum fpga_mgr_states socfpga_state_to_framework_state[] = {
0512     [SOCFPGA_FPGMGR_STAT_POWER_OFF] = FPGA_MGR_STATE_POWER_OFF,
0513     [SOCFPGA_FPGMGR_STAT_RESET] = FPGA_MGR_STATE_RESET,
0514     [SOCFPGA_FPGMGR_STAT_CFG] = FPGA_MGR_STATE_WRITE_INIT,
0515     [SOCFPGA_FPGMGR_STAT_INIT] = FPGA_MGR_STATE_WRITE_INIT,
0516     [SOCFPGA_FPGMGR_STAT_USER_MODE] = FPGA_MGR_STATE_OPERATING,
0517     [SOCFPGA_FPGMGR_STAT_UNKNOWN] = FPGA_MGR_STATE_UNKNOWN,
0518 };
0519
0520 static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr)
0521 {
0522     struct socfpga_fpga_priv *priv = mgr->priv;
0523     enum fpga_mgr_states ret;
0524     u32 state;
0525
0526     state = socfpga_fpga_state_get(priv);
0527
0528     if (state < ARRAY_SIZE(socfpga_state_to_framework_state))
0529         ret = socfpga_state_to_framework_state[state];
0530     else
0531         ret = FPGA_MGR_STATE_UNKNOWN;
0532
0533     return ret;
0534 }
0535
0536 static const struct fpga_manager_ops socfpga_fpga_ops = {
0537     .state = socfpga_fpga_ops_state,
0538     .write_init = socfpga_fpga_ops_configure_init,
0539     .write = socfpga_fpga_ops_configure_write,
0540     .write_complete = socfpga_fpga_ops_configure_complete,
0541 };
0542
0543 static int socfpga_fpga_probe(struct platform_device *pdev)
0544 {
0545     struct device *dev = &pdev->dev;
0546     struct socfpga_fpga_priv *priv;
0547     struct fpga_manager *mgr;
0548     struct resource *res;
0549     int ret;
0550
0551     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0552     if (!priv)
0553         return -ENOMEM;
0554
0555     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0556     priv->fpga_base_addr = devm_ioremap_resource(dev, res);
0557     if (IS_ERR(priv->fpga_base_addr))
0558         return PTR_ERR(priv->fpga_base_addr);
0559
0560     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0561     priv->fpga_data_addr = devm_ioremap_resource(dev, res);
0562     if (IS_ERR(priv->fpga_data_addr))
0563         return PTR_ERR(priv->fpga_data_addr);
0564
0565     priv->irq = platform_get_irq(pdev, 0);
0566     if (priv->irq < 0)
0567         return priv->irq;
0568
0569     ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0,
0570                    dev_name(dev), priv);
0571     if (ret)
0572         return ret;
0573
0574     mgr = devm_fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
0575                      &socfpga_fpga_ops, priv);
0576     return PTR_ERR_OR_ZERO(mgr);
0577 }
0578
0579 #ifdef CONFIG_OF
0580 static const struct of_device_id socfpga_fpga_of_match[] = {
0581     { .compatible = "altr,socfpga-fpga-mgr", },
0582     {},
0583 };
0584
0585 MODULE_DEVICE_TABLE(of, socfpga_fpga_of_match);
0586 #endif
0587
0588 static struct platform_driver socfpga_fpga_driver = {
0589     .probe = socfpga_fpga_probe,
0590     .driver = {
0591         .name   = "socfpga_fpga_manager",
0592         .of_match_table = of_match_ptr(socfpga_fpga_of_match),
0593     },
0594 };
0595
0596 module_platform_driver(socfpga_fpga_driver);
0597
0598 MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
0599 MODULE_DESCRIPTION("Altera SOCFPGA FPGA Manager");
0600 MODULE_LICENSE("GPL v2");