drivers/fpga/socfpga-a10.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FPGA Manager Driver for Altera Arria10 SoCFPGA
0004  *
0005  * Copyright (C) 2015-2016 Altera Corporation
0006  */
0007 #include <linux/clk.h>
0008 #include <linux/device.h>
0009 #include <linux/delay.h>
0010 #include <linux/fpga/fpga-mgr.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/regmap.h>
0015
0016 #define A10_FPGAMGR_DCLKCNT_OFST                0x08
0017 #define A10_FPGAMGR_DCLKSTAT_OFST               0x0c
0018 #define A10_FPGAMGR_IMGCFG_CTL_00_OFST              0x70
0019 #define A10_FPGAMGR_IMGCFG_CTL_01_OFST              0x74
0020 #define A10_FPGAMGR_IMGCFG_CTL_02_OFST              0x78
0021 #define A10_FPGAMGR_IMGCFG_STAT_OFST                0x80
0022
0023 #define A10_FPGAMGR_DCLKSTAT_DCLKDONE               BIT(0)
0024
0025 #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG       BIT(0)
0026 #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS       BIT(1)
0027 #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE       BIT(2)
0028 #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG           BIT(8)
0029 #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE        BIT(16)
0030 #define A10_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE        BIT(24)
0031
0032 #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG        BIT(0)
0033 #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST        BIT(16)
0034 #define A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE           BIT(24)
0035
0036 #define A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL           BIT(0)
0037 #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK      (BIT(16) | BIT(17))
0038 #define A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT         16
0039 #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH          BIT(24)
0040 #define A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT        24
0041
0042 #define A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR           BIT(0)
0043 #define A10_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE      BIT(1)
0044 #define A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE            BIT(2)
0045 #define A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN         BIT(4)
0046 #define A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN         BIT(6)
0047 #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY            BIT(9)
0048 #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE         BIT(10)
0049 #define A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR            BIT(11)
0050 #define A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN         BIT(12)
0051 #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK   (BIT(16) | BIT(17) | BIT(18))
0052 #define A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT              16
0053
0054 /* FPGA CD Ratio Value */
0055 #define CDRATIO_x1                      0x0
0056 #define CDRATIO_x2                      0x1
0057 #define CDRATIO_x4                      0x2
0058 #define CDRATIO_x8                      0x3
0059
0060 /* Configuration width 16/32 bit */
0061 #define CFGWDTH_32                      1
0062 #define CFGWDTH_16                      0
0063
0064 /*
0065  * struct a10_fpga_priv - private data for fpga manager
0066  * @regmap: regmap for register access
0067  * @fpga_data_addr: iomap for single address data register to FPGA
0068  * @clk: clock
0069  */
0070 struct a10_fpga_priv {
0071     struct regmap *regmap;
0072     void __iomem *fpga_data_addr;
0073     struct clk *clk;
0074 };
0075
0076 static bool socfpga_a10_fpga_writeable_reg(struct device *dev, unsigned int reg)
0077 {
0078     switch (reg) {
0079     case A10_FPGAMGR_DCLKCNT_OFST:
0080     case A10_FPGAMGR_DCLKSTAT_OFST:
0081     case A10_FPGAMGR_IMGCFG_CTL_00_OFST:
0082     case A10_FPGAMGR_IMGCFG_CTL_01_OFST:
0083     case A10_FPGAMGR_IMGCFG_CTL_02_OFST:
0084         return true;
0085     }
0086     return false;
0087 }
0088
0089 static bool socfpga_a10_fpga_readable_reg(struct device *dev, unsigned int reg)
0090 {
0091     switch (reg) {
0092     case A10_FPGAMGR_DCLKCNT_OFST:
0093     case A10_FPGAMGR_DCLKSTAT_OFST:
0094     case A10_FPGAMGR_IMGCFG_CTL_00_OFST:
0095     case A10_FPGAMGR_IMGCFG_CTL_01_OFST:
0096     case A10_FPGAMGR_IMGCFG_CTL_02_OFST:
0097     case A10_FPGAMGR_IMGCFG_STAT_OFST:
0098         return true;
0099     }
0100     return false;
0101 }
0102
0103 static const struct regmap_config socfpga_a10_fpga_regmap_config = {
0104     .reg_bits = 32,
0105     .reg_stride = 4,
0106     .val_bits = 32,
0107     .writeable_reg = socfpga_a10_fpga_writeable_reg,
0108     .readable_reg = socfpga_a10_fpga_readable_reg,
0109     .max_register = A10_FPGAMGR_IMGCFG_STAT_OFST,
0110     .cache_type = REGCACHE_NONE,
0111 };
0112
0113 /*
0114  * from the register map description of cdratio in imgcfg_ctrl_02:
0115  *  Normal Configuration    : 32bit Passive Parallel
0116  *  Partial Reconfiguration : 16bit Passive Parallel
0117  */
0118 static void socfpga_a10_fpga_set_cfg_width(struct a10_fpga_priv *priv,
0119                        int width)
0120 {
0121     width <<= A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SHIFT;
0122
0123     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
0124                A10_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH, width);
0125 }
0126
0127 static void socfpga_a10_fpga_generate_dclks(struct a10_fpga_priv *priv,
0128                         u32 count)
0129 {
0130     u32 val;
0131
0132     /* Clear any existing DONE status. */
0133     regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST,
0134              A10_FPGAMGR_DCLKSTAT_DCLKDONE);
0135
0136     /* Issue the DCLK regmap. */
0137     regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count);
0138
0139     /* wait till the dclkcnt done */
0140     regmap_read_poll_timeout(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, val,
0141                  val, 1, 100);
0142
0143     /* Clear DONE status. */
0144     regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST,
0145              A10_FPGAMGR_DCLKSTAT_DCLKDONE);
0146 }
0147
0148 #define RBF_ENCRYPTION_MODE_OFFSET      69
0149 #define RBF_DECOMPRESS_OFFSET           229
0150
0151 static int socfpga_a10_fpga_encrypted(u32 *buf32, size_t buf32_size)
0152 {
0153     if (buf32_size < RBF_ENCRYPTION_MODE_OFFSET + 1)
0154         return -EINVAL;
0155
0156     /* Is the bitstream encrypted? */
0157     return ((buf32[RBF_ENCRYPTION_MODE_OFFSET] >> 2) & 3) != 0;
0158 }
0159
0160 static int socfpga_a10_fpga_compressed(u32 *buf32, size_t buf32_size)
0161 {
0162     if (buf32_size < RBF_DECOMPRESS_OFFSET + 1)
0163         return -EINVAL;
0164
0165     /* Is the bitstream compressed? */
0166     return !((buf32[RBF_DECOMPRESS_OFFSET] >> 1) & 1);
0167 }
0168
0169 static unsigned int socfpga_a10_fpga_get_cd_ratio(unsigned int cfg_width,
0170                           bool encrypt, bool compress)
0171 {
0172     unsigned int cd_ratio;
0173
0174     /*
0175      * cd ratio is dependent on cfg width and whether the bitstream
0176      * is encrypted and/or compressed.
0177      *
0178      * | width | encr. | compr. | cd ratio |
0179      * |  16   |   0   |   0    |     1    |
0180      * |  16   |   0   |   1    |     4    |
0181      * |  16   |   1   |   0    |     2    |
0182      * |  16   |   1   |   1    |     4    |
0183      * |  32   |   0   |   0    |     1    |
0184      * |  32   |   0   |   1    |     8    |
0185      * |  32   |   1   |   0    |     4    |
0186      * |  32   |   1   |   1    |     8    |
0187      */
0188     if (!compress && !encrypt)
0189         return CDRATIO_x1;
0190
0191     if (compress)
0192         cd_ratio = CDRATIO_x4;
0193     else
0194         cd_ratio = CDRATIO_x2;
0195
0196     /* If 32 bit, double the cd ratio by incrementing the field  */
0197     if (cfg_width == CFGWDTH_32)
0198         cd_ratio += 1;
0199
0200     return cd_ratio;
0201 }
0202
0203 static int socfpga_a10_fpga_set_cdratio(struct fpga_manager *mgr,
0204                     unsigned int cfg_width,
0205                     const char *buf, size_t count)
0206 {
0207     struct a10_fpga_priv *priv = mgr->priv;
0208     unsigned int cd_ratio;
0209     int encrypt, compress;
0210
0211     encrypt = socfpga_a10_fpga_encrypted((u32 *)buf, count / 4);
0212     if (encrypt < 0)
0213         return -EINVAL;
0214
0215     compress = socfpga_a10_fpga_compressed((u32 *)buf, count / 4);
0216     if (compress < 0)
0217         return -EINVAL;
0218
0219     cd_ratio = socfpga_a10_fpga_get_cd_ratio(cfg_width, encrypt, compress);
0220
0221     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
0222                A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MASK,
0223                cd_ratio << A10_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SHIFT);
0224
0225     return 0;
0226 }
0227
0228 static u32 socfpga_a10_fpga_read_stat(struct a10_fpga_priv *priv)
0229 {
0230     u32 val;
0231
0232     regmap_read(priv->regmap, A10_FPGAMGR_IMGCFG_STAT_OFST, &val);
0233
0234     return val;
0235 }
0236
0237 static int socfpga_a10_fpga_wait_for_pr_ready(struct a10_fpga_priv *priv)
0238 {
0239     u32 reg, i;
0240
0241     for (i = 0; i < 10 ; i++) {
0242         reg = socfpga_a10_fpga_read_stat(priv);
0243
0244         if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR)
0245             return -EINVAL;
0246
0247         if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY)
0248             return 0;
0249     }
0250
0251     return -ETIMEDOUT;
0252 }
0253
0254 static int socfpga_a10_fpga_wait_for_pr_done(struct a10_fpga_priv *priv)
0255 {
0256     u32 reg, i;
0257
0258     for (i = 0; i < 10 ; i++) {
0259         reg = socfpga_a10_fpga_read_stat(priv);
0260
0261         if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR)
0262             return -EINVAL;
0263
0264         if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE)
0265             return 0;
0266     }
0267
0268     return -ETIMEDOUT;
0269 }
0270
0271 /* Start the FPGA programming by initialize the FPGA Manager */
0272 static int socfpga_a10_fpga_write_init(struct fpga_manager *mgr,
0273                        struct fpga_image_info *info,
0274                        const char *buf, size_t count)
0275 {
0276     struct a10_fpga_priv *priv = mgr->priv;
0277     unsigned int cfg_width;
0278     u32 msel, stat, mask;
0279     int ret;
0280
0281     if (info->flags & FPGA_MGR_PARTIAL_RECONFIG)
0282         cfg_width = CFGWDTH_16;
0283     else
0284         return -EINVAL;
0285
0286     /* Check for passive parallel (msel == 000 or 001) */
0287     msel = socfpga_a10_fpga_read_stat(priv);
0288     msel &= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_MASK;
0289     msel >>= A10_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SHIFT;
0290     if ((msel != 0) && (msel != 1)) {
0291         dev_dbg(&mgr->dev, "Fail: invalid msel=%d\n", msel);
0292         return -EINVAL;
0293     }
0294
0295     /* Make sure no external devices are interfering */
0296     stat = socfpga_a10_fpga_read_stat(priv);
0297     mask = A10_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN |
0298            A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN;
0299     if ((stat & mask) != mask)
0300         return -EINVAL;
0301
0302     /* Set cfg width */
0303     socfpga_a10_fpga_set_cfg_width(priv, cfg_width);
0304
0305     /* Determine cd ratio from bitstream header and set cd ratio */
0306     ret = socfpga_a10_fpga_set_cdratio(mgr, cfg_width, buf, count);
0307     if (ret)
0308         return ret;
0309
0310     /*
0311      * Clear s2f_nce to enable chip select.  Leave pr_request
0312      * unasserted and override disabled.
0313      */
0314     regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
0315              A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG);
0316
0317     /* Set cfg_ctrl to enable s2f dclk and data */
0318     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
0319                A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL,
0320                A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL);
0321
0322     /*
0323      * Disable overrides not needed for pr.
0324      * s2f_config==1 leaves reset deasseted.
0325      */
0326     regmap_write(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_00_OFST,
0327              A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG |
0328              A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS |
0329              A10_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE |
0330              A10_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG);
0331
0332     /* Enable override for data, dclk, nce, and pr_request to CSS */
0333     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
0334                A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG, 0);
0335
0336     /* Send some clocks to clear out any errors */
0337     socfpga_a10_fpga_generate_dclks(priv, 256);
0338
0339     /* Assert pr_request */
0340     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
0341                A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST,
0342                A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST);
0343
0344     /* Provide 2048 DCLKs before starting the config data streaming. */
0345     socfpga_a10_fpga_generate_dclks(priv, 0x7ff);
0346
0347     /* Wait for pr_ready */
0348     return socfpga_a10_fpga_wait_for_pr_ready(priv);
0349 }
0350
0351 /*
0352  * write data to the FPGA data register
0353  */
0354 static int socfpga_a10_fpga_write(struct fpga_manager *mgr, const char *buf,
0355                   size_t count)
0356 {
0357     struct a10_fpga_priv *priv = mgr->priv;
0358     u32 *buffer_32 = (u32 *)buf;
0359     size_t i = 0;
0360
0361     if (count <= 0)
0362         return -EINVAL;
0363
0364     /* Write out the complete 32-bit chunks */
0365     while (count >= sizeof(u32)) {
0366         writel(buffer_32[i++], priv->fpga_data_addr);
0367         count -= sizeof(u32);
0368     }
0369
0370     /* Write out remaining non 32-bit chunks */
0371     switch (count) {
0372     case 3:
0373         writel(buffer_32[i++] & 0x00ffffff, priv->fpga_data_addr);
0374         break;
0375     case 2:
0376         writel(buffer_32[i++] & 0x0000ffff, priv->fpga_data_addr);
0377         break;
0378     case 1:
0379         writel(buffer_32[i++] & 0x000000ff, priv->fpga_data_addr);
0380         break;
0381     case 0:
0382         break;
0383     default:
0384         /* This will never happen */
0385         return -EFAULT;
0386     }
0387
0388     return 0;
0389 }
0390
0391 static int socfpga_a10_fpga_write_complete(struct fpga_manager *mgr,
0392                        struct fpga_image_info *info)
0393 {
0394     struct a10_fpga_priv *priv = mgr->priv;
0395     u32 reg;
0396     int ret;
0397
0398     /* Wait for pr_done */
0399     ret = socfpga_a10_fpga_wait_for_pr_done(priv);
0400
0401     /* Clear pr_request */
0402     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
0403                A10_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST, 0);
0404
0405     /* Send some clocks to clear out any errors */
0406     socfpga_a10_fpga_generate_dclks(priv, 256);
0407
0408     /* Disable s2f dclk and data */
0409     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST,
0410                A10_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL, 0);
0411
0412     /* Deassert chip select */
0413     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
0414                A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE,
0415                A10_FPGAMGR_IMGCFG_CTL_01_S2F_NCE);
0416
0417     /* Disable data, dclk, nce, and pr_request override to CSS */
0418     regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_01_OFST,
0419                A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG,
0420                A10_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG);
0421
0422     /* Return any errors regarding pr_done or pr_error */
0423     if (ret)
0424         return ret;
0425
0426     /* Final check */
0427     reg = socfpga_a10_fpga_read_stat(priv);
0428
0429     if (((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE) == 0) ||
0430         ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN) == 0) ||
0431         ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)) {
0432         dev_dbg(&mgr->dev,
0433             "Timeout in final check. Status=%08xf\n", reg);
0434         return -ETIMEDOUT;
0435     }
0436
0437     return 0;
0438 }
0439
0440 static enum fpga_mgr_states socfpga_a10_fpga_state(struct fpga_manager *mgr)
0441 {
0442     struct a10_fpga_priv *priv = mgr->priv;
0443     u32 reg = socfpga_a10_fpga_read_stat(priv);
0444
0445     if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_USERMODE)
0446         return FPGA_MGR_STATE_OPERATING;
0447
0448     if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_PR_READY)
0449         return FPGA_MGR_STATE_WRITE;
0450
0451     if (reg & A10_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR)
0452         return FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
0453
0454     if ((reg & A10_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN) == 0)
0455         return FPGA_MGR_STATE_RESET;
0456
0457     return FPGA_MGR_STATE_UNKNOWN;
0458 }
0459
0460 static const struct fpga_manager_ops socfpga_a10_fpga_mgr_ops = {
0461     .initial_header_size = (RBF_DECOMPRESS_OFFSET + 1) * 4,
0462     .state = socfpga_a10_fpga_state,
0463     .write_init = socfpga_a10_fpga_write_init,
0464     .write = socfpga_a10_fpga_write,
0465     .write_complete = socfpga_a10_fpga_write_complete,
0466 };
0467
0468 static int socfpga_a10_fpga_probe(struct platform_device *pdev)
0469 {
0470     struct device *dev = &pdev->dev;
0471     struct a10_fpga_priv *priv;
0472     void __iomem *reg_base;
0473     struct fpga_manager *mgr;
0474     struct resource *res;
0475     int ret;
0476
0477     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0478     if (!priv)
0479         return -ENOMEM;
0480
0481     /* First mmio base is for register access */
0482     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0483     reg_base = devm_ioremap_resource(dev, res);
0484     if (IS_ERR(reg_base))
0485         return PTR_ERR(reg_base);
0486
0487     /* Second mmio base is for writing FPGA image data */
0488     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0489     priv->fpga_data_addr = devm_ioremap_resource(dev, res);
0490     if (IS_ERR(priv->fpga_data_addr))
0491         return PTR_ERR(priv->fpga_data_addr);
0492
0493     /* regmap for register access */
0494     priv->regmap = devm_regmap_init_mmio(dev, reg_base,
0495                          &socfpga_a10_fpga_regmap_config);
0496     if (IS_ERR(priv->regmap))
0497         return -ENODEV;
0498
0499     priv->clk = devm_clk_get(dev, NULL);
0500     if (IS_ERR(priv->clk)) {
0501         dev_err(dev, "no clock specified\n");
0502         return PTR_ERR(priv->clk);
0503     }
0504
0505     ret = clk_prepare_enable(priv->clk);
0506     if (ret) {
0507         dev_err(dev, "could not enable clock\n");
0508         return -EBUSY;
0509     }
0510
0511     mgr = fpga_mgr_register(dev, "SoCFPGA Arria10 FPGA Manager",
0512                 &socfpga_a10_fpga_mgr_ops, priv);
0513     if (IS_ERR(mgr)) {
0514         clk_disable_unprepare(priv->clk);
0515         return PTR_ERR(mgr);
0516     }
0517
0518     platform_set_drvdata(pdev, mgr);
0519
0520     return 0;
0521 }
0522
0523 static int socfpga_a10_fpga_remove(struct platform_device *pdev)
0524 {
0525     struct fpga_manager *mgr = platform_get_drvdata(pdev);
0526     struct a10_fpga_priv *priv = mgr->priv;
0527
0528     fpga_mgr_unregister(mgr);
0529     clk_disable_unprepare(priv->clk);
0530
0531     return 0;
0532 }
0533
0534 static const struct of_device_id socfpga_a10_fpga_of_match[] = {
0535     { .compatible = "altr,socfpga-a10-fpga-mgr", },
0536     {},
0537 };
0538
0539 MODULE_DEVICE_TABLE(of, socfpga_a10_fpga_of_match);
0540
0541 static struct platform_driver socfpga_a10_fpga_driver = {
0542     .probe = socfpga_a10_fpga_probe,
0543     .remove = socfpga_a10_fpga_remove,
0544     .driver = {
0545         .name   = "socfpga_a10_fpga_manager",
0546         .of_match_table = socfpga_a10_fpga_of_match,
0547     },
0548 };
0549
0550 module_platform_driver(socfpga_a10_fpga_driver);
0551
0552 MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
0553 MODULE_DESCRIPTION("SoCFPGA Arria10 FPGA Manager");
0554 MODULE_LICENSE("GPL v2");