drivers/fpga/microchip-spi.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Microchip Polarfire FPGA programming over slave SPI interface.
0004  */
0005
0006 #include <asm/unaligned.h>
0007 #include <linux/delay.h>
0008 #include <linux/fpga/fpga-mgr.h>
0009 #include <linux/module.h>
0010 #include <linux/of_device.h>
0011 #include <linux/spi/spi.h>
0012
0013 #define MPF_SPI_ISC_ENABLE  0x0B
0014 #define MPF_SPI_ISC_DISABLE 0x0C
0015 #define MPF_SPI_READ_STATUS 0x00
0016 #define MPF_SPI_READ_DATA   0x01
0017 #define MPF_SPI_FRAME_INIT  0xAE
0018 #define MPF_SPI_FRAME       0xEE
0019 #define MPF_SPI_PRG_MODE    0x01
0020 #define MPF_SPI_RELEASE     0x23
0021
0022 #define MPF_SPI_FRAME_SIZE  16
0023
0024 #define MPF_HEADER_SIZE_OFFSET  24
0025 #define MPF_DATA_SIZE_OFFSET    55
0026
0027 #define MPF_LOOKUP_TABLE_RECORD_SIZE        9
0028 #define MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET    0
0029 #define MPF_LOOKUP_TABLE_BLOCK_START_OFFSET 1
0030
0031 #define MPF_COMPONENTS_SIZE_ID  5
0032 #define MPF_BITSTREAM_ID    8
0033
0034 #define MPF_BITS_PER_COMPONENT_SIZE 22
0035
0036 #define MPF_STATUS_POLL_RETRIES     10000
0037 #define MPF_STATUS_BUSY         BIT(0)
0038 #define MPF_STATUS_READY        BIT(1)
0039 #define MPF_STATUS_SPI_VIOLATION    BIT(2)
0040 #define MPF_STATUS_SPI_ERROR        BIT(3)
0041
0042 struct mpf_priv {
0043     struct spi_device *spi;
0044     bool program_mode;
0045 };
0046
0047 static int mpf_read_status(struct spi_device *spi)
0048 {
0049     u8 status = 0, status_command = MPF_SPI_READ_STATUS;
0050     struct spi_transfer xfers[2] = { 0 };
0051     int ret;
0052
0053     /*
0054      * HW status is returned on MISO in the first byte after CS went
0055      * active. However, first reading can be inadequate, so we submit
0056      * two identical SPI transfers and use result of the later one.
0057      */
0058     xfers[0].tx_buf = &status_command;
0059     xfers[1].tx_buf = &status_command;
0060     xfers[0].rx_buf = &status;
0061     xfers[1].rx_buf = &status;
0062     xfers[0].len = 1;
0063     xfers[1].len = 1;
0064     xfers[0].cs_change = 1;
0065
0066     ret = spi_sync_transfer(spi, xfers, 2);
0067
0068     if ((status & MPF_STATUS_SPI_VIOLATION) ||
0069         (status & MPF_STATUS_SPI_ERROR))
0070         ret = -EIO;
0071
0072     return ret ? : status;
0073 }
0074
0075 static enum fpga_mgr_states mpf_ops_state(struct fpga_manager *mgr)
0076 {
0077     struct mpf_priv *priv = mgr->priv;
0078     struct spi_device *spi;
0079     bool program_mode;
0080     int status;
0081
0082     spi = priv->spi;
0083     program_mode = priv->program_mode;
0084     status = mpf_read_status(spi);
0085
0086     if (!program_mode && !status)
0087         return FPGA_MGR_STATE_OPERATING;
0088
0089     return FPGA_MGR_STATE_UNKNOWN;
0090 }
0091
0092 static int mpf_ops_parse_header(struct fpga_manager *mgr,
0093                 struct fpga_image_info *info,
0094                 const char *buf, size_t count)
0095 {
0096     size_t component_size_byte_num, component_size_byte_off,
0097            components_size_start, bitstream_start,
0098            block_id_offset, block_start_offset;
0099     u8 header_size, blocks_num, block_id;
0100     u32 block_start, component_size;
0101     u16 components_num, i;
0102
0103     if (!buf) {
0104         dev_err(&mgr->dev, "Image buffer is not provided\n");
0105         return -EINVAL;
0106     }
0107
0108     header_size = *(buf + MPF_HEADER_SIZE_OFFSET);
0109     if (header_size > count) {
0110         info->header_size = header_size;
0111         return -EAGAIN;
0112     }
0113
0114     /*
0115      * Go through look-up table to find out where actual bitstream starts
0116      * and where sizes of components of the bitstream lies.
0117      */
0118     blocks_num = *(buf + header_size - 1);
0119     block_id_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_ID_OFFSET;
0120     block_start_offset = header_size + MPF_LOOKUP_TABLE_BLOCK_START_OFFSET;
0121
0122     header_size += blocks_num * MPF_LOOKUP_TABLE_RECORD_SIZE;
0123     if (header_size > count) {
0124         info->header_size = header_size;
0125         return -EAGAIN;
0126     }
0127
0128     components_size_start = 0;
0129     bitstream_start = 0;
0130
0131     while (blocks_num--) {
0132         block_id = *(buf + block_id_offset);
0133         block_start = get_unaligned_le32(buf + block_start_offset);
0134
0135         switch (block_id) {
0136         case MPF_BITSTREAM_ID:
0137             bitstream_start = block_start;
0138             info->header_size = block_start;
0139             if (block_start > count)
0140                 return -EAGAIN;
0141
0142             break;
0143         case MPF_COMPONENTS_SIZE_ID:
0144             components_size_start = block_start;
0145             break;
0146         default:
0147             break;
0148         }
0149
0150         if (bitstream_start && components_size_start)
0151             break;
0152
0153         block_id_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
0154         block_start_offset += MPF_LOOKUP_TABLE_RECORD_SIZE;
0155     }
0156
0157     if (!bitstream_start || !components_size_start) {
0158         dev_err(&mgr->dev, "Failed to parse header look-up table\n");
0159         return -EFAULT;
0160     }
0161
0162     /*
0163      * Parse bitstream size.
0164      * Sizes of components of the bitstream are 22-bits long placed next
0165      * to each other. Image header should be extended by now up to where
0166      * actual bitstream starts, so no need for overflow check anymore.
0167      */
0168     components_num = get_unaligned_le16(buf + MPF_DATA_SIZE_OFFSET);
0169
0170     for (i = 0; i < components_num; i++) {
0171         component_size_byte_num =
0172             (i * MPF_BITS_PER_COMPONENT_SIZE) / BITS_PER_BYTE;
0173         component_size_byte_off =
0174             (i * MPF_BITS_PER_COMPONENT_SIZE) % BITS_PER_BYTE;
0175
0176         component_size = get_unaligned_le32(buf +
0177                             components_size_start +
0178                             component_size_byte_num);
0179         component_size >>= component_size_byte_off;
0180         component_size &= GENMASK(MPF_BITS_PER_COMPONENT_SIZE - 1, 0);
0181
0182         info->data_size += component_size * MPF_SPI_FRAME_SIZE;
0183     }
0184
0185     return 0;
0186 }
0187
0188 /* Poll HW status until busy bit is cleared and mask bits are set. */
0189 static int mpf_poll_status(struct spi_device *spi, u8 mask)
0190 {
0191     int status, retries = MPF_STATUS_POLL_RETRIES;
0192
0193     while (retries--) {
0194         status = mpf_read_status(spi);
0195         if (status < 0)
0196             return status;
0197
0198         if (status & MPF_STATUS_BUSY)
0199             continue;
0200
0201         if (!mask || (status & mask))
0202             return status;
0203     }
0204
0205     return -EBUSY;
0206 }
0207
0208 static int mpf_spi_write(struct spi_device *spi, const void *buf, size_t buf_size)
0209 {
0210     int status = mpf_poll_status(spi, 0);
0211
0212     if (status < 0)
0213         return status;
0214
0215     return spi_write(spi, buf, buf_size);
0216 }
0217
0218 static int mpf_spi_write_then_read(struct spi_device *spi,
0219                    const void *txbuf, size_t txbuf_size,
0220                    void *rxbuf, size_t rxbuf_size)
0221 {
0222     const u8 read_command[] = { MPF_SPI_READ_DATA };
0223     int ret;
0224
0225     ret = mpf_spi_write(spi, txbuf, txbuf_size);
0226     if (ret)
0227         return ret;
0228
0229     ret = mpf_poll_status(spi, MPF_STATUS_READY);
0230     if (ret < 0)
0231         return ret;
0232
0233     return spi_write_then_read(spi, read_command, sizeof(read_command),
0234                    rxbuf, rxbuf_size);
0235 }
0236
0237 static int mpf_ops_write_init(struct fpga_manager *mgr,
0238                   struct fpga_image_info *info, const char *buf,
0239                   size_t count)
0240 {
0241     const u8 program_mode[] = { MPF_SPI_FRAME_INIT, MPF_SPI_PRG_MODE };
0242     const u8 isc_en_command[] = { MPF_SPI_ISC_ENABLE };
0243     struct mpf_priv *priv = mgr->priv;
0244     struct device *dev = &mgr->dev;
0245     struct spi_device *spi;
0246     u32 isc_ret = 0;
0247     int ret;
0248
0249     if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
0250         dev_err(dev, "Partial reconfiguration is not supported\n");
0251         return -EOPNOTSUPP;
0252     }
0253
0254     spi = priv->spi;
0255
0256     ret = mpf_spi_write_then_read(spi, isc_en_command, sizeof(isc_en_command),
0257                       &isc_ret, sizeof(isc_ret));
0258     if (ret || isc_ret) {
0259         dev_err(dev, "Failed to enable ISC: spi_ret %d, isc_ret %u\n",
0260             ret, isc_ret);
0261         return -EFAULT;
0262     }
0263
0264     ret = mpf_spi_write(spi, program_mode, sizeof(program_mode));
0265     if (ret) {
0266         dev_err(dev, "Failed to enter program mode: %d\n", ret);
0267         return ret;
0268     }
0269
0270     priv->program_mode = true;
0271
0272     return 0;
0273 }
0274
0275 static int mpf_ops_write(struct fpga_manager *mgr, const char *buf, size_t count)
0276 {
0277     u8 spi_frame_command[] = { MPF_SPI_FRAME };
0278     struct spi_transfer xfers[2] = { 0 };
0279     struct mpf_priv *priv = mgr->priv;
0280     struct device *dev = &mgr->dev;
0281     struct spi_device *spi;
0282     int ret, i;
0283
0284     if (count % MPF_SPI_FRAME_SIZE) {
0285         dev_err(dev, "Bitstream size is not a multiple of %d\n",
0286             MPF_SPI_FRAME_SIZE);
0287         return -EINVAL;
0288     }
0289
0290     spi = priv->spi;
0291
0292     xfers[0].tx_buf = spi_frame_command;
0293     xfers[0].len = sizeof(spi_frame_command);
0294
0295     for (i = 0; i < count / MPF_SPI_FRAME_SIZE; i++) {
0296         xfers[1].tx_buf = buf + i * MPF_SPI_FRAME_SIZE;
0297         xfers[1].len = MPF_SPI_FRAME_SIZE;
0298
0299         ret = mpf_poll_status(spi, 0);
0300         if (ret >= 0)
0301             ret = spi_sync_transfer(spi, xfers, ARRAY_SIZE(xfers));
0302
0303         if (ret) {
0304             dev_err(dev, "Failed to write bitstream frame %d/%zu\n",
0305                 i, count / MPF_SPI_FRAME_SIZE);
0306             return ret;
0307         }
0308     }
0309
0310     return 0;
0311 }
0312
0313 static int mpf_ops_write_complete(struct fpga_manager *mgr,
0314                   struct fpga_image_info *info)
0315 {
0316     const u8 isc_dis_command[] = { MPF_SPI_ISC_DISABLE };
0317     const u8 release_command[] = { MPF_SPI_RELEASE };
0318     struct mpf_priv *priv = mgr->priv;
0319     struct device *dev = &mgr->dev;
0320     struct spi_device *spi;
0321     int ret;
0322
0323     spi = priv->spi;
0324
0325     ret = mpf_spi_write(spi, isc_dis_command, sizeof(isc_dis_command));
0326     if (ret) {
0327         dev_err(dev, "Failed to disable ISC: %d\n", ret);
0328         return ret;
0329     }
0330
0331     usleep_range(1000, 2000);
0332
0333     ret = mpf_spi_write(spi, release_command, sizeof(release_command));
0334     if (ret) {
0335         dev_err(dev, "Failed to exit program mode: %d\n", ret);
0336         return ret;
0337     }
0338
0339     priv->program_mode = false;
0340
0341     return 0;
0342 }
0343
0344 static const struct fpga_manager_ops mpf_ops = {
0345     .state = mpf_ops_state,
0346     .initial_header_size = 71,
0347     .skip_header = true,
0348     .parse_header = mpf_ops_parse_header,
0349     .write_init = mpf_ops_write_init,
0350     .write = mpf_ops_write,
0351     .write_complete = mpf_ops_write_complete,
0352 };
0353
0354 static int mpf_probe(struct spi_device *spi)
0355 {
0356     struct device *dev = &spi->dev;
0357     struct fpga_manager *mgr;
0358     struct mpf_priv *priv;
0359
0360     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0361     if (!priv)
0362         return -ENOMEM;
0363
0364     priv->spi = spi;
0365
0366     mgr = devm_fpga_mgr_register(dev, "Microchip Polarfire SPI FPGA Manager",
0367                      &mpf_ops, priv);
0368
0369     return PTR_ERR_OR_ZERO(mgr);
0370 }
0371
0372 static const struct spi_device_id mpf_spi_ids[] = {
0373     { .name = "mpf-spi-fpga-mgr", },
0374     {},
0375 };
0376 MODULE_DEVICE_TABLE(spi, mpf_spi_ids);
0377
0378 #if IS_ENABLED(CONFIG_OF)
0379 static const struct of_device_id mpf_of_ids[] = {
0380     { .compatible = "microchip,mpf-spi-fpga-mgr" },
0381     {},
0382 };
0383 MODULE_DEVICE_TABLE(of, mpf_of_ids);
0384 #endif /* IS_ENABLED(CONFIG_OF) */
0385
0386 static struct spi_driver mpf_driver = {
0387     .probe = mpf_probe,
0388     .id_table = mpf_spi_ids,
0389     .driver = {
0390         .name = "microchip_mpf_spi_fpga_mgr",
0391         .of_match_table = of_match_ptr(mpf_of_ids),
0392     },
0393 };
0394
0395 module_spi_driver(mpf_driver);
0396
0397 MODULE_DESCRIPTION("Microchip Polarfire SPI FPGA Manager");
0398 MODULE_LICENSE("GPL");