drivers/fpga/machxo2-spi.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Lattice MachXO2 Slave SPI Driver
0004  *
0005  * Manage Lattice FPGA firmware that is loaded over SPI using
0006  * the slave serial configuration interface.
0007  *
0008  * Copyright (C) 2018 Paolo Pisati <p.pisati@gmail.com>
0009  */
0010
0011 #include <linux/delay.h>
0012 #include <linux/fpga/fpga-mgr.h>
0013 #include <linux/gpio/consumer.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/spi/spi.h>
0017
0018 /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
0019 #define IDCODE_PUB      {0xe0, 0x00, 0x00, 0x00}
0020 #define ISC_ENABLE      {0xc6, 0x08, 0x00, 0x00}
0021 #define ISC_ERASE       {0x0e, 0x04, 0x00, 0x00}
0022 #define ISC_PROGRAMDONE     {0x5e, 0x00, 0x00, 0x00}
0023 #define LSC_INITADDRESS     {0x46, 0x00, 0x00, 0x00}
0024 #define LSC_PROGINCRNV      {0x70, 0x00, 0x00, 0x01}
0025 #define LSC_READ_STATUS     {0x3c, 0x00, 0x00, 0x00}
0026 #define LSC_REFRESH     {0x79, 0x00, 0x00, 0x00}
0027
0028 /*
0029  * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
0030  * Sheet' sysCONFIG Port Timing Specifications (3-36)
0031  */
0032 #define MACHXO2_MAX_SPEED       66000000
0033
0034 #define MACHXO2_LOW_DELAY_USEC      5
0035 #define MACHXO2_HIGH_DELAY_USEC     200
0036 #define MACHXO2_REFRESH_USEC        4800
0037 #define MACHXO2_MAX_BUSY_LOOP       128
0038 #define MACHXO2_MAX_REFRESH_LOOP    16
0039
0040 #define MACHXO2_PAGE_SIZE       16
0041 #define MACHXO2_BUF_SIZE        (MACHXO2_PAGE_SIZE + 4)
0042
0043 /* Status register bits, errors and error mask */
0044 #define BUSY    12
0045 #define DONE    8
0046 #define DVER    27
0047 #define ENAB    9
0048 #define ERRBITS 23
0049 #define ERRMASK 7
0050 #define FAIL    13
0051
0052 #define ENOERR  0 /* no error */
0053 #define EID 1
0054 #define ECMD    2
0055 #define ECRC    3
0056 #define EPREAM  4 /* preamble error */
0057 #define EABRT   5 /* abort error */
0058 #define EOVERFL 6 /* overflow error */
0059 #define ESDMEOF 7 /* SDM EOF */
0060
0061 static inline u8 get_err(unsigned long *status)
0062 {
0063     return (*status >> ERRBITS) & ERRMASK;
0064 }
0065
0066 static int get_status(struct spi_device *spi, unsigned long *status)
0067 {
0068     struct spi_message msg;
0069     struct spi_transfer rx, tx;
0070     static const u8 cmd[] = LSC_READ_STATUS;
0071     int ret;
0072
0073     memset(&rx, 0, sizeof(rx));
0074     memset(&tx, 0, sizeof(tx));
0075     tx.tx_buf = cmd;
0076     tx.len = sizeof(cmd);
0077     rx.rx_buf = status;
0078     rx.len = 4;
0079     spi_message_init(&msg);
0080     spi_message_add_tail(&tx, &msg);
0081     spi_message_add_tail(&rx, &msg);
0082     ret = spi_sync(spi, &msg);
0083     if (ret)
0084         return ret;
0085
0086     *status = be32_to_cpu(*status);
0087
0088     return 0;
0089 }
0090
0091 #ifdef DEBUG
0092 static const char *get_err_string(u8 err)
0093 {
0094     switch (err) {
0095     case ENOERR:    return "No Error";
0096     case EID:   return "ID ERR";
0097     case ECMD:  return "CMD ERR";
0098     case ECRC:  return "CRC ERR";
0099     case EPREAM:    return "Preamble ERR";
0100     case EABRT: return "Abort ERR";
0101     case EOVERFL:   return "Overflow ERR";
0102     case ESDMEOF:   return "SDM EOF";
0103     }
0104
0105     return "Default switch case";
0106 }
0107 #endif
0108
0109 static void dump_status_reg(unsigned long *status)
0110 {
0111 #ifdef DEBUG
0112     pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
0113          *status, test_bit(DONE, status), test_bit(ENAB, status),
0114          test_bit(BUSY, status), test_bit(FAIL, status),
0115          test_bit(DVER, status), get_err_string(get_err(status)));
0116 #endif
0117 }
0118
0119 static int wait_until_not_busy(struct spi_device *spi)
0120 {
0121     unsigned long status;
0122     int ret, loop = 0;
0123
0124     do {
0125         ret = get_status(spi, &status);
0126         if (ret)
0127             return ret;
0128         if (++loop >= MACHXO2_MAX_BUSY_LOOP)
0129             return -EBUSY;
0130     } while (test_bit(BUSY, &status));
0131
0132     return 0;
0133 }
0134
0135 static int machxo2_cleanup(struct fpga_manager *mgr)
0136 {
0137     struct spi_device *spi = mgr->priv;
0138     struct spi_message msg;
0139     struct spi_transfer tx[2];
0140     static const u8 erase[] = ISC_ERASE;
0141     static const u8 refresh[] = LSC_REFRESH;
0142     int ret;
0143
0144     memset(tx, 0, sizeof(tx));
0145     spi_message_init(&msg);
0146     tx[0].tx_buf = &erase;
0147     tx[0].len = sizeof(erase);
0148     spi_message_add_tail(&tx[0], &msg);
0149     ret = spi_sync(spi, &msg);
0150     if (ret)
0151         goto fail;
0152
0153     ret = wait_until_not_busy(spi);
0154     if (ret)
0155         goto fail;
0156
0157     spi_message_init(&msg);
0158     tx[1].tx_buf = &refresh;
0159     tx[1].len = sizeof(refresh);
0160     tx[1].delay.value = MACHXO2_REFRESH_USEC;
0161     tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
0162     spi_message_add_tail(&tx[1], &msg);
0163     ret = spi_sync(spi, &msg);
0164     if (ret)
0165         goto fail;
0166
0167     return 0;
0168 fail:
0169     dev_err(&mgr->dev, "Cleanup failed\n");
0170
0171     return ret;
0172 }
0173
0174 static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
0175 {
0176     struct spi_device *spi = mgr->priv;
0177     unsigned long status;
0178
0179     get_status(spi, &status);
0180     if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
0181         get_err(&status) == ENOERR)
0182         return FPGA_MGR_STATE_OPERATING;
0183
0184     return FPGA_MGR_STATE_UNKNOWN;
0185 }
0186
0187 static int machxo2_write_init(struct fpga_manager *mgr,
0188                   struct fpga_image_info *info,
0189                   const char *buf, size_t count)
0190 {
0191     struct spi_device *spi = mgr->priv;
0192     struct spi_message msg;
0193     struct spi_transfer tx[3];
0194     static const u8 enable[] = ISC_ENABLE;
0195     static const u8 erase[] = ISC_ERASE;
0196     static const u8 initaddr[] = LSC_INITADDRESS;
0197     unsigned long status;
0198     int ret;
0199
0200     if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
0201         dev_err(&mgr->dev,
0202             "Partial reconfiguration is not supported\n");
0203         return -ENOTSUPP;
0204     }
0205
0206     get_status(spi, &status);
0207     dump_status_reg(&status);
0208     memset(tx, 0, sizeof(tx));
0209     spi_message_init(&msg);
0210     tx[0].tx_buf = &enable;
0211     tx[0].len = sizeof(enable);
0212     tx[0].delay.value = MACHXO2_LOW_DELAY_USEC;
0213     tx[0].delay.unit = SPI_DELAY_UNIT_USECS;
0214     spi_message_add_tail(&tx[0], &msg);
0215
0216     tx[1].tx_buf = &erase;
0217     tx[1].len = sizeof(erase);
0218     spi_message_add_tail(&tx[1], &msg);
0219     ret = spi_sync(spi, &msg);
0220     if (ret)
0221         goto fail;
0222
0223     ret = wait_until_not_busy(spi);
0224     if (ret)
0225         goto fail;
0226
0227     get_status(spi, &status);
0228     if (test_bit(FAIL, &status)) {
0229         ret = -EINVAL;
0230         goto fail;
0231     }
0232     dump_status_reg(&status);
0233
0234     spi_message_init(&msg);
0235     tx[2].tx_buf = &initaddr;
0236     tx[2].len = sizeof(initaddr);
0237     spi_message_add_tail(&tx[2], &msg);
0238     ret = spi_sync(spi, &msg);
0239     if (ret)
0240         goto fail;
0241
0242     get_status(spi, &status);
0243     dump_status_reg(&status);
0244
0245     return 0;
0246 fail:
0247     dev_err(&mgr->dev, "Error during FPGA init.\n");
0248
0249     return ret;
0250 }
0251
0252 static int machxo2_write(struct fpga_manager *mgr, const char *buf,
0253              size_t count)
0254 {
0255     struct spi_device *spi = mgr->priv;
0256     struct spi_message msg;
0257     struct spi_transfer tx;
0258     static const u8 progincr[] = LSC_PROGINCRNV;
0259     u8 payload[MACHXO2_BUF_SIZE];
0260     unsigned long status;
0261     int i, ret;
0262
0263     if (count % MACHXO2_PAGE_SIZE != 0) {
0264         dev_err(&mgr->dev, "Malformed payload.\n");
0265         return -EINVAL;
0266     }
0267     get_status(spi, &status);
0268     dump_status_reg(&status);
0269     memcpy(payload, &progincr, sizeof(progincr));
0270     for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
0271         memcpy(&payload[sizeof(progincr)], &buf[i], MACHXO2_PAGE_SIZE);
0272         memset(&tx, 0, sizeof(tx));
0273         spi_message_init(&msg);
0274         tx.tx_buf = payload;
0275         tx.len = MACHXO2_BUF_SIZE;
0276         tx.delay.value = MACHXO2_HIGH_DELAY_USEC;
0277         tx.delay.unit = SPI_DELAY_UNIT_USECS;
0278         spi_message_add_tail(&tx, &msg);
0279         ret = spi_sync(spi, &msg);
0280         if (ret) {
0281             dev_err(&mgr->dev, "Error loading the bitstream.\n");
0282             return ret;
0283         }
0284     }
0285     get_status(spi, &status);
0286     dump_status_reg(&status);
0287
0288     return 0;
0289 }
0290
0291 static int machxo2_write_complete(struct fpga_manager *mgr,
0292                   struct fpga_image_info *info)
0293 {
0294     struct spi_device *spi = mgr->priv;
0295     struct spi_message msg;
0296     struct spi_transfer tx[2];
0297     static const u8 progdone[] = ISC_PROGRAMDONE;
0298     static const u8 refresh[] = LSC_REFRESH;
0299     unsigned long status;
0300     int ret, refreshloop = 0;
0301
0302     memset(tx, 0, sizeof(tx));
0303     spi_message_init(&msg);
0304     tx[0].tx_buf = &progdone;
0305     tx[0].len = sizeof(progdone);
0306     spi_message_add_tail(&tx[0], &msg);
0307     ret = spi_sync(spi, &msg);
0308     if (ret)
0309         goto fail;
0310     ret = wait_until_not_busy(spi);
0311     if (ret)
0312         goto fail;
0313
0314     get_status(spi, &status);
0315     dump_status_reg(&status);
0316     if (!test_bit(DONE, &status)) {
0317         machxo2_cleanup(mgr);
0318         ret = -EINVAL;
0319         goto fail;
0320     }
0321
0322     do {
0323         spi_message_init(&msg);
0324         tx[1].tx_buf = &refresh;
0325         tx[1].len = sizeof(refresh);
0326         tx[1].delay.value = MACHXO2_REFRESH_USEC;
0327         tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
0328         spi_message_add_tail(&tx[1], &msg);
0329         ret = spi_sync(spi, &msg);
0330         if (ret)
0331             goto fail;
0332
0333         /* check refresh status */
0334         get_status(spi, &status);
0335         dump_status_reg(&status);
0336         if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
0337             get_err(&status) == ENOERR)
0338             break;
0339         if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
0340             machxo2_cleanup(mgr);
0341             ret = -EINVAL;
0342             goto fail;
0343         }
0344     } while (1);
0345
0346     get_status(spi, &status);
0347     dump_status_reg(&status);
0348
0349     return 0;
0350 fail:
0351     dev_err(&mgr->dev, "Refresh failed.\n");
0352
0353     return ret;
0354 }
0355
0356 static const struct fpga_manager_ops machxo2_ops = {
0357     .state = machxo2_spi_state,
0358     .write_init = machxo2_write_init,
0359     .write = machxo2_write,
0360     .write_complete = machxo2_write_complete,
0361 };
0362
0363 static int machxo2_spi_probe(struct spi_device *spi)
0364 {
0365     struct device *dev = &spi->dev;
0366     struct fpga_manager *mgr;
0367
0368     if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
0369         dev_err(dev, "Speed is too high\n");
0370         return -EINVAL;
0371     }
0372
0373     mgr = devm_fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
0374                      &machxo2_ops, spi);
0375     return PTR_ERR_OR_ZERO(mgr);
0376 }
0377
0378 #ifdef CONFIG_OF
0379 static const struct of_device_id of_match[] = {
0380     { .compatible = "lattice,machxo2-slave-spi", },
0381     {}
0382 };
0383 MODULE_DEVICE_TABLE(of, of_match);
0384 #endif
0385
0386 static const struct spi_device_id lattice_ids[] = {
0387     { "machxo2-slave-spi", 0 },
0388     { },
0389 };
0390 MODULE_DEVICE_TABLE(spi, lattice_ids);
0391
0392 static struct spi_driver machxo2_spi_driver = {
0393     .driver = {
0394         .name = "machxo2-slave-spi",
0395         .of_match_table = of_match_ptr(of_match),
0396     },
0397     .probe = machxo2_spi_probe,
0398     .id_table = lattice_ids,
0399 };
0400
0401 module_spi_driver(machxo2_spi_driver)
0402
0403 MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>");
0404 MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
0405 MODULE_LICENSE("GPL v2");