drivers/fpga/ice40-spi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * FPGA Manager Driver for Lattice iCE40.
0004  *
0005  *  Copyright (c) 2016 Joel Holdsworth
0006  *
0007  * This driver adds support to the FPGA manager for configuring the SRAM of
0008  * Lattice iCE40 FPGAs through slave SPI.
0009  */
0010
0011 #include <linux/fpga/fpga-mgr.h>
0012 #include <linux/gpio/consumer.h>
0013 #include <linux/module.h>
0014 #include <linux/of_gpio.h>
0015 #include <linux/spi/spi.h>
0016 #include <linux/stringify.h>
0017
0018 #define ICE40_SPI_MAX_SPEED 25000000 /* Hz */
0019 #define ICE40_SPI_MIN_SPEED 1000000 /* Hz */
0020
0021 #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
0022 #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
0023
0024 #define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
0025
0026 struct ice40_fpga_priv {
0027     struct spi_device *dev;
0028     struct gpio_desc *reset;
0029     struct gpio_desc *cdone;
0030 };
0031
0032 static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
0033 {
0034     struct ice40_fpga_priv *priv = mgr->priv;
0035
0036     return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
0037         FPGA_MGR_STATE_UNKNOWN;
0038 }
0039
0040 static int ice40_fpga_ops_write_init(struct fpga_manager *mgr,
0041                      struct fpga_image_info *info,
0042                      const char *buf, size_t count)
0043 {
0044     struct ice40_fpga_priv *priv = mgr->priv;
0045     struct spi_device *dev = priv->dev;
0046     struct spi_message message;
0047     struct spi_transfer assert_cs_then_reset_delay = {
0048         .cs_change   = 1,
0049         .delay = {
0050             .value = ICE40_SPI_RESET_DELAY,
0051             .unit = SPI_DELAY_UNIT_USECS
0052         }
0053     };
0054     struct spi_transfer housekeeping_delay_then_release_cs = {
0055         .delay = {
0056             .value = ICE40_SPI_HOUSEKEEPING_DELAY,
0057             .unit = SPI_DELAY_UNIT_USECS
0058         }
0059     };
0060     int ret;
0061
0062     if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
0063         dev_err(&dev->dev,
0064             "Partial reconfiguration is not supported\n");
0065         return -ENOTSUPP;
0066     }
0067
0068     /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
0069     spi_bus_lock(dev->master);
0070
0071     gpiod_set_value(priv->reset, 1);
0072
0073     spi_message_init(&message);
0074     spi_message_add_tail(&assert_cs_then_reset_delay, &message);
0075     ret = spi_sync_locked(dev, &message);
0076
0077     /* Come out of reset */
0078     gpiod_set_value(priv->reset, 0);
0079
0080     /* Abort if the chip-select failed */
0081     if (ret)
0082         goto fail;
0083
0084     /* Check CDONE is de-asserted i.e. the FPGA is reset */
0085     if (gpiod_get_value(priv->cdone)) {
0086         dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
0087         ret = -EIO;
0088         goto fail;
0089     }
0090
0091     /* Wait for the housekeeping to complete, and release SS_B */
0092     spi_message_init(&message);
0093     spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
0094     ret = spi_sync_locked(dev, &message);
0095
0096 fail:
0097     spi_bus_unlock(dev->master);
0098
0099     return ret;
0100 }
0101
0102 static int ice40_fpga_ops_write(struct fpga_manager *mgr,
0103                 const char *buf, size_t count)
0104 {
0105     struct ice40_fpga_priv *priv = mgr->priv;
0106
0107     return spi_write(priv->dev, buf, count);
0108 }
0109
0110 static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr,
0111                      struct fpga_image_info *info)
0112 {
0113     struct ice40_fpga_priv *priv = mgr->priv;
0114     struct spi_device *dev = priv->dev;
0115     const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0};
0116
0117     /* Check CDONE is asserted */
0118     if (!gpiod_get_value(priv->cdone)) {
0119         dev_err(&dev->dev,
0120             "CDONE was not asserted after firmware transfer\n");
0121         return -EIO;
0122     }
0123
0124     /* Send of zero-padding to activate the firmware */
0125     return spi_write(dev, padding, sizeof(padding));
0126 }
0127
0128 static const struct fpga_manager_ops ice40_fpga_ops = {
0129     .state = ice40_fpga_ops_state,
0130     .write_init = ice40_fpga_ops_write_init,
0131     .write = ice40_fpga_ops_write,
0132     .write_complete = ice40_fpga_ops_write_complete,
0133 };
0134
0135 static int ice40_fpga_probe(struct spi_device *spi)
0136 {
0137     struct device *dev = &spi->dev;
0138     struct ice40_fpga_priv *priv;
0139     struct fpga_manager *mgr;
0140     int ret;
0141
0142     priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
0143     if (!priv)
0144         return -ENOMEM;
0145
0146     priv->dev = spi;
0147
0148     /* Check board setup data. */
0149     if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {
0150         dev_err(dev, "SPI speed is too high, maximum speed is "
0151             __stringify(ICE40_SPI_MAX_SPEED) "\n");
0152         return -EINVAL;
0153     }
0154
0155     if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {
0156         dev_err(dev, "SPI speed is too low, minimum speed is "
0157             __stringify(ICE40_SPI_MIN_SPEED) "\n");
0158         return -EINVAL;
0159     }
0160
0161     if (spi->mode & SPI_CPHA) {
0162         dev_err(dev, "Bad SPI mode, CPHA not supported\n");
0163         return -EINVAL;
0164     }
0165
0166     /* Set up the GPIOs */
0167     priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
0168     if (IS_ERR(priv->cdone)) {
0169         ret = PTR_ERR(priv->cdone);
0170         dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret);
0171         return ret;
0172     }
0173
0174     priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
0175     if (IS_ERR(priv->reset)) {
0176         ret = PTR_ERR(priv->reset);
0177         dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret);
0178         return ret;
0179     }
0180
0181     mgr = devm_fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager",
0182                      &ice40_fpga_ops, priv);
0183     return PTR_ERR_OR_ZERO(mgr);
0184 }
0185
0186 static const struct of_device_id ice40_fpga_of_match[] = {
0187     { .compatible = "lattice,ice40-fpga-mgr", },
0188     {},
0189 };
0190 MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
0191
0192 static const struct spi_device_id ice40_fpga_spi_ids[] = {
0193     { .name = "ice40-fpga-mgr", },
0194     {},
0195 };
0196 MODULE_DEVICE_TABLE(spi, ice40_fpga_spi_ids);
0197
0198 static struct spi_driver ice40_fpga_driver = {
0199     .probe = ice40_fpga_probe,
0200     .driver = {
0201         .name = "ice40spi",
0202         .of_match_table = of_match_ptr(ice40_fpga_of_match),
0203     },
0204     .id_table = ice40_fpga_spi_ids,
0205 };
0206
0207 module_spi_driver(ice40_fpga_driver);
0208
0209 MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>");
0210 MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
0211 MODULE_LICENSE("GPL v2");