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0001 /* SPDX-License-Identifier: GPL-2.0 */ 0002 /* 0003 * Header file for FPGA Management Engine (FME) Driver 0004 * 0005 * Copyright (C) 2017-2018 Intel Corporation, Inc. 0006 * 0007 * Authors: 0008 * Kang Luwei <luwei.kang@intel.com> 0009 * Xiao Guangrong <guangrong.xiao@linux.intel.com> 0010 * Wu Hao <hao.wu@intel.com> 0011 * Joseph Grecco <joe.grecco@intel.com> 0012 * Enno Luebbers <enno.luebbers@intel.com> 0013 * Tim Whisonant <tim.whisonant@intel.com> 0014 * Ananda Ravuri <ananda.ravuri@intel.com> 0015 * Henry Mitchel <henry.mitchel@intel.com> 0016 */ 0017 0018 #ifndef __DFL_FME_H 0019 #define __DFL_FME_H 0020 0021 /** 0022 * struct dfl_fme - dfl fme private data 0023 * 0024 * @mgr: FME's FPGA manager platform device. 0025 * @region_list: linked list of FME's FPGA regions. 0026 * @bridge_list: linked list of FME's FPGA bridges. 0027 * @pdata: fme platform device's pdata. 0028 */ 0029 struct dfl_fme { 0030 struct platform_device *mgr; 0031 struct list_head region_list; 0032 struct list_head bridge_list; 0033 struct dfl_feature_platform_data *pdata; 0034 }; 0035 0036 extern const struct dfl_feature_ops fme_pr_mgmt_ops; 0037 extern const struct dfl_feature_id fme_pr_mgmt_id_table[]; 0038 extern const struct dfl_feature_ops fme_global_err_ops; 0039 extern const struct dfl_feature_id fme_global_err_id_table[]; 0040 extern const struct attribute_group fme_global_err_group; 0041 extern const struct dfl_feature_ops fme_perf_ops; 0042 extern const struct dfl_feature_id fme_perf_id_table[]; 0043 0044 #endif /* __DFL_FME_H */
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