drivers/fpga/dfl-fme-pr.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
0004  *
0005  * Copyright (C) 2017-2018 Intel Corporation, Inc.
0006  *
0007  * Authors:
0008  *   Kang Luwei <luwei.kang@intel.com>
0009  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
0010  *   Wu Hao <hao.wu@intel.com>
0011  *   Joseph Grecco <joe.grecco@intel.com>
0012  *   Enno Luebbers <enno.luebbers@intel.com>
0013  *   Tim Whisonant <tim.whisonant@intel.com>
0014  *   Ananda Ravuri <ananda.ravuri@intel.com>
0015  *   Henry Mitchel <henry.mitchel@intel.com>
0016  */
0017
0018 #ifndef __DFL_FME_PR_H
0019 #define __DFL_FME_PR_H
0020
0021 #include <linux/platform_device.h>
0022
0023 /**
0024  * struct dfl_fme_region - FME fpga region data structure
0025  *
0026  * @region: platform device of the FPGA region.
0027  * @node: used to link fme_region to a list.
0028  * @port_id: indicate which port this region connected to.
0029  */
0030 struct dfl_fme_region {
0031     struct platform_device *region;
0032     struct list_head node;
0033     int port_id;
0034 };
0035
0036 /**
0037  * struct dfl_fme_region_pdata - platform data for FME region platform device.
0038  *
0039  * @mgr: platform device of the FPGA manager.
0040  * @br: platform device of the FPGA bridge.
0041  * @region_id: region id (same as port_id).
0042  */
0043 struct dfl_fme_region_pdata {
0044     struct platform_device *mgr;
0045     struct platform_device *br;
0046     int region_id;
0047 };
0048
0049 /**
0050  * struct dfl_fme_bridge - FME fpga bridge data structure
0051  *
0052  * @br: platform device of the FPGA bridge.
0053  * @node: used to link fme_bridge to a list.
0054  */
0055 struct dfl_fme_bridge {
0056     struct platform_device *br;
0057     struct list_head node;
0058 };
0059
0060 /**
0061  * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device.
0062  *
0063  * @cdev: container device.
0064  * @port_id: port id.
0065  */
0066 struct dfl_fme_br_pdata {
0067     struct dfl_fpga_cdev *cdev;
0068     int port_id;
0069 };
0070
0071 /**
0072  * struct dfl_fme_mgr_pdata - platform data for FME manager platform device.
0073  *
0074  * @ioaddr: mapped io address for FME manager platform device.
0075  */
0076 struct dfl_fme_mgr_pdata {
0077     void __iomem *ioaddr;
0078 };
0079
0080 #define DFL_FPGA_FME_MGR    "dfl-fme-mgr"
0081 #define DFL_FPGA_FME_BRIDGE "dfl-fme-bridge"
0082 #define DFL_FPGA_FME_REGION "dfl-fme-region"
0083
0084 #endif /* __DFL_FME_PR_H */