drivers/fpga/dfl-fme-mgr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FPGA Manager Driver for FPGA Management Engine (FME)
0004  *
0005  * Copyright (C) 2017-2018 Intel Corporation, Inc.
0006  *
0007  * Authors:
0008  *   Kang Luwei <luwei.kang@intel.com>
0009  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
0010  *   Wu Hao <hao.wu@intel.com>
0011  *   Joseph Grecco <joe.grecco@intel.com>
0012  *   Enno Luebbers <enno.luebbers@intel.com>
0013  *   Tim Whisonant <tim.whisonant@intel.com>
0014  *   Ananda Ravuri <ananda.ravuri@intel.com>
0015  *   Christopher Rauer <christopher.rauer@intel.com>
0016  *   Henry Mitchel <henry.mitchel@intel.com>
0017  */
0018
0019 #include <linux/bitfield.h>
0020 #include <linux/module.h>
0021 #include <linux/iopoll.h>
0022 #include <linux/io-64-nonatomic-lo-hi.h>
0023 #include <linux/fpga/fpga-mgr.h>
0024
0025 #include "dfl-fme-pr.h"
0026
0027 /* FME Partial Reconfiguration Sub Feature Register Set */
0028 #define FME_PR_DFH      0x0
0029 #define FME_PR_CTRL     0x8
0030 #define FME_PR_STS      0x10
0031 #define FME_PR_DATA     0x18
0032 #define FME_PR_ERR      0x20
0033 #define FME_PR_INTFC_ID_L   0xA8
0034 #define FME_PR_INTFC_ID_H   0xB0
0035
0036 /* FME PR Control Register Bitfield */
0037 #define FME_PR_CTRL_PR_RST  BIT_ULL(0)  /* Reset PR engine */
0038 #define FME_PR_CTRL_PR_RSTACK   BIT_ULL(4)  /* Ack for PR engine reset */
0039 #define FME_PR_CTRL_PR_RGN_ID   GENMASK_ULL(9, 7)       /* PR Region ID */
0040 #define FME_PR_CTRL_PR_START    BIT_ULL(12) /* Start to request PR service */
0041 #define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
0042
0043 /* FME PR Status Register Bitfield */
0044 /* Number of available entries in HW queue inside the PR engine. */
0045 #define FME_PR_STS_PR_CREDIT    GENMASK_ULL(8, 0)
0046 #define FME_PR_STS_PR_STS   BIT_ULL(16) /* PR operation status */
0047 #define FME_PR_STS_PR_STS_IDLE  0
0048 #define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20)     /* Controller status */
0049 #define FME_PR_STS_PR_HOST_STS  GENMASK_ULL(27, 24)     /* PR host status */
0050
0051 /* FME PR Data Register Bitfield */
0052 /* PR data from the raw-binary file. */
0053 #define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)
0054
0055 /* FME PR Error Register */
0056 /* PR Operation errors detected. */
0057 #define FME_PR_ERR_OPERATION_ERR    BIT_ULL(0)
0058 /* CRC error detected. */
0059 #define FME_PR_ERR_CRC_ERR      BIT_ULL(1)
0060 /* Incompatible PR bitstream detected. */
0061 #define FME_PR_ERR_INCOMPATIBLE_BS  BIT_ULL(2)
0062 /* PR data push protocol violated. */
0063 #define FME_PR_ERR_PROTOCOL_ERR     BIT_ULL(3)
0064 /* PR data fifo overflow error detected */
0065 #define FME_PR_ERR_FIFO_OVERFLOW    BIT_ULL(4)
0066
0067 #define PR_WAIT_TIMEOUT   8000000
0068 #define PR_HOST_STATUS_IDLE 0
0069
0070 struct fme_mgr_priv {
0071     void __iomem *ioaddr;
0072     u64 pr_error;
0073 };
0074
0075 static u64 pr_error_to_mgr_status(u64 err)
0076 {
0077     u64 status = 0;
0078
0079     if (err & FME_PR_ERR_OPERATION_ERR)
0080         status |= FPGA_MGR_STATUS_OPERATION_ERR;
0081     if (err & FME_PR_ERR_CRC_ERR)
0082         status |= FPGA_MGR_STATUS_CRC_ERR;
0083     if (err & FME_PR_ERR_INCOMPATIBLE_BS)
0084         status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
0085     if (err & FME_PR_ERR_PROTOCOL_ERR)
0086         status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
0087     if (err & FME_PR_ERR_FIFO_OVERFLOW)
0088         status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
0089
0090     return status;
0091 }
0092
0093 static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
0094 {
0095     u64 pr_status, pr_error;
0096
0097     pr_status = readq(fme_pr + FME_PR_STS);
0098     if (!(pr_status & FME_PR_STS_PR_STS))
0099         return 0;
0100
0101     pr_error = readq(fme_pr + FME_PR_ERR);
0102     writeq(pr_error, fme_pr + FME_PR_ERR);
0103
0104     return pr_error;
0105 }
0106
0107 static int fme_mgr_write_init(struct fpga_manager *mgr,
0108                   struct fpga_image_info *info,
0109                   const char *buf, size_t count)
0110 {
0111     struct device *dev = &mgr->dev;
0112     struct fme_mgr_priv *priv = mgr->priv;
0113     void __iomem *fme_pr = priv->ioaddr;
0114     u64 pr_ctrl, pr_status;
0115
0116     if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
0117         dev_err(dev, "only supports partial reconfiguration.\n");
0118         return -EINVAL;
0119     }
0120
0121     dev_dbg(dev, "resetting PR before initiated PR\n");
0122
0123     pr_ctrl = readq(fme_pr + FME_PR_CTRL);
0124     pr_ctrl |= FME_PR_CTRL_PR_RST;
0125     writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
0126
0127     if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
0128                    pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
0129                    PR_WAIT_TIMEOUT)) {
0130         dev_err(dev, "PR Reset ACK timeout\n");
0131         return -ETIMEDOUT;
0132     }
0133
0134     pr_ctrl = readq(fme_pr + FME_PR_CTRL);
0135     pr_ctrl &= ~FME_PR_CTRL_PR_RST;
0136     writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
0137
0138     dev_dbg(dev,
0139         "waiting for PR resource in HW to be initialized and ready\n");
0140
0141     if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
0142                    (pr_status & FME_PR_STS_PR_STS) ==
0143                    FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
0144         dev_err(dev, "PR Status timeout\n");
0145         priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
0146         return -ETIMEDOUT;
0147     }
0148
0149     dev_dbg(dev, "check and clear previous PR error\n");
0150     priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
0151     if (priv->pr_error)
0152         dev_dbg(dev, "previous PR error detected %llx\n",
0153             (unsigned long long)priv->pr_error);
0154
0155     dev_dbg(dev, "set PR port ID\n");
0156
0157     pr_ctrl = readq(fme_pr + FME_PR_CTRL);
0158     pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
0159     pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
0160     writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
0161
0162     return 0;
0163 }
0164
0165 static int fme_mgr_write(struct fpga_manager *mgr,
0166              const char *buf, size_t count)
0167 {
0168     struct device *dev = &mgr->dev;
0169     struct fme_mgr_priv *priv = mgr->priv;
0170     void __iomem *fme_pr = priv->ioaddr;
0171     u64 pr_ctrl, pr_status, pr_data;
0172     int delay = 0, pr_credit, i = 0;
0173
0174     dev_dbg(dev, "start request\n");
0175
0176     pr_ctrl = readq(fme_pr + FME_PR_CTRL);
0177     pr_ctrl |= FME_PR_CTRL_PR_START;
0178     writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
0179
0180     dev_dbg(dev, "pushing data from bitstream to HW\n");
0181
0182     /*
0183      * driver can push data to PR hardware using PR_DATA register once HW
0184      * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
0185      * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
0186      * to wait for enough pr_credit from hardware by polling.
0187      */
0188     pr_status = readq(fme_pr + FME_PR_STS);
0189     pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
0190
0191     while (count > 0) {
0192         while (pr_credit <= 1) {
0193             if (delay++ > PR_WAIT_TIMEOUT) {
0194                 dev_err(dev, "PR_CREDIT timeout\n");
0195                 return -ETIMEDOUT;
0196             }
0197             udelay(1);
0198
0199             pr_status = readq(fme_pr + FME_PR_STS);
0200             pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
0201         }
0202
0203         if (count < 4) {
0204             dev_err(dev, "Invalid PR bitstream size\n");
0205             return -EINVAL;
0206         }
0207
0208         pr_data = 0;
0209         pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
0210                       *(((u32 *)buf) + i));
0211         writeq(pr_data, fme_pr + FME_PR_DATA);
0212         count -= 4;
0213         pr_credit--;
0214         i++;
0215     }
0216
0217     return 0;
0218 }
0219
0220 static int fme_mgr_write_complete(struct fpga_manager *mgr,
0221                   struct fpga_image_info *info)
0222 {
0223     struct device *dev = &mgr->dev;
0224     struct fme_mgr_priv *priv = mgr->priv;
0225     void __iomem *fme_pr = priv->ioaddr;
0226     u64 pr_ctrl;
0227
0228     pr_ctrl = readq(fme_pr + FME_PR_CTRL);
0229     pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
0230     writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
0231
0232     dev_dbg(dev, "green bitstream push complete\n");
0233     dev_dbg(dev, "waiting for HW to release PR resource\n");
0234
0235     if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
0236                    !(pr_ctrl & FME_PR_CTRL_PR_START), 1,
0237                    PR_WAIT_TIMEOUT)) {
0238         dev_err(dev, "PR Completion ACK timeout.\n");
0239         return -ETIMEDOUT;
0240     }
0241
0242     dev_dbg(dev, "PR operation complete, checking status\n");
0243     priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
0244     if (priv->pr_error) {
0245         dev_dbg(dev, "PR error detected %llx\n",
0246             (unsigned long long)priv->pr_error);
0247         return -EIO;
0248     }
0249
0250     dev_dbg(dev, "PR done successfully\n");
0251
0252     return 0;
0253 }
0254
0255 static u64 fme_mgr_status(struct fpga_manager *mgr)
0256 {
0257     struct fme_mgr_priv *priv = mgr->priv;
0258
0259     return pr_error_to_mgr_status(priv->pr_error);
0260 }
0261
0262 static const struct fpga_manager_ops fme_mgr_ops = {
0263     .write_init = fme_mgr_write_init,
0264     .write = fme_mgr_write,
0265     .write_complete = fme_mgr_write_complete,
0266     .status = fme_mgr_status,
0267 };
0268
0269 static void fme_mgr_get_compat_id(void __iomem *fme_pr,
0270                   struct fpga_compat_id *id)
0271 {
0272     id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
0273     id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
0274 }
0275
0276 static int fme_mgr_probe(struct platform_device *pdev)
0277 {
0278     struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
0279     struct fpga_manager_info info = { 0 };
0280     struct device *dev = &pdev->dev;
0281     struct fme_mgr_priv *priv;
0282     struct fpga_manager *mgr;
0283     struct resource *res;
0284
0285     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0286     if (!priv)
0287         return -ENOMEM;
0288
0289     if (pdata->ioaddr)
0290         priv->ioaddr = pdata->ioaddr;
0291
0292     if (!priv->ioaddr) {
0293         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0294         priv->ioaddr = devm_ioremap_resource(dev, res);
0295         if (IS_ERR(priv->ioaddr))
0296             return PTR_ERR(priv->ioaddr);
0297     }
0298
0299     info.name = "DFL FME FPGA Manager";
0300     info.mops = &fme_mgr_ops;
0301     info.priv = priv;
0302     info.compat_id = devm_kzalloc(dev, sizeof(*info.compat_id), GFP_KERNEL);
0303     if (!info.compat_id)
0304         return -ENOMEM;
0305
0306     fme_mgr_get_compat_id(priv->ioaddr, info.compat_id);
0307     mgr = devm_fpga_mgr_register_full(dev, &info);
0308     return PTR_ERR_OR_ZERO(mgr);
0309 }
0310
0311 static struct platform_driver fme_mgr_driver = {
0312     .driver = {
0313         .name    = DFL_FPGA_FME_MGR,
0314     },
0315     .probe   = fme_mgr_probe,
0316 };
0317
0318 module_platform_driver(fme_mgr_driver);
0319
0320 MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
0321 MODULE_AUTHOR("Intel Corporation");
0322 MODULE_LICENSE("GPL v2");
0323 MODULE_ALIAS("platform:dfl-fme-mgr");