drivers/fpga/dfl-fme-br.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FPGA Bridge Driver for FPGA Management Engine (FME)
0004  *
0005  * Copyright (C) 2017-2018 Intel Corporation, Inc.
0006  *
0007  * Authors:
0008  *   Wu Hao <hao.wu@intel.com>
0009  *   Joseph Grecco <joe.grecco@intel.com>
0010  *   Enno Luebbers <enno.luebbers@intel.com>
0011  *   Tim Whisonant <tim.whisonant@intel.com>
0012  *   Ananda Ravuri <ananda.ravuri@intel.com>
0013  *   Henry Mitchel <henry.mitchel@intel.com>
0014  */
0015
0016 #include <linux/module.h>
0017 #include <linux/fpga/fpga-bridge.h>
0018
0019 #include "dfl.h"
0020 #include "dfl-fme-pr.h"
0021
0022 struct fme_br_priv {
0023     struct dfl_fme_br_pdata *pdata;
0024     struct dfl_fpga_port_ops *port_ops;
0025     struct platform_device *port_pdev;
0026 };
0027
0028 static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable)
0029 {
0030     struct fme_br_priv *priv = bridge->priv;
0031     struct platform_device *port_pdev;
0032     struct dfl_fpga_port_ops *ops;
0033
0034     if (!priv->port_pdev) {
0035         port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev,
0036                             &priv->pdata->port_id,
0037                             dfl_fpga_check_port_id);
0038         if (!port_pdev)
0039             return -ENODEV;
0040
0041         priv->port_pdev = port_pdev;
0042     }
0043
0044     if (priv->port_pdev && !priv->port_ops) {
0045         ops = dfl_fpga_port_ops_get(priv->port_pdev);
0046         if (!ops || !ops->enable_set)
0047             return -ENOENT;
0048
0049         priv->port_ops = ops;
0050     }
0051
0052     return priv->port_ops->enable_set(priv->port_pdev, enable);
0053 }
0054
0055 static const struct fpga_bridge_ops fme_bridge_ops = {
0056     .enable_set = fme_bridge_enable_set,
0057 };
0058
0059 static int fme_br_probe(struct platform_device *pdev)
0060 {
0061     struct device *dev = &pdev->dev;
0062     struct fme_br_priv *priv;
0063     struct fpga_bridge *br;
0064
0065     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0066     if (!priv)
0067         return -ENOMEM;
0068
0069     priv->pdata = dev_get_platdata(dev);
0070
0071     br = fpga_bridge_register(dev, "DFL FPGA FME Bridge",
0072                   &fme_bridge_ops, priv);
0073     if (IS_ERR(br))
0074         return PTR_ERR(br);
0075
0076     platform_set_drvdata(pdev, br);
0077
0078     return 0;
0079 }
0080
0081 static int fme_br_remove(struct platform_device *pdev)
0082 {
0083     struct fpga_bridge *br = platform_get_drvdata(pdev);
0084     struct fme_br_priv *priv = br->priv;
0085
0086     fpga_bridge_unregister(br);
0087
0088     if (priv->port_pdev)
0089         put_device(&priv->port_pdev->dev);
0090     if (priv->port_ops)
0091         dfl_fpga_port_ops_put(priv->port_ops);
0092
0093     return 0;
0094 }
0095
0096 static struct platform_driver fme_br_driver = {
0097     .driver = {
0098         .name    = DFL_FPGA_FME_BRIDGE,
0099     },
0100     .probe   = fme_br_probe,
0101     .remove  = fme_br_remove,
0102 };
0103
0104 module_platform_driver(fme_br_driver);
0105
0106 MODULE_DESCRIPTION("FPGA Bridge for DFL FPGA Management Engine");
0107 MODULE_AUTHOR("Intel Corporation");
0108 MODULE_LICENSE("GPL v2");
0109 MODULE_ALIAS("platform:dfl-fme-bridge");