drivers/fpga/altera-freeze-bridge.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * FPGA Freeze Bridge Controller
0004  *
0005  *  Copyright (C) 2016 Altera Corporation. All rights reserved.
0006  */
0007 #include <linux/delay.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/of_device.h>
0011 #include <linux/module.h>
0012 #include <linux/fpga/fpga-bridge.h>
0013
0014 #define FREEZE_CSR_STATUS_OFFSET        0
0015 #define FREEZE_CSR_CTRL_OFFSET          4
0016 #define FREEZE_CSR_ILLEGAL_REQ_OFFSET       8
0017 #define FREEZE_CSR_REG_VERSION          12
0018
0019 #define FREEZE_CSR_SUPPORTED_VERSION        2
0020 #define FREEZE_CSR_OFFICIAL_VERSION     0xad000003
0021
0022 #define FREEZE_CSR_STATUS_FREEZE_REQ_DONE   BIT(0)
0023 #define FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE BIT(1)
0024
0025 #define FREEZE_CSR_CTRL_FREEZE_REQ      BIT(0)
0026 #define FREEZE_CSR_CTRL_RESET_REQ       BIT(1)
0027 #define FREEZE_CSR_CTRL_UNFREEZE_REQ        BIT(2)
0028
0029 #define FREEZE_BRIDGE_NAME          "freeze"
0030
0031 struct altera_freeze_br_data {
0032     struct device *dev;
0033     void __iomem *base_addr;
0034     bool enable;
0035 };
0036
0037 /*
0038  * Poll status until status bit is set or we have a timeout.
0039  */
0040 static int altera_freeze_br_req_ack(struct altera_freeze_br_data *priv,
0041                     u32 timeout, u32 req_ack)
0042 {
0043     struct device *dev = priv->dev;
0044     void __iomem *csr_illegal_req_addr = priv->base_addr +
0045                          FREEZE_CSR_ILLEGAL_REQ_OFFSET;
0046     u32 status, illegal, ctrl;
0047     int ret = -ETIMEDOUT;
0048
0049     do {
0050         illegal = readl(csr_illegal_req_addr);
0051         if (illegal) {
0052             dev_err(dev, "illegal request detected 0x%x", illegal);
0053
0054             writel(1, csr_illegal_req_addr);
0055
0056             illegal = readl(csr_illegal_req_addr);
0057             if (illegal)
0058                 dev_err(dev, "illegal request not cleared 0x%x",
0059                     illegal);
0060
0061             ret = -EINVAL;
0062             break;
0063         }
0064
0065         status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
0066         dev_dbg(dev, "%s %x %x\n", __func__, status, req_ack);
0067         status &= req_ack;
0068         if (status) {
0069             ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET);
0070             dev_dbg(dev, "%s request %x acknowledged %x %x\n",
0071                 __func__, req_ack, status, ctrl);
0072             ret = 0;
0073             break;
0074         }
0075
0076         udelay(1);
0077     } while (timeout--);
0078
0079     if (ret == -ETIMEDOUT)
0080         dev_err(dev, "%s timeout waiting for 0x%x\n",
0081             __func__, req_ack);
0082
0083     return ret;
0084 }
0085
0086 static int altera_freeze_br_do_freeze(struct altera_freeze_br_data *priv,
0087                       u32 timeout)
0088 {
0089     struct device *dev = priv->dev;
0090     void __iomem *csr_ctrl_addr = priv->base_addr +
0091                       FREEZE_CSR_CTRL_OFFSET;
0092     u32 status;
0093     int ret;
0094
0095     status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
0096
0097     dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
0098
0099     if (status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE) {
0100         dev_dbg(dev, "%s bridge already disabled %d\n",
0101             __func__, status);
0102         return 0;
0103     } else if (!(status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)) {
0104         dev_err(dev, "%s bridge not enabled %d\n", __func__, status);
0105         return -EINVAL;
0106     }
0107
0108     writel(FREEZE_CSR_CTRL_FREEZE_REQ, csr_ctrl_addr);
0109
0110     ret = altera_freeze_br_req_ack(priv, timeout,
0111                        FREEZE_CSR_STATUS_FREEZE_REQ_DONE);
0112
0113     if (ret)
0114         writel(0, csr_ctrl_addr);
0115     else
0116         writel(FREEZE_CSR_CTRL_RESET_REQ, csr_ctrl_addr);
0117
0118     return ret;
0119 }
0120
0121 static int altera_freeze_br_do_unfreeze(struct altera_freeze_br_data *priv,
0122                     u32 timeout)
0123 {
0124     struct device *dev = priv->dev;
0125     void __iomem *csr_ctrl_addr = priv->base_addr +
0126                       FREEZE_CSR_CTRL_OFFSET;
0127     u32 status;
0128     int ret;
0129
0130     writel(0, csr_ctrl_addr);
0131
0132     status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
0133
0134     dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
0135
0136     if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE) {
0137         dev_dbg(dev, "%s bridge already enabled %d\n",
0138             __func__, status);
0139         return 0;
0140     } else if (!(status & FREEZE_CSR_STATUS_FREEZE_REQ_DONE)) {
0141         dev_err(dev, "%s bridge not frozen %d\n", __func__, status);
0142         return -EINVAL;
0143     }
0144
0145     writel(FREEZE_CSR_CTRL_UNFREEZE_REQ, csr_ctrl_addr);
0146
0147     ret = altera_freeze_br_req_ack(priv, timeout,
0148                        FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE);
0149
0150     status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET);
0151
0152     dev_dbg(dev, "%s %d %d\n", __func__, status, readl(csr_ctrl_addr));
0153
0154     writel(0, csr_ctrl_addr);
0155
0156     return ret;
0157 }
0158
0159 /*
0160  * enable = 1 : allow traffic through the bridge
0161  * enable = 0 : disable traffic through the bridge
0162  */
0163 static int altera_freeze_br_enable_set(struct fpga_bridge *bridge,
0164                        bool enable)
0165 {
0166     struct altera_freeze_br_data *priv = bridge->priv;
0167     struct fpga_image_info *info = bridge->info;
0168     u32 timeout = 0;
0169     int ret;
0170
0171     if (enable) {
0172         if (info)
0173             timeout = info->enable_timeout_us;
0174
0175         ret = altera_freeze_br_do_unfreeze(bridge->priv, timeout);
0176     } else {
0177         if (info)
0178             timeout = info->disable_timeout_us;
0179
0180         ret = altera_freeze_br_do_freeze(bridge->priv, timeout);
0181     }
0182
0183     if (!ret)
0184         priv->enable = enable;
0185
0186     return ret;
0187 }
0188
0189 static int altera_freeze_br_enable_show(struct fpga_bridge *bridge)
0190 {
0191     struct altera_freeze_br_data *priv = bridge->priv;
0192
0193     return priv->enable;
0194 }
0195
0196 static const struct fpga_bridge_ops altera_freeze_br_br_ops = {
0197     .enable_set = altera_freeze_br_enable_set,
0198     .enable_show = altera_freeze_br_enable_show,
0199 };
0200
0201 #ifdef CONFIG_OF
0202 static const struct of_device_id altera_freeze_br_of_match[] = {
0203     { .compatible = "altr,freeze-bridge-controller", },
0204     {},
0205 };
0206 MODULE_DEVICE_TABLE(of, altera_freeze_br_of_match);
0207 #endif
0208
0209 static int altera_freeze_br_probe(struct platform_device *pdev)
0210 {
0211     struct device *dev = &pdev->dev;
0212     struct device_node *np = pdev->dev.of_node;
0213     void __iomem *base_addr;
0214     struct altera_freeze_br_data *priv;
0215     struct fpga_bridge *br;
0216     struct resource *res;
0217     u32 status, revision;
0218
0219     if (!np)
0220         return -ENODEV;
0221
0222     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0223     base_addr = devm_ioremap_resource(dev, res);
0224     if (IS_ERR(base_addr))
0225         return PTR_ERR(base_addr);
0226
0227     revision = readl(base_addr + FREEZE_CSR_REG_VERSION);
0228     if ((revision != FREEZE_CSR_SUPPORTED_VERSION) &&
0229         (revision != FREEZE_CSR_OFFICIAL_VERSION)) {
0230         dev_err(dev,
0231             "%s unexpected revision 0x%x != 0x%x != 0x%x\n",
0232             __func__, revision, FREEZE_CSR_SUPPORTED_VERSION,
0233             FREEZE_CSR_OFFICIAL_VERSION);
0234         return -EINVAL;
0235     }
0236
0237     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0238     if (!priv)
0239         return -ENOMEM;
0240
0241     priv->dev = dev;
0242
0243     status = readl(base_addr + FREEZE_CSR_STATUS_OFFSET);
0244     if (status & FREEZE_CSR_STATUS_UNFREEZE_REQ_DONE)
0245         priv->enable = 1;
0246
0247     priv->base_addr = base_addr;
0248
0249     br = fpga_bridge_register(dev, FREEZE_BRIDGE_NAME,
0250                   &altera_freeze_br_br_ops, priv);
0251     if (IS_ERR(br))
0252         return PTR_ERR(br);
0253
0254     platform_set_drvdata(pdev, br);
0255
0256     return 0;
0257 }
0258
0259 static int altera_freeze_br_remove(struct platform_device *pdev)
0260 {
0261     struct fpga_bridge *br = platform_get_drvdata(pdev);
0262
0263     fpga_bridge_unregister(br);
0264
0265     return 0;
0266 }
0267
0268 static struct platform_driver altera_freeze_br_driver = {
0269     .probe = altera_freeze_br_probe,
0270     .remove = altera_freeze_br_remove,
0271     .driver = {
0272         .name   = "altera_freeze_br",
0273         .of_match_table = of_match_ptr(altera_freeze_br_of_match),
0274     },
0275 };
0276
0277 module_platform_driver(altera_freeze_br_driver);
0278
0279 MODULE_DESCRIPTION("Altera Freeze Bridge");
0280 MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
0281 MODULE_LICENSE("GPL v2");